diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-10 11:57:37 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-10 11:57:37 -0400 |
| commit | d6283445744d5be2a9ac33f0adbc729d48e22c40 (patch) | |
| tree | 67910602fd144f50fa86b1c8a90e0e4f0e66ee90 /tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt | |
| parent | cf5935445f23d0ba2f41debc50952fe45d7c9f4a (diff) | |
| download | gem5-d6283445744d5be2a9ac33f0adbc729d48e22c40.tar.xz | |
Device: Update stats for PIO and PCI latency change
This patch merely updates the regression stats to reflect the change
in PIO and PCI latency.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt | 900 |
1 files changed, 450 insertions, 450 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index c7cd1312f..9ccbe5ddb 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.920853 # Number of seconds simulated -sim_ticks 1920853042000 # Number of ticks simulated -final_tick 1920853042000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.921792 # Number of seconds simulated +sim_ticks 1921792488000 # Number of ticks simulated +final_tick 1921792488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1381815 # Simulator instruction rate (inst/s) -host_op_rate 1381815 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47239093914 # Simulator tick rate (ticks/s) -host_mem_usage 299308 # Number of bytes of host memory used -host_seconds 40.66 # Real time elapsed on the host -sim_insts 56187824 # Number of instructions simulated -sim_ops 56187824 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24847552 # Number of bytes read from this memory +host_inst_rate 1964765 # Simulator instruction rate (inst/s) +host_op_rate 1964764 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67191639126 # Simulator tick rate (ticks/s) +host_mem_usage 295072 # Number of bytes of host memory used +host_seconds 28.60 # Real time elapsed on the host +sim_insts 56195476 # Number of instructions simulated +sim_ops 56195476 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24858752 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28350592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850688 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7389056 # Number of bytes written to this memory -system.physmem.bytes_written::total 7389056 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13292 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388243 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28361728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7403520 # Number of bytes written to this memory +system.physmem.bytes_written::total 7403520 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388418 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 442978 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115454 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115454 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12935686 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1380820 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14759376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442870 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442870 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3846758 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3846758 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3846758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12935686 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1380820 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18606133 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 336066 # number of replacements -system.l2c.tagsinuse 65311.806529 # Cycle average of tags in use -system.l2c.total_refs 2448197 # Total number of references to valid blocks. -system.l2c.sampled_refs 401228 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.101760 # Average number of references to valid blocks. -system.l2c.warmup_cycle 5946056000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55675.727094 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 4768.395922 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 4867.683513 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.849544 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.072760 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.074275 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996579 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 916208 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 814933 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1731141 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835149 # number of Writeback hits -system.l2c.Writeback_hits::total 835149 # number of Writeback hits +system.physmem.num_reads::total 443152 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115680 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115680 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12935191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1380145 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14757955 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3852403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3852403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3852403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12935191 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1380145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18610359 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 336240 # number of replacements +system.l2c.tagsinuse 65308.066862 # Cycle average of tags in use +system.l2c.total_refs 2448422 # Total number of references to valid blocks. +system.l2c.sampled_refs 401402 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.099676 # Average number of references to valid blocks. +system.l2c.warmup_cycle 6040304000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 55651.693971 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 4767.859045 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 4888.513847 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.849177 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.072752 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.074593 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.996522 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 916493 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 814973 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1731466 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835196 # number of Writeback hits +system.l2c.Writeback_hits::total 835196 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 187605 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 187605 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 916208 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1002538 # number of demand (read+write) hits -system.l2c.demand_hits::total 1918746 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 916208 # number of overall hits -system.l2c.overall_hits::cpu.data 1002538 # number of overall hits -system.l2c.overall_hits::total 1918746 # number of overall hits -system.l2c.ReadReq_misses::cpu.inst 13292 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 271915 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285207 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu.data 187534 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 187534 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 916493 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1002507 # number of demand (read+write) hits +system.l2c.demand_hits::total 1919000 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.inst 916493 # number of overall hits +system.l2c.overall_hits::cpu.data 1002507 # number of overall hits +system.l2c.overall_hits::total 1919000 # number of overall hits +system.l2c.ReadReq_misses::cpu.inst 13291 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 271963 # number of ReadReq misses +system.l2c.ReadReq_misses::total 285254 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu.data 14 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 14 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 116718 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 116718 # number of ReadExReq misses -system.l2c.demand_misses::cpu.inst 13292 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 388633 # number of demand (read+write) misses -system.l2c.demand_misses::total 401925 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.inst 13292 # number of overall misses -system.l2c.overall_misses::cpu.data 388633 # number of overall misses -system.l2c.overall_misses::total 401925 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.inst 691773000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 14144855000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 14836628000 # number of ReadReq miss cycles +system.l2c.ReadExReq_misses::cpu.data 116845 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 116845 # number of ReadExReq misses +system.l2c.demand_misses::cpu.inst 13291 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 388808 # number of demand (read+write) misses +system.l2c.demand_misses::total 402099 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.inst 13291 # number of overall misses +system.l2c.overall_misses::cpu.data 388808 # number of overall misses +system.l2c.overall_misses::total 402099 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.inst 691744000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 14147302000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 14839046000 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu.data 320000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 320000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6070015000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6070015000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.inst 691773000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 20214870000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 20906643000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.inst 691773000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 20214870000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 20906643000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.inst 929500 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1086848 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2016348 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 835149 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835149 # number of Writeback accesses(hits+misses) +system.l2c.ReadExReq_miss_latency::cpu.data 6076563000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6076563000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.inst 691744000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 20223865000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 20915609000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.inst 691744000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 20223865000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 20915609000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.inst 929784 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1086936 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2016720 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 835196 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 835196 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu.data 18 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 304323 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 304323 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.inst 929500 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1391171 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2320671 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.inst 929500 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1391171 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2320671 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.014300 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.250187 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.141447 # miss rate for ReadReq accesses +system.l2c.ReadExReq_accesses::cpu.data 304379 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 304379 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.inst 929784 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1391315 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2321099 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.inst 929784 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1391315 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2321099 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.014295 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.250211 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.141445 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.777778 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.777778 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.383533 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.383533 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.inst 0.014300 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.279357 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.173193 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.inst 0.014300 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.279357 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.173193 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52044.312368 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.399445 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52020.560505 # average ReadReq miss latency +system.l2c.ReadExReq_miss_rate::cpu.data 0.383880 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.383880 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.inst 0.014295 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.279454 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.173236 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.inst 0.014295 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.279454 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.173236 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52046.046197 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.215849 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52020.465971 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu.data 22857.142857 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 22857.142857 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.817440 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52005.817440 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52044.312368 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52015.320367 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52016.279157 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52044.312368 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52015.320367 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52016.279157 # average overall miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.331850 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52005.331850 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52046.046197 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52015.043415 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52016.068182 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52046.046197 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52015.043415 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52016.068182 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -141,66 +141,66 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 73942 # number of writebacks -system.l2c.writebacks::total 73942 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu.inst 13292 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 271915 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 285207 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 74168 # number of writebacks +system.l2c.writebacks::total 74168 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu.inst 13291 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 271963 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 285254 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 116718 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 116718 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 13292 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 388633 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 401925 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 13292 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 388633 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 401925 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 532266000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 10881875000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 11414141000 # number of ReadReq MSHR miss cycles +system.l2c.ReadExReq_mshr_misses::cpu.data 116845 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 116845 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 13291 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 388808 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 402099 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 13291 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 388808 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 402099 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 532249000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 10883746000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 11415995000 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 620000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 620000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4669399000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4669399000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 532266000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 15551274000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16083540000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 532266000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 15551274000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16083540000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 772639030 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 772639030 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1072677000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1072677000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 1845316030 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1845316030 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250187 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.141447 # mshr miss rate for ReadReq accesses +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4674423000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4674423000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 532249000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 15558169000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16090418000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 532249000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 15558169000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16090418000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 1331550000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1331550000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1893145000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1893145000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 3224695000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3224695000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014295 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250211 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.141445 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.777778 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.777778 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383533 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.383533 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.279357 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.173193 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.279357 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173193 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40044.086669 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.399445 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.549987 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383880 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.383880 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.014295 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.279454 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173236 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.014295 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.279454 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173236 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.820480 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.215849 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.455454 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 44285.714286 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44285.714286 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.817440 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.817440 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40044.086669 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.320367 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40016.271692 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40044.086669 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.320367 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40016.271692 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.331850 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.331850 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40045.820480 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.043415 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40016.060721 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40045.820480 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.043415 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40016.060721 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -209,14 +209,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.356968 # Cycle average of tags in use +system.iocache.tagsinuse 1.355427 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1753491316000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.356968 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.084811 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.084811 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1754498131000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.355427 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.084714 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.084714 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -227,12 +227,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 7638105806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 7638105806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 7658778804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7658778804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 7658778804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7658778804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 7634106806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 7634106806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 7654779804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7654779804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 7654779804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7654779804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -251,17 +251,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183820.413121 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 183820.413121 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 183553.716093 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183553.716093 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 183553.716093 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183553.716093 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7453000 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183724.172266 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 183724.172266 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 183457.874272 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183457.874272 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 183457.874272 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183457.874272 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7454000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7118 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7097 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 1047.063782 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 1050.302945 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -277,12 +277,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5477251000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5477251000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5488927000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5488927000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5488927000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5488927000 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5473252000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 5473252000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5484928000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5484928000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5484928000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5484928000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -293,12 +293,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131816.783789 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 131816.783789 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131550.077891 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131550.077891 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131550.077891 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131550.077891 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131720.542934 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 131720.542934 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131454.236070 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131454.236070 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131454.236070 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131454.236070 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -316,22 +316,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9065773 # DTB read hits +system.cpu.dtb.read_hits 9066933 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6357048 # DTB write hits +system.cpu.dtb.write_hits 6357519 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15422821 # DTB hits +system.cpu.dtb.data_hits 15424452 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4975760 # ITB hits +system.cpu.itb.fetch_hits 4975863 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4980766 # ITB accesses +system.cpu.itb.fetch_accesses 4980869 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -344,51 +344,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3841706084 # number of cpu cycles simulated +system.cpu.numCycles 3843584976 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56187824 # Number of instructions committed -system.cpu.committedOps 56187824 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52059470 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses -system.cpu.num_func_calls 1483670 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6469221 # number of instructions that are conditional controls -system.cpu.num_int_insts 52059470 # number of integer instructions -system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 71329755 # number of times the integer registers were read -system.cpu.num_int_register_writes 38524240 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 15475451 # number of memory refs -system.cpu.num_load_insts 9102635 # Number of load instructions -system.cpu.num_store_insts 6372816 # Number of store instructions -system.cpu.num_idle_cycles 3589579952.998131 # Number of idle cycles -system.cpu.num_busy_cycles 252126131.001869 # Number of busy cycles -system.cpu.not_idle_fraction 0.065629 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934371 # Percentage of idle cycles +system.cpu.committedInsts 56195476 # Number of instructions committed +system.cpu.committedOps 56195476 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52066692 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses +system.cpu.num_func_calls 1483822 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6469666 # number of instructions that are conditional controls +system.cpu.num_int_insts 52066692 # number of integer instructions +system.cpu.num_fp_insts 324259 # number of float instructions +system.cpu.num_int_register_reads 71339619 # number of times the integer registers were read +system.cpu.num_int_register_writes 38530592 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written +system.cpu.num_mem_refs 15477059 # number of memory refs +system.cpu.num_load_insts 9103780 # Number of load instructions +system.cpu.num_store_insts 6373279 # Number of store instructions +system.cpu.num_idle_cycles 3588655153.998133 # Number of idle cycles +system.cpu.num_busy_cycles 254929822.001867 # Number of busy cycles +system.cpu.not_idle_fraction 0.066326 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.933674 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212104 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74929 40.88% 40.88% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212119 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74932 40.88% 40.88% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1936 1.06% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106285 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183281 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73562 49.31% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1936 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73562 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149191 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1861395652500 96.90% 96.90% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 90398000 0.00% 96.91% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 587366500 0.03% 96.94% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 58778792000 3.06% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1920852209000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_count::22 1937 1.06% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106298 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183298 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73565 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1937 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73565 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149198 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1861046523500 96.84% 96.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 104284500 0.01% 96.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 779455000 0.04% 96.89% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 59861392000 3.11% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1921791655000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981757 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692120 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814001 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692064 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.813964 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -424,33 +424,33 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4177 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4174 2.16% 2.16% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 176052 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6837 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 176067 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6838 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5161 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5162 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 193007 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5906 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1908 -system.cpu.kern.mode_good::user 1738 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.323061 # fraction of useful protection mode switches +system.cpu.kern.callpal::total 193021 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5905 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1740 +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.323285 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.391706 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46234707000 2.41% 2.41% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5259387000 0.27% 2.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1869358108000 97.32% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.080591 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.391911 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46687559000 2.43% 2.43% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5260775000 0.27% 2.70% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1869843314000 97.30% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -482,51 +482,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 928849 # number of replacements -system.cpu.icache.tagsinuse 508.732123 # Cycle average of tags in use -system.cpu.icache.total_refs 55270143 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 929360 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.471188 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 35877190000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 508.732123 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.993617 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.993617 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55270143 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55270143 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55270143 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55270143 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55270143 # number of overall hits -system.cpu.icache.overall_hits::total 55270143 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929520 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929520 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929520 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929520 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929520 # number of overall misses -system.cpu.icache.overall_misses::total 929520 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13854449500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13854449500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13854449500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13854449500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13854449500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13854449500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56199663 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56199663 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56199663 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56199663 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56199663 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56199663 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016540 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016540 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016540 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016540 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016540 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.950405 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14904.950405 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.950405 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14904.950405 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.950405 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14904.950405 # average overall miss latency +system.cpu.icache.replacements 929133 # number of replacements +system.cpu.icache.tagsinuse 508.706285 # Cycle average of tags in use +system.cpu.icache.total_refs 55277511 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 929644 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 59.460945 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 36213864000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 508.706285 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.993567 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.993567 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55277511 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55277511 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55277511 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55277511 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55277511 # number of overall hits +system.cpu.icache.overall_hits::total 55277511 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929804 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929804 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929804 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929804 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929804 # number of overall misses +system.cpu.icache.overall_misses::total 929804 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13857748000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13857748000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13857748000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13857748000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13857748000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13857748000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56207315 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56207315 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56207315 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56207315 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56207315 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56207315 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016542 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016542 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016542 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016542 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016542 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016542 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14903.945348 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14903.945348 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14903.945348 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14903.945348 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14903.945348 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14903.945348 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -535,104 +535,104 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929520 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929520 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929520 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929520 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929520 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929520 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11065203000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11065203000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11065203000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11065203000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11065203000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11065203000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016540 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016540 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016540 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11904.211851 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11904.211851 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11904.211851 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11904.211851 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11904.211851 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11904.211851 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929804 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016542 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016542 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016542 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11903.206482 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11903.206482 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11903.206482 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11903.206482 # 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mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086498 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086498 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091333 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091333 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21923.254501 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21923.254501 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27336.996987 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27336.996987 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11342.202470 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11342.202470 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23122.518039 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23122.518039 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23122.518039 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23122.518039 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049432 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049432 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086236 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086236 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091337 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091337 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21923.723640 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21923.723640 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27350.795179 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27350.795179 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11341.168297 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11341.168297 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23125.988676 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23125.988676 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23125.988676 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23125.988676 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |