diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing')
3 files changed, 314 insertions, 401 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 54195aa23..c8fe39e38 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -68,6 +69,7 @@ profile=0 progress_interval=0 system=system tracer=system.cpu.tracer +workload= dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -82,20 +84,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -118,20 +113,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -215,20 +203,13 @@ is_top_level=true latency=50000 max_miss_count=0 mshrs=20 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=500000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -247,20 +228,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false @@ -286,7 +260,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -356,7 +329,6 @@ pio=system.iobus.port[25] type=TsunamiCChip pio_addr=8803072344064 pio_latency=1000 -platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.port[1] @@ -438,7 +410,6 @@ fake_mem=false pio_addr=8796093677568 pio_latency=1000 pio_size=393216 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -455,7 +426,6 @@ fake_mem=false pio_addr=8804615848432 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -472,7 +442,6 @@ fake_mem=false pio_addr=8804615848304 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -489,7 +458,6 @@ fake_mem=false pio_addr=8804615848569 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -506,7 +474,6 @@ fake_mem=false pio_addr=8804615848451 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -523,7 +490,6 @@ fake_mem=false pio_addr=8804615848515 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -540,7 +506,6 @@ fake_mem=false pio_addr=8804615848579 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -557,7 +522,6 @@ fake_mem=false pio_addr=8804615848643 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -574,7 +538,6 @@ fake_mem=false pio_addr=8804615848707 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -591,7 +554,6 @@ fake_mem=false pio_addr=8804615848771 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -608,7 +570,6 @@ fake_mem=false pio_addr=8804615848835 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -625,7 +586,6 @@ fake_mem=false pio_addr=8804615848899 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -642,7 +602,6 @@ fake_mem=false pio_addr=8804615850617 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -659,7 +618,6 @@ fake_mem=false pio_addr=8804615848891 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -676,7 +634,6 @@ fake_mem=false pio_addr=8804615848816 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -693,7 +650,6 @@ fake_mem=false pio_addr=8804615848696 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -710,7 +666,6 @@ fake_mem=false pio_addr=8804615848936 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -727,7 +682,6 @@ fake_mem=false pio_addr=8804615848680 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -744,7 +698,6 @@ fake_mem=false pio_addr=8804615848944 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -760,7 +713,6 @@ type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 pio_latency=1000 -platform=system.tsunami system=system pio=system.iobus.port[22] @@ -825,7 +777,6 @@ type=TsunamiIO frequency=976562500 pio_addr=8804615847936 pio_latency=1000 -platform=system.tsunami system=system time=Thu Jan 1 00:00:00 2009 tsunami=system.tsunami @@ -836,7 +787,6 @@ pio=system.iobus.port[23] type=TsunamiPChip pio_addr=8802535473152 pio_latency=1000 -platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.port[2] diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index 826f2c28b..e3d6e41ac 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -1,12 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:53:29 -gem5 started Jan 23 2012 04:22:43 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:47 gem5 executing on zizzer -command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1915548867000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index ac9598c08..713b264a4 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 1.915549 # Nu sim_ticks 1915548867000 # Number of ticks simulated final_tick 1915548867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1659827 # Simulator instruction rate (inst/s) -host_tick_rate 56637748152 # Simulator tick rate (ticks/s) -host_mem_usage 290988 # Number of bytes of host memory used -host_seconds 33.82 # Real time elapsed on the host +host_inst_rate 1998214 # Simulator instruction rate (inst/s) +host_op_rate 1998212 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68184353129 # Simulator tick rate (ticks/s) +host_mem_usage 288188 # Number of bytes of host memory used +host_seconds 28.09 # Real time elapsed on the host sim_insts 56137087 # Number of instructions simulated +sim_ops 56137087 # Number of ops (including micro ops) simulated system.physmem.bytes_read 29663360 # Number of bytes read from this memory system.physmem.bytes_inst_read 943040 # Number of instructions bytes read from this memory system.physmem.bytes_written 10122368 # Number of bytes written to this memory @@ -25,79 +27,85 @@ system.l2c.total_refs 2311163 # To system.l2c.sampled_refs 421794 # Sample count of references to valid blocks. system.l2c.avg_refs 5.479364 # Average number of references to valid blocks. system.l2c.warmup_cycle 6937912000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11241.373247 # Average occupied blocks per context -system.l2c.occ_blocks::1 23110.665097 # Average occupied blocks per context -system.l2c.occ_percent::0 0.171530 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.352641 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1710461 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 23110.665097 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 3746.363547 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 7495.009700 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.352641 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.057165 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.114365 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.524171 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 913599 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 796862 # number of ReadReq hits system.l2c.ReadReq_hits::total 1710461 # number of ReadReq hits -system.l2c.Writeback_hits::0 826671 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 826671 # number of Writeback hits system.l2c.Writeback_hits::total 826671 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 6 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu.data 6 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 6 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 185878 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu.data 185878 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 185878 # number of ReadExReq hits -system.l2c.demand_hits::0 1896339 # number of demand (read+write) hits -system.l2c.demand_hits::1 0 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 913599 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 982740 # number of demand (read+write) hits system.l2c.demand_hits::total 1896339 # number of demand (read+write) hits -system.l2c.overall_hits::0 1896339 # number of overall hits -system.l2c.overall_hits::1 0 # number of overall hits +system.l2c.overall_hits::cpu.inst 913599 # number of overall hits +system.l2c.overall_hits::cpu.data 982740 # number of overall hits system.l2c.overall_hits::total 1896339 # number of overall hits -system.l2c.ReadReq_misses::0 304138 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 14735 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 289403 # number of ReadReq misses system.l2c.ReadReq_misses::total 304138 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 7 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 7 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 118294 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu.data 118294 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 118294 # number of ReadExReq misses -system.l2c.demand_misses::0 422432 # number of demand (read+write) misses -system.l2c.demand_misses::1 0 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 14735 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 407697 # number of demand (read+write) misses system.l2c.demand_misses::total 422432 # number of demand (read+write) misses -system.l2c.overall_misses::0 422432 # number of overall misses -system.l2c.overall_misses::1 0 # number of overall misses +system.l2c.overall_misses::cpu.inst 14735 # number of overall misses +system.l2c.overall_misses::cpu.data 407697 # number of overall misses system.l2c.overall_misses::total 422432 # number of overall misses -system.l2c.ReadReq_miss_latency 15820206500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 248000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6151753000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 21971959500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 21971959500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2014599 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_miss_latency::cpu.inst 766261500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 15053945000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 15820206500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 248000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 248000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6151753000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6151753000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.inst 766261500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 21205698000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21971959500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.inst 766261500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 21205698000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21971959500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.inst 928334 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1086265 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2014599 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 826671 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 826671 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 826671 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 13 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 304172 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 304172 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 304172 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2318771 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 928334 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1390437 # number of demand (read+write) accesses system.l2c.demand_accesses::total 2318771 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2318771 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 928334 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1390437 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2318771 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.150967 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.538462 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.388905 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.182179 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses -system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.182179 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses -system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52016.540189 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 35428.571429 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52003.930884 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52013.009194 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency -system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52013.009194 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency -system.l2c.overall_avg_miss_latency::total inf # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu.inst 0.015873 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.266420 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.538462 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.388905 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.inst 0.015873 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.293215 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.inst 0.015873 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.293215 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52002.816423 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52017.238937 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 35428.571429 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52003.930884 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -106,48 +114,59 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 116650 # number of writebacks -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 304138 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 7 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 118294 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 422432 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 422432 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12170545000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 320000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 4732225000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 16902770000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 16902770000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 772673000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1083819500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 1856492500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.150967 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.538462 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.388905 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.182179 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.182179 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40016.522105 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 45714.285714 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40003.930884 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40012.996175 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40012.996175 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.writebacks::writebacks 116650 # number of writebacks +system.l2c.writebacks::total 116650 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu.inst 14735 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 289403 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 304138 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 7 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 7 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 118294 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 118294 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 14735 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 407697 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 422432 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 14735 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 407697 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 422432 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 589436000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 11581109000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 12170545000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 320000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 320000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4732225000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4732225000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 589436000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 16313334000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16902770000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 589436000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 16313334000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16902770000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 772673000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 772673000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1083819500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1083819500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 1856492500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1856492500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.266420 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.538462 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.388905 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.443163 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40017.238937 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 45714.285714 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40003.930884 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements system.iocache.tagsinuse 1.340325 # Cycle average of tags in use @@ -155,58 +174,41 @@ system.iocache.total_refs 0 # To system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1750545944000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 1.340325 # Average occupied blocks per context -system.iocache.occ_percent::1 0.083770 # Average percentage of cache occupancy -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 173 # number of ReadReq misses +system.iocache.occ_blocks::tsunami.ide 1.340325 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.083770 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.083770 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses +system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41725 # number of demand (read+write) misses +system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41725 # number of overall misses +system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency 19940998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5722300806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5742241804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5742241804 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_miss_latency::tsunami.ide 19940998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 19940998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5722300806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5722300806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5742241804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5742241804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5742241804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5742241804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115265.884393 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137714.208847 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137621.133709 # average overall miss latency -system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137621.133709 # average overall miss latency -system.iocache.overall_avg_miss_latency::total inf # average overall miss latency +system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115265.884393 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137714.208847 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 64604060 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked @@ -215,38 +217,32 @@ system.iocache.avg_blocked_cycles::no_mshrs 6166.863307 # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 41512 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 10944998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3561447990 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3572392988 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3572392988 # number of overall MSHR miss cycles -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 63265.884393 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85710.627407 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85617.567118 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85617.567118 # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.writebacks::writebacks 41512 # number of writebacks +system.iocache.writebacks::total 41512 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10944998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 10944998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561447990 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3561447990 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3572392988 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3572392988 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3572392988 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3572392988 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63265.884393 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85710.627407 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -295,7 +291,8 @@ system.cpu.itb.data_accesses 0 # DT system.cpu.numCycles 3831097734 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 56137087 # Number of instructions executed +system.cpu.committedInsts 56137087 # Number of instructions committed +system.cpu.committedOps 56137087 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 52011214 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324192 # Number of float alu accesses system.cpu.num_func_calls 1482242 # number of times a function call or return occured @@ -434,51 +431,39 @@ system.cpu.icache.total_refs 55220553 # To system.cpu.icache.sampled_refs 928194 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 59.492469 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 36307428000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 508.721464 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.993597 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 55220553 # number of ReadReq hits +system.cpu.icache.occ_blocks::cpu.inst 508.721464 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.993597 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.993597 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55220553 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 55220553 # number of ReadReq hits -system.cpu.icache.demand_hits::0 55220553 # number of demand (read+write) hits -system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::cpu.inst 55220553 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 55220553 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 55220553 # number of overall hits -system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::cpu.inst 55220553 # number of overall hits system.cpu.icache.overall_hits::total 55220553 # number of overall hits -system.cpu.icache.ReadReq_misses::0 928354 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::cpu.inst 928354 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 928354 # number of ReadReq misses -system.cpu.icache.demand_misses::0 928354 # number of demand (read+write) misses -system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::cpu.inst 928354 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 928354 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 928354 # number of overall misses -system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::cpu.inst 928354 # number of overall misses system.cpu.icache.overall_misses::total 928354 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 13616370500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 13616370500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 13616370500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 56148907 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13616370500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13616370500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13616370500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13616370500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13616370500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13616370500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56148907 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 56148907 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 56148907 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::cpu.inst 56148907 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 56148907 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 56148907 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56148907 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 56148907 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.016534 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.016534 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.016534 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14667.218001 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14667.218001 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14667.218001 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016534 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016534 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016534 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14667.218001 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -487,32 +472,26 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 85 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 928354 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 928354 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 928354 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 10830625500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 10830625500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 10830625500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.016534 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.016534 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.016534 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11666.482290 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11666.482290 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11666.482290 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.writebacks::writebacks 85 # number of writebacks +system.cpu.icache.writebacks::total 85 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928354 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 928354 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 928354 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 928354 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 928354 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 928354 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10830625500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10830625500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10830625500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10830625500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10830625500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10830625500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11666.482290 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1390115 # number of replacements system.cpu.dcache.tagsinuse 511.984023 # Cycle average of tags in use @@ -520,77 +499,63 @@ system.cpu.dcache.total_refs 14038335 # To system.cpu.dcache.sampled_refs 1390627 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 10.094968 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 84029000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.984023 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999969 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 7807536 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 511.984023 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999969 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999969 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7807536 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 7807536 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 5848554 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848554 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 5848554 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 183025 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183025 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 183025 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 199203 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199203 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199203 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 13656090 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 13656090 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 13656090 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 13656090 # number of overall hits -system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 13656090 # number of overall hits system.cpu.dcache.overall_hits::total 13656090 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 1069110 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 1069110 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1069110 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 304335 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304335 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 304335 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 17201 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17201 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17201 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::0 1373445 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 1373445 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1373445 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 1373445 # number of overall misses -system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 1373445 # number of overall misses system.cpu.dcache.overall_misses::total 1373445 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 27121920500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 9228484000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 245980000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 36350404500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 36350404500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 8876646 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 27121920500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 27121920500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9228484000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9228484000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 245980000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 245980000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36350404500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36350404500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36350404500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36350404500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8876646 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 8876646 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 6152889 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152889 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6152889 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 200226 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200226 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 200226 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 199203 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199203 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 199203 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 15029535 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 15029535 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 15029535 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 15029535 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15029535 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15029535 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.120441 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.049462 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.085908 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::0 0.091383 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.091383 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 25368.690313 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 30323.439631 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14300.331376 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 26466.589124 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 26466.589124 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120441 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049462 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085908 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091383 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091383 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25368.690313 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30323.439631 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14300.331376 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -599,48 +564,47 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 826586 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1069110 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 304335 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 17201 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1373445 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1373445 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 23914545000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8315479000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 194377000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 32230024000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 32230024000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 862763000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1199607500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 2062370500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.120441 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.049462 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.085908 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.091383 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.091383 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22368.647754 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27323.439631 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11300.331376 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23466.555996 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23466.555996 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 826586 # number of writebacks +system.cpu.dcache.writebacks::total 826586 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069110 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069110 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304335 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304335 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17201 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17201 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373445 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373445 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373445 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373445 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23914545000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23914545000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8315479000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8315479000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194377000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194377000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32230024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 32230024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32230024000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 32230024000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 862763000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 862763000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1199607500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1199607500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2062370500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 2062370500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120441 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049462 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085908 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22368.647754 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27323.439631 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11300.331376 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |