diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
| commit | a217eba078b17c51f6a74c9237584f066ef78bf1 (patch) | |
| tree | e566cbeb3520341dbdf6ecb0d3932a31d4e156fe /tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing | |
| parent | db430698bfd4d77a49e11031bb65444552891f37 (diff) | |
| download | gem5-a217eba078b17c51f6a74c9237584f066ef78bf1.tar.xz | |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt | 1465 |
1 files changed, 729 insertions, 736 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 24f1d16b8..7916cb036 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,127 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.919447 # Number of seconds simulated -sim_ticks 1919446558000 # Number of ticks simulated -final_tick 1919446558000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.919439 # Number of seconds simulated +sim_ticks 1919438772000 # Number of ticks simulated +final_tick 1919438772000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 885398 # Simulator instruction rate (inst/s) -host_op_rate 885398 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30291378157 # Simulator tick rate (ticks/s) -host_mem_usage 344696 # Number of bytes of host memory used -host_seconds 63.37 # Real time elapsed on the host -sim_insts 56104177 # Number of instructions simulated -sim_ops 56104177 # Number of ops (including micro ops) simulated +host_inst_rate 1398299 # Simulator instruction rate (inst/s) +host_op_rate 1398299 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47840414078 # Simulator tick rate (ticks/s) +host_mem_usage 314348 # Number of bytes of host memory used +host_seconds 40.12 # Real time elapsed on the host +sim_insts 56102112 # Number of instructions simulated +sim_ops 56102112 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24858240 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28361344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7404032 # Number of bytes written to this memory -system.physmem.bytes_written::total 7404032 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388410 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443146 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115688 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115688 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 443228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12950733 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1381832 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14775792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 443228 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443228 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3857379 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3857379 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3857379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 443228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12950733 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1381832 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18633171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 443146 # Number of read requests accepted -system.physmem.writeReqs 115688 # Number of write requests accepted -system.physmem.readBursts 443146 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115688 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28353856 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue -system.physmem.bytesWritten 7402304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28361344 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7404032 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 850816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24875968 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 25727744 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850816 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4747712 # Number of bytes written to this memory +system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory +system.physmem.bytes_written::total 7407040 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13294 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388687 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 401996 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 74183 # Number of write requests responded to by this memory +system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115735 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 443263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12960022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13403785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 443263 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 443263 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2473490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1385472 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3858961 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2473490 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 443263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12960022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1385972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17262746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401996 # Number of read requests accepted +system.physmem.writeReqs 115735 # Number of write requests accepted +system.physmem.readBursts 401996 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115735 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25716224 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11520 # Total number of bytes read from write queue +system.physmem.bytesWritten 7405312 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25727744 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7407040 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 180 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 27768 # Per bank write bursts -system.physmem.perBankRdBursts::1 28019 # Per bank write bursts -system.physmem.perBankRdBursts::2 28336 # Per bank write bursts -system.physmem.perBankRdBursts::3 28020 # Per bank write bursts -system.physmem.perBankRdBursts::4 27518 # Per bank write bursts -system.physmem.perBankRdBursts::5 27546 # Per bank write bursts -system.physmem.perBankRdBursts::6 26737 # Per bank write bursts -system.physmem.perBankRdBursts::7 26852 # Per bank write bursts -system.physmem.perBankRdBursts::8 27860 # Per bank write bursts -system.physmem.perBankRdBursts::9 27104 # Per bank write bursts -system.physmem.perBankRdBursts::10 27841 # Per bank write bursts -system.physmem.perBankRdBursts::11 27413 # Per bank write bursts -system.physmem.perBankRdBursts::12 27378 # Per bank write bursts -system.physmem.perBankRdBursts::13 28201 # Per bank write bursts -system.physmem.perBankRdBursts::14 28236 # Per bank write bursts -system.physmem.perBankRdBursts::15 28200 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 132 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25161 # Per bank write bursts +system.physmem.perBankRdBursts::1 25541 # Per bank write bursts +system.physmem.perBankRdBursts::2 25618 # Per bank write bursts +system.physmem.perBankRdBursts::3 25537 # Per bank write bursts +system.physmem.perBankRdBursts::4 24981 # Per bank write bursts +system.physmem.perBankRdBursts::5 24976 # Per bank write bursts +system.physmem.perBankRdBursts::6 24228 # Per bank write bursts +system.physmem.perBankRdBursts::7 24506 # Per bank write bursts +system.physmem.perBankRdBursts::8 25159 # Per bank write bursts +system.physmem.perBankRdBursts::9 24820 # Per bank write bursts +system.physmem.perBankRdBursts::10 25363 # Per bank write bursts +system.physmem.perBankRdBursts::11 24840 # Per bank write bursts +system.physmem.perBankRdBursts::12 24420 # Per bank write bursts +system.physmem.perBankRdBursts::13 25388 # Per bank write bursts +system.physmem.perBankRdBursts::14 25795 # Per bank write bursts +system.physmem.perBankRdBursts::15 25483 # Per bank write bursts system.physmem.perBankWrBursts::0 7550 # Per bank write bursts system.physmem.perBankWrBursts::1 7529 # Per bank write bursts -system.physmem.perBankWrBursts::2 7869 # Per bank write bursts -system.physmem.perBankWrBursts::3 7540 # Per bank write bursts +system.physmem.perBankWrBursts::2 7880 # Per bank write bursts +system.physmem.perBankWrBursts::3 7553 # Per bank write bursts system.physmem.perBankWrBursts::4 7115 # Per bank write bursts system.physmem.perBankWrBursts::5 6983 # Per bank write bursts system.physmem.perBankWrBursts::6 6321 # Per bank write bursts -system.physmem.perBankWrBursts::7 6313 # Per bank write bursts +system.physmem.perBankWrBursts::7 6319 # Per bank write bursts system.physmem.perBankWrBursts::8 7293 # Per bank write bursts -system.physmem.perBankWrBursts::9 6538 # Per bank write bursts +system.physmem.perBankWrBursts::9 6554 # Per bank write bursts system.physmem.perBankWrBursts::10 7205 # Per bank write bursts system.physmem.perBankWrBursts::11 6861 # Per bank write bursts system.physmem.perBankWrBursts::12 6964 # Per bank write bursts system.physmem.perBankWrBursts::13 7821 # Per bank write bursts -system.physmem.perBankWrBursts::14 7979 # Per bank write bursts +system.physmem.perBankWrBursts::14 7980 # Per bank write bursts system.physmem.perBankWrBursts::15 7780 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 1919434637000 # Total gap between requests +system.physmem.totGap 1919426851000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 443146 # Read request sizes (log2) +system.physmem.readPktSize::6 401996 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115688 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2685 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1622 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1907 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1224 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 883 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115735 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -148,278 +151,267 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66429 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 538.261302 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 328.855989 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.099114 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14887 22.41% 22.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11472 17.27% 39.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4684 7.05% 46.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3132 4.71% 51.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3072 4.62% 56.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1874 2.82% 58.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1342 2.02% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1444 2.17% 63.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24522 36.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66429 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6775 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 65.389077 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 16.529238 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2564.130292 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 6772 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6775 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6775 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.071734 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.848509 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.695111 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 5062 74.72% 74.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 127 1.87% 76.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1207 17.82% 94.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 25 0.37% 94.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 12 0.18% 94.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 16 0.24% 95.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 18 0.27% 95.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 98 1.45% 96.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 22 0.32% 97.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 41 0.61% 97.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 20 0.30% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 8 0.12% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 7 0.10% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 8 0.12% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 7 0.10% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 15 0.22% 98.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 9 0.13% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.01% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.01% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.01% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.01% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 1 0.01% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 4 0.06% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 9 0.13% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 8 0.12% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 2 0.03% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 2 0.03% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 2 0.03% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 1 0.01% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 1 0.01% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 8 0.12% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 7 0.10% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 1 0.01% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 2 0.03% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 2 0.03% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 1 0.01% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54 1 0.01% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 7 0.10% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 9 0.13% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::59 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6775 # Writes before turning the bus around for reads -system.physmem.totQLat 7315796250 # Total ticks spent queuing -system.physmem.totMemAccLat 15622590000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2215145000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16513.13 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63869 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 518.585480 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 313.979775 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.923527 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14875 23.29% 23.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11515 18.03% 41.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4721 7.39% 48.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3142 4.92% 53.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3018 4.73% 58.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1863 2.92% 61.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1301 2.04% 63.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1404 2.20% 65.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22030 34.49% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63869 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5101 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.768477 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2955.016496 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5098 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5101 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5101 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.683395 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.235797 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.276820 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4452 87.28% 87.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 22 0.43% 87.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 15 0.29% 88.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 224 4.39% 92.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 41 0.80% 93.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 6 0.12% 93.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 9 0.18% 93.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.14% 93.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 19 0.37% 94.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.04% 94.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.08% 94.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.04% 94.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 11 0.22% 94.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.06% 94.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 7 0.14% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 30 0.59% 95.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 13 0.25% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.06% 95.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 166 3.25% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 10 0.20% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 6 0.12% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.08% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.04% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 6 0.12% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 9 0.18% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 9 0.18% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.06% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.04% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.06% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 4 0.08% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5101 # Writes before turning the bus around for reads +system.physmem.totQLat 2117396500 # Total ticks spent queuing +system.physmem.totMemAccLat 9651446500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2009080000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5269.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35263.13 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24019.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.78 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.40 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.86 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.13 # Data bus utilization in percentage +system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.40 # Average write queue length when enqueuing -system.physmem.readRowHits 398273 # Number of row buffer hits during reads -system.physmem.writeRowHits 93988 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.90 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.24 # Row buffer hit rate for writes -system.physmem.avgGap 3434713.42 # Average gap between requests -system.physmem.pageHitRate 88.11 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1800016178000 # Time in different power states -system.physmem.memoryStateTime::REF 64094420000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.42 # Average write queue length when enqueuing +system.physmem.readRowHits 360116 # Number of row buffer hits during reads +system.physmem.writeRowHits 93539 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.82 # Row buffer hit rate for writes +system.physmem.avgGap 3707382.50 # Average gap between requests +system.physmem.pageHitRate 87.65 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1800046548500 # Time in different power states +system.physmem.memoryStateTime::REF 64094160000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 55332653250 # Time in different power states +system.physmem.memoryStateTime::ACT 55294756500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 18674823 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292356 # Transaction distribution -system.membus.trans_dist::ReadResp 292356 # Transaction distribution +system.membus.throughput 17291227 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292357 # Transaction distribution +system.membus.trans_dist::ReadResp 292357 # Transaction distribution system.membus.trans_dist::WriteReq 9649 # Transaction distribution system.membus.trans_dist::WriteResp 9649 # Transaction distribution -system.membus.trans_dist::Writeback 115688 # Transaction distribution +system.membus.trans_dist::Writeback 74183 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 158273 # Transaction distribution -system.membus.trans_dist::ReadExResp 158273 # Transaction distribution +system.membus.trans_dist::ReadExReq 116727 # Transaction distribution +system.membus.trans_dist::ReadExResp 116727 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878115 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911273 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1035953 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878409 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911567 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 994859 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30456256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30500812 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 35809932 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35809932 # Total data (bytes) -system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 32376000 # Layer occupancy (ticks) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30474496 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30519052 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 33179340 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 33179340 # Total data (bytes) +system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 32375500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1491996000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1450892000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3751677600 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3751806368 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376660500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43113000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.344872 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.344805 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1753525004000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.344872 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084054 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084054 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1753524887000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.344805 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.084050 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.084050 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses -system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses -system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21253133 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21253133 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12447285431 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12447285431 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 12468538564 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12468538564 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 12468538564 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12468538564 # number of overall miss cycles +system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses +system.iocache.demand_misses::total 173 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 173 # number of overall misses +system.iocache.overall_misses::total 173 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122850.479769 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122850.479769 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299559.237365 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 299559.237365 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 298826.568340 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 298826.568340 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 298826.568340 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 298826.568340 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 365803 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28265 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.941907 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41512 # number of writebacks -system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12255133 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12255133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10284312431 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10284312431 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10296567564 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10296567564 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10296567564 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10296567564 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2506570306 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2506570306 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70838.919075 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70838.919075 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247504.631089 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 247504.631089 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246772.140539 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 246772.140539 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246772.140539 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 246772.140539 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60323.698161 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60323.698161 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -438,22 +430,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9052923 # DTB read hits -system.cpu.dtb.read_misses 10354 # DTB read misses +system.cpu.dtb.read_hits 9052614 # DTB read hits +system.cpu.dtb.read_misses 10356 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728911 # DTB read accesses -system.cpu.dtb.write_hits 6349403 # DTB write hits -system.cpu.dtb.write_misses 1143 # DTB write misses +system.cpu.dtb.read_accesses 728915 # DTB read accesses +system.cpu.dtb.write_hits 6349217 # DTB write hits +system.cpu.dtb.write_misses 1144 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291932 # DTB write accesses -system.cpu.dtb.data_hits 15402326 # DTB hits -system.cpu.dtb.data_misses 11497 # DTB misses +system.cpu.dtb.write_accesses 291933 # DTB write accesses +system.cpu.dtb.data_hits 15401831 # DTB hits +system.cpu.dtb.data_misses 11500 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020843 # DTB accesses -system.cpu.itb.fetch_hits 4974965 # ITB hits +system.cpu.dtb.data_accesses 1020848 # DTB accesses +system.cpu.itb.fetch_hits 4974960 # ITB hits system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979975 # ITB accesses +system.cpu.itb.fetch_accesses 4979970 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -466,34 +458,34 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3838893116 # number of cpu cycles simulated +system.cpu.numCycles 3838877544 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56104177 # Number of instructions committed -system.cpu.committedOps 56104177 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 51979169 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324594 # Number of float alu accesses -system.cpu.num_func_calls 1481286 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6461218 # number of instructions that are conditional controls -system.cpu.num_int_insts 51979169 # number of integer instructions -system.cpu.num_fp_insts 324594 # number of float instructions -system.cpu.num_int_register_reads 71209746 # number of times the integer registers were read -system.cpu.num_int_register_writes 38460532 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163708 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166588 # number of times the floating registers were written -system.cpu.num_mem_refs 15454993 # number of memory refs -system.cpu.num_load_insts 9089820 # Number of load instructions -system.cpu.num_store_insts 6365173 # Number of store instructions -system.cpu.num_idle_cycles 3587243859.498131 # Number of idle cycles -system.cpu.num_busy_cycles 251649256.501869 # Number of busy cycles -system.cpu.not_idle_fraction 0.065553 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934447 # Percentage of idle cycles -system.cpu.Branches 8413035 # Number of branches fetched -system.cpu.op_class::No_OpClass 3197761 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36186344 64.48% 70.18% # Class of executed instruction -system.cpu.op_class::IntMult 61011 0.11% 70.29% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.29% # Class of executed instruction -system.cpu.op_class::FloatAdd 25613 0.05% 70.34% # Class of executed instruction +system.cpu.committedInsts 56102112 # Number of instructions committed +system.cpu.committedOps 56102112 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 51977185 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses +system.cpu.num_func_calls 1481236 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6460933 # number of instructions that are conditional controls +system.cpu.num_int_insts 51977185 # number of integer instructions +system.cpu.num_fp_insts 324460 # number of float instructions +system.cpu.num_int_register_reads 71206533 # number of times the integer registers were read +system.cpu.num_int_register_writes 38459103 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written +system.cpu.num_mem_refs 15454487 # number of memory refs +system.cpu.num_load_insts 9089505 # Number of load instructions +system.cpu.num_store_insts 6364982 # Number of store instructions +system.cpu.num_idle_cycles 3587234430.998131 # Number of idle cycles +system.cpu.num_busy_cycles 251643113.001869 # Number of busy cycles +system.cpu.not_idle_fraction 0.065551 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934449 # Percentage of idle cycles +system.cpu.Branches 8412678 # Number of branches fetched +system.cpu.op_class::No_OpClass 3197715 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36172357 64.46% 70.16% # Class of executed instruction +system.cpu.op_class::IntMult 61004 0.11% 70.27% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction +system.cpu.op_class::FloatAdd 38087 0.07% 70.34% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction @@ -519,34 +511,34 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::MemRead 9316905 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6371245 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953526 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 9316582 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6371054 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953544 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56116041 # Class of executed instruction +system.cpu.op_class::total 56113979 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212017 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 212019 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106210 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183167 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106211 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183168 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149118 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857252195000 96.76% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91387500 0.00% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 737178000 0.04% 96.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 61365063500 3.20% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1919445824000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1857248521000 96.76% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91287500 0.00% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 737179000 0.04% 96.80% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 61361050500 3.20% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1919438038000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692289 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814110 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692282 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814105 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -582,10 +574,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4179 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175948 91.21% 93.41% # number of callpals executed +system.cpu.kern.callpal::swpipl 175949 91.22% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed @@ -594,21 +586,21 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192895 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.callpal::total 192894 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5902 # number of protection mode switches +system.cpu.kern.mode_switch::user 1742 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches system.cpu.kern.mode_good::kernel 1912 -system.cpu.kern.mode_good::user 1741 -system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.323848 # fraction of useful protection mode switches +system.cpu.kern.mode_good::user 1742 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.323958 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392527 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46108525500 2.40% 2.40% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5189217000 0.27% 2.67% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1868148079500 97.33% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4180 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392567 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46116573000 2.40% 2.40% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5192895500 0.27% 2.67% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1868128567500 97.33% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -640,7 +632,7 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1409867 # Throughput (bytes/s) +system.iobus.throughput 1409873 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51201 # Transaction distribution @@ -700,21 +692,21 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380199064 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374407689 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43233500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42014000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 927875 # number of replacements -system.cpu.icache.tags.tagsinuse 508.303976 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55187496 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 928386 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.444559 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 927724 # number of replacements +system.cpu.icache.tags.tagsinuse 508.304001 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55185585 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 928235 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.452170 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 39855277250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.303976 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 508.304001 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.992781 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.992781 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -723,44 +715,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 1 system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57044588 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57044588 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 55187496 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55187496 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55187496 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55187496 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55187496 # number of overall hits -system.cpu.icache.overall_hits::total 55187496 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928546 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928546 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928546 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 928546 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 928546 # number of overall misses -system.cpu.icache.overall_misses::total 928546 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12910342260 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12910342260 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12910342260 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12910342260 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12910342260 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12910342260 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56116042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56116042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56116042 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56116042 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56116042 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56116042 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016547 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016547 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016547 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016547 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016547 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016547 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13903.826262 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13903.826262 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13903.826262 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13903.826262 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13903.826262 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13903.826262 # average overall miss latency +system.cpu.icache.tags.tag_accesses 57042375 # Number of tag accesses +system.cpu.icache.tags.data_accesses 57042375 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 55185585 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55185585 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55185585 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55185585 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55185585 # number of overall hits +system.cpu.icache.overall_hits::total 55185585 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 928395 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 928395 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 928395 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 928395 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 928395 # number of overall misses +system.cpu.icache.overall_misses::total 928395 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12914246500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12914246500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12914246500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12914246500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12914246500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12914246500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56113980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56113980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56113980 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56113980 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56113980 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56113980 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016545 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016545 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016545 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016545 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016545 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016545 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13910.293033 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13910.293033 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13910.293033 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13910.293033 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13910.293033 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13910.293033 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -769,135 +761,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928546 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 928546 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 928546 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 928546 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 928546 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 928546 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11048086740 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11048086740 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11048086740 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11048086740 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11048086740 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11048086740 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016547 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016547 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016547 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016547 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016547 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016547 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11898.265396 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11898.265396 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11898.265396 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11898.265396 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11898.265396 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11898.265396 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928395 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 928395 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 928395 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 928395 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 928395 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 928395 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11052282500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11052282500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11052282500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11052282500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11052282500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11052282500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016545 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016545 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016545 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016545 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016545 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016545 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11904.719974 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11904.719974 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11904.719974 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11904.719974 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11904.719974 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11904.719974 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 336232 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65296.289611 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2446119 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 401393 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.094075 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 336239 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65296.333666 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2445823 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 401400 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.093231 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 6784872750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 55555.447127 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4766.385283 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4974.457201 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.847709 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072729 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.075904 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996342 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 55553.405547 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4767.094279 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4975.833840 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.847678 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072740 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.075925 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996343 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65161 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # 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mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279571 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173374 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279571 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173374 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60231.419544 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52579.398640 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52935.988452 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56549.489687 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56549.489687 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60231.419544 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53772.468182 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53985.997988 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60231.419544 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53772.468182 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53985.997988 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384122 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384122 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014320 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279596 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173396 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014320 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279596 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173396 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60666.917406 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52570.305376 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52947.640524 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56538.425526 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56538.425526 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60666.917406 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53762.825468 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53991.084603 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60666.917406 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53762.825468 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53991.084603 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -973,13 +965,13 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1390190 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.978877 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14030691 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1390702 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.088927 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1390084 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.978881 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14030288 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390596 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.089406 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.978877 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.978881 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -987,72 +979,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63076279 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63076279 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7802806 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7802806 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5845593 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5845593 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183040 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183040 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199235 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199235 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13648399 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13648399 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13648399 # number of overall hits -system.cpu.dcache.overall_hits::total 13648399 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069264 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069264 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304240 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304240 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17216 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17216 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373504 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373504 # 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number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15021903 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15021903 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120520 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120520 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049471 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049471 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085970 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085970 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091433 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091433 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091433 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091433 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27122.777447 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27122.777447 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35852.292223 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35852.292223 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13255.881157 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13255.881157 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29056.421306 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29056.421306 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29056.421306 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29056.421306 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63074137 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63074137 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7802568 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7802568 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5845442 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5845442 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183034 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183034 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199227 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199227 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13648010 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13648010 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13648010 # number of overall hits +system.cpu.dcache.overall_hits::total 13648010 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069193 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069193 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304207 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304207 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17214 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17214 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373400 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373400 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373400 # number of overall misses +system.cpu.dcache.overall_misses::total 1373400 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28998201750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28998201750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10906246382 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10906246382 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228174000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 228174000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39904448132 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39904448132 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39904448132 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39904448132 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8871761 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8871761 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6149649 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6149649 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200248 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200248 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199227 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199227 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15021410 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15021410 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15021410 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15021410 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120516 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120516 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049467 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049467 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085963 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085963 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091429 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091429 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091429 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091429 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27121.578377 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27121.578377 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35851.398495 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35851.398495 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13255.141164 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13255.141164 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29055.226541 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29055.226541 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29055.226541 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29055.226541 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1061,54 +1053,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834591 # number of writebacks -system.cpu.dcache.writebacks::total 834591 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069264 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069264 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304240 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304240 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17216 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17216 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373504 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373504 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373504 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373504 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26737269496 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26737269496 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10246531614 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10246531614 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193767750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193767750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36983801110 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36983801110 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36983801110 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36983801110 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011220500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011220500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435456000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435456000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120520 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120520 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049471 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049471 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085970 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085970 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091433 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091433 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091433 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091433 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25005.302242 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25005.302242 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33679.107330 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33679.107330 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11255.097003 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11255.097003 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26926.606046 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26926.606046 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26926.606046 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26926.606046 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 834526 # number of writebacks +system.cpu.dcache.writebacks::total 834526 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069193 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069193 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304207 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304207 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17214 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17214 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373400 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373400 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373400 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373400 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26734131250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26734131250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10245126618 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245126618 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193732000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193732000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36979257868 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 36979257868 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36979257868 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36979257868 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011219500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011219500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435455500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435455500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120516 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120516 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049467 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049467 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085963 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085963 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091429 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091429 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091429 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091429 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25004.027570 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25004.027570 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33678.142245 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33678.142245 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11254.327873 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11254.327873 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26925.337023 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26925.337023 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26925.337023 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26925.337023 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1116,31 +1108,32 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 105186760 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2022129 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2022112 # Transaction distribution +system.cpu.toL2Bus.throughput 106562255 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2021905 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2021888 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 834591 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 834526 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41563 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 345775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857072 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649346 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5506418 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59425664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142473420 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 201899084 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 201889036 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 11328 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2424633500 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 304190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304190 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856770 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649068 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5505838 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59416000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142462412 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 201878412 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 201868428 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 2671296 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2424407500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1395400760 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1395179500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2186975140 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2186860632 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |