diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-07-27 16:08:05 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-07-27 16:08:05 -0400 |
| commit | b1a58933e07d7af0eb5f43942f8ad9bc93f28039 (patch) | |
| tree | 21f36b849ba0aed06ec18ed45aef46feeacd7532 /tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing | |
| parent | 630068be6f7b6dc5c612867c764c37e41fd90a4a (diff) | |
| download | gem5-b1a58933e07d7af0eb5f43942f8ad9bc93f28039.tar.xz | |
stats: update stats for icache change not allowing dirty data
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing')
3 files changed, 258 insertions, 259 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index a60709d68..734887994 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -250,7 +250,7 @@ header_cycles=1 use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.physmem.port[0] +master=system.bridge.slave system.physmem.port slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index c99186441..e4a5afde7 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:09:16 +gem5 compiled Jul 26 2012 21:20:05 +gem5 started Jul 26 2012 21:40:05 gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1920852274000 because m5_exit instruction encountered +Exiting @ tick 1920853042000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 8d476d641..c7cd1312f 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.920852 # Number of seconds simulated -sim_ticks 1920852274000 # Number of ticks simulated -final_tick 1920852274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.920853 # Number of seconds simulated +sim_ticks 1920853042000 # Number of ticks simulated +final_tick 1920853042000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1904642 # Simulator instruction rate (inst/s) -host_op_rate 1904641 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65112526106 # Simulator tick rate (ticks/s) -host_mem_usage 294856 # Number of bytes of host memory used -host_seconds 29.50 # Real time elapsed on the host +host_inst_rate 1381815 # Simulator instruction rate (inst/s) +host_op_rate 1381815 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47239093914 # Simulator tick rate (ticks/s) +host_mem_usage 299308 # Number of bytes of host memory used +host_seconds 40.66 # Real time elapsed on the host sim_insts 56187824 # Number of instructions simulated sim_ops 56187824 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory @@ -26,113 +26,113 @@ system.physmem.num_reads::total 442978 # Nu system.physmem.num_writes::writebacks 115454 # Number of write requests responded to by this memory system.physmem.num_writes::total 115454 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 442870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12935691 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12935686 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 1380820 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14759382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14759376 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 442870 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 442870 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3846759 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3846759 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3846759 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 3846758 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3846758 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3846758 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 442870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12935691 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12935686 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1380820 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18606141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18606133 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 336066 # number of replacements -system.l2c.tagsinuse 65311.816256 # Cycle average of tags in use -system.l2c.total_refs 2448229 # Total number of references to valid blocks. -system.l2c.sampled_refs 401229 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.101825 # Average number of references to valid blocks. +system.l2c.tagsinuse 65311.806529 # Cycle average of tags in use +system.l2c.total_refs 2448197 # Total number of references to valid blocks. +system.l2c.sampled_refs 401228 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.101760 # Average number of references to valid blocks. system.l2c.warmup_cycle 5946056000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55675.740322 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 4768.394145 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 4867.681789 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 55675.727094 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 4768.395922 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 4867.683513 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.849544 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.inst 0.072760 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.data 0.074275 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.996579 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 916210 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 814879 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1731089 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835223 # number of Writeback hits -system.l2c.Writeback_hits::total 835223 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 6 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 6 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 187457 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 187457 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 916210 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1002336 # number of demand (read+write) hits -system.l2c.demand_hits::total 1918546 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 916210 # number of overall hits -system.l2c.overall_hits::cpu.data 1002336 # number of overall hits -system.l2c.overall_hits::total 1918546 # number of overall hits +system.l2c.ReadReq_hits::cpu.inst 916208 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 814933 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1731141 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835149 # number of Writeback hits +system.l2c.Writeback_hits::total 835149 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 4 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 187605 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 187605 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 916208 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1002538 # number of demand (read+write) hits +system.l2c.demand_hits::total 1918746 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.inst 916208 # number of overall hits +system.l2c.overall_hits::cpu.data 1002538 # number of overall hits +system.l2c.overall_hits::total 1918746 # number of overall hits system.l2c.ReadReq_misses::cpu.inst 13292 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.data 271915 # number of ReadReq misses system.l2c.ReadReq_misses::total 285207 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 8 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 116714 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 116714 # number of ReadExReq misses +system.l2c.UpgradeReq_misses::cpu.data 14 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 14 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 116718 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 116718 # number of ReadExReq misses system.l2c.demand_misses::cpu.inst 13292 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 388629 # number of demand (read+write) misses -system.l2c.demand_misses::total 401921 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 388633 # number of demand (read+write) misses +system.l2c.demand_misses::total 401925 # number of demand (read+write) misses system.l2c.overall_misses::cpu.inst 13292 # number of overall misses -system.l2c.overall_misses::cpu.data 388629 # number of overall misses -system.l2c.overall_misses::total 401921 # number of overall misses +system.l2c.overall_misses::cpu.data 388633 # number of overall misses +system.l2c.overall_misses::total 401925 # number of overall misses system.l2c.ReadReq_miss_latency::cpu.inst 691773000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu.data 14144855000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::total 14836628000 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu.data 320000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 320000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6069807000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6069807000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6070015000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6070015000 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu.inst 691773000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 20214662000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 20906435000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 20214870000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 20906643000 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu.inst 691773000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 20214662000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 20906435000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.inst 929502 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1086794 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2016296 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 835223 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835223 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 14 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 14 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 304171 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 304171 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.inst 929502 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1390965 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2320467 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.inst 929502 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1390965 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2320467 # number of overall (read+write) accesses +system.l2c.overall_miss_latency::cpu.data 20214870000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 20906643000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.inst 929500 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1086848 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2016348 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 835149 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 835149 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 304323 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 304323 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.inst 929500 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1391171 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2320671 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.inst 929500 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1391171 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2320671 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.014300 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.250199 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.141451 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.571429 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.571429 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.383712 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.383712 # miss rate for ReadExReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.250187 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.141447 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.777778 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.777778 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.383533 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.383533 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.inst 0.014300 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.279395 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.173207 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.279357 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.173193 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.inst 0.014300 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.279395 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.173207 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.279357 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.173193 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.inst 52044.312368 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.399445 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 52020.560505 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 40000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 40000 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.817640 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52005.817640 # average ReadExReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 22857.142857 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 22857.142857 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.817440 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52005.817440 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.inst 52044.312368 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52015.320524 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52016.279319 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52015.320367 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52016.279157 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.inst 52044.312368 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52015.320524 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52016.279319 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52015.320367 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52016.279157 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -146,29 +146,29 @@ system.l2c.writebacks::total 73942 # nu system.l2c.ReadReq_mshr_misses::cpu.inst 13292 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu.data 271915 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 285207 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 116714 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 116714 # number of ReadExReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 116718 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 116718 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu.inst 13292 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 388629 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 401921 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 388633 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 401925 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu.inst 13292 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 388629 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 401921 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 388633 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 401925 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu.inst 532266000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu.data 10881875000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 11414141000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 380000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 380000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4669239000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4669239000 # number of ReadExReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 620000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 620000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4669399000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4669399000 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu.inst 532266000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 15551114000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16083380000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 15551274000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16083540000 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu.inst 532266000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 15551114000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16083380000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 15551274000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16083540000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 772639030 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 772639030 # number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1072677000 # number of WriteReq MSHR uncacheable cycles @@ -176,31 +176,31 @@ system.l2c.WriteReq_mshr_uncacheable_latency::total 1072677000 system.l2c.overall_mshr_uncacheable_latency::cpu.data 1845316030 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::total 1845316030 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250199 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.141451 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.571429 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.571429 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383712 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.383712 # mshr miss rate for ReadExReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250187 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.141447 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.777778 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.777778 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383533 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.383533 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.279395 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.173207 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.279357 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173193 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.279395 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173207 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.279357 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173193 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40044.086669 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.399445 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.549987 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 47500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 47500 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.817640 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.817640 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 44285.714286 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44285.714286 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.817440 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.817440 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40044.086669 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.320524 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40016.271854 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.320367 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40016.271692 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40044.086669 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.320524 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40016.271854 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.320367 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40016.271692 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -209,14 +209,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.356962 # Cycle average of tags in use +system.iocache.tagsinuse 1.356968 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1753491316000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.356962 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.084810 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.084810 # Average percentage of cache occupancy +system.iocache.occ_blocks::tsunami.ide 1.356968 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.084811 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.084811 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -344,7 +344,7 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3841704548 # number of cpu cycles simulated +system.cpu.numCycles 3841706084 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 56187824 # Number of instructions committed @@ -362,10 +362,10 @@ system.cpu.num_fp_register_writes 166520 # nu system.cpu.num_mem_refs 15475451 # number of memory refs system.cpu.num_load_insts 9102635 # Number of load instructions system.cpu.num_store_insts 6372816 # Number of store instructions -system.cpu.num_idle_cycles 3589583028.998131 # Number of idle cycles -system.cpu.num_busy_cycles 252121519.001869 # Number of busy cycles -system.cpu.not_idle_fraction 0.065628 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934372 # Percentage of idle cycles +system.cpu.num_idle_cycles 3589579952.998131 # Number of idle cycles +system.cpu.num_busy_cycles 252126131.001869 # Number of busy cycles +system.cpu.not_idle_fraction 0.065629 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934371 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed system.cpu.kern.inst.hwrei 212104 # number of hwrei instructions executed @@ -379,11 +379,11 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.40% # nu system.cpu.kern.ipl_good::22 1936 1.30% 50.69% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73562 49.31% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149191 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1861395067500 96.90% 96.90% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1861395652500 96.90% 96.90% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 90398000 0.00% 96.91% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 587303500 0.03% 96.94% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 58778672000 3.06% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1920851441000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 587366500 0.03% 96.94% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 58778792000 3.06% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1920852209000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -447,9 +447,9 @@ system.cpu.kern.mode_switch_good::kernel 0.323061 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.391706 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46234544000 2.41% 2.41% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5257252000 0.27% 2.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1869359638000 97.32% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 46234707000 2.41% 2.41% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5259387000 0.27% 2.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1869358108000 97.32% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -482,33 +482,33 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 928851 # number of replacements -system.cpu.icache.tagsinuse 508.732124 # Cycle average of tags in use -system.cpu.icache.total_refs 55270141 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 929362 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.471058 # Average number of references to valid blocks. +system.cpu.icache.replacements 928849 # number of replacements +system.cpu.icache.tagsinuse 508.732123 # Cycle average of tags in use +system.cpu.icache.total_refs 55270143 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 929360 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 59.471188 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 35877190000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 508.732124 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 508.732123 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.993617 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.993617 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55270141 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55270141 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55270141 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55270141 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55270141 # number of overall hits -system.cpu.icache.overall_hits::total 55270141 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929522 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929522 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929522 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929522 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929522 # number of overall misses -system.cpu.icache.overall_misses::total 929522 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13854472500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13854472500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13854472500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13854472500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13854472500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13854472500 # number of overall miss cycles +system.cpu.icache.ReadReq_hits::cpu.inst 55270143 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55270143 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55270143 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55270143 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55270143 # number of overall hits +system.cpu.icache.overall_hits::total 55270143 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929520 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929520 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929520 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929520 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929520 # number of overall misses +system.cpu.icache.overall_misses::total 929520 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13854449500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13854449500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13854449500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13854449500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13854449500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13854449500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 56199663 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 56199663 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 56199663 # number of demand (read+write) accesses @@ -521,12 +521,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.016540 system.cpu.icache.demand_miss_rate::total 0.016540 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.016540 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.943078 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14904.943078 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.943078 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14904.943078 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.943078 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14904.943078 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.950405 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14904.950405 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.950405 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14904.950405 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.950405 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14904.950405 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -535,74 +535,72 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 85 # number of writebacks -system.cpu.icache.writebacks::total 85 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929522 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929522 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929522 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929522 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929522 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929522 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11065220000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11065220000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11065220000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11065220000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11065220000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11065220000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929520 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 929520 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 929520 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 929520 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 929520 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 929520 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11065203000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11065203000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11065203000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11065203000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11065203000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11065203000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016540 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.016540 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.016540 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11904.204527 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11904.204527 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11904.204527 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11904.204527 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11904.204527 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11904.204527 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11904.211851 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11904.211851 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11904.211851 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11904.211851 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11904.211851 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11904.211851 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1390643 # number of replacements +system.cpu.dcache.replacements 1390657 # number of replacements system.cpu.dcache.tagsinuse 511.983813 # Cycle average of tags in use -system.cpu.dcache.total_refs 14050710 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1391155 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.100032 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 14050696 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1391169 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.099920 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 85768000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.983813 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999968 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7815347 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7815347 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5853082 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5853082 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 7815339 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7815339 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5853076 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5853076 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 182979 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 182979 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199284 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199284 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13668429 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13668429 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13668429 # number of overall hits -system.cpu.dcache.overall_hits::total 13668429 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069514 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069514 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304335 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304335 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 13668415 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13668415 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13668415 # number of overall hits +system.cpu.dcache.overall_hits::total 13668415 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069522 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069522 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304341 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304341 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 17326 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17326 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373849 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373849 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373849 # number of overall misses -system.cpu.dcache.overall_misses::total 1373849 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26655510000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26655510000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9230954000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9230954000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1373863 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373863 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373863 # number of overall misses +system.cpu.dcache.overall_misses::total 1373863 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26656014000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26656014000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9232792000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9232792000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 248493000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 248493000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35886464000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35886464000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35886464000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35886464000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35888806000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35888806000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35888806000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35888806000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 8884861 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 8884861 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6157417 # number of WriteReq accesses(hits+misses) @@ -615,26 +613,26 @@ system.cpu.dcache.demand_accesses::cpu.data 15042278 # system.cpu.dcache.demand_accesses::total 15042278 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 15042278 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15042278 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120375 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120375 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049426 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049426 # miss rate for WriteReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120376 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120376 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049427 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049427 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086498 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086498 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.091333 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.091333 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.091333 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.091333 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.011760 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.011760 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30331.555687 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30331.555687 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.296575 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.296575 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30336.996987 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30336.996987 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14342.202470 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14342.202470 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26121.112291 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26121.112291 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26121.112291 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26121.112291 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26122.550793 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26122.550793 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26122.550793 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26122.550793 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -643,54 +641,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835138 # number of writebacks -system.cpu.dcache.writebacks::total 835138 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069514 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069514 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304335 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304335 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 835149 # number of writebacks +system.cpu.dcache.writebacks::total 835149 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069522 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069522 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304341 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304341 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17326 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 17326 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373849 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373849 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373849 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373849 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23446923000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23446923000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8317949000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8317949000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1373863 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373863 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373863 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373863 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23447403000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23447403000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8319769000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8319769000 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 196515000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196515000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31764872000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31764872000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31764872000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31764872000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31767172000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31767172000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31767172000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31767172000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 862831000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 862831000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1190523500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1190523500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2053354500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 2053354500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120375 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120375 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049426 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049426 # mshr miss rate for WriteReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120376 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120376 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049427 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049427 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086498 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086498 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.091333 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.091333 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21922.969685 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21922.969685 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27331.555687 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27331.555687 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21923.254501 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21923.254501 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27336.996987 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27336.996987 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11342.202470 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11342.202470 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23121.079536 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23121.079536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23121.079536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23121.079536 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23122.518039 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23122.518039 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23122.518039 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23122.518039 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |