diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
| commit | fda338f8d3ba6f6cb271e2c10cb880ff064edb61 (patch) | |
| tree | 20a91f6acacb2cb40967ce56a539d8444b744b9e /tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing | |
| parent | b265d9925c123f0df50db98cf56dab6a3596b54b (diff) | |
| download | gem5-fda338f8d3ba6f6cb271e2c10cb880ff064edb61.tar.xz | |
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing')
3 files changed, 494 insertions, 494 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index d6cd88975..a60709d68 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -186,7 +186,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=true -width=64 +width=8 default=system.tsunami.pciconfig.pio master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma @@ -248,7 +248,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.physmem.port[0] slave=system.system_port system.iocache.mem_side system.l2c.mem_side @@ -305,7 +305,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index c4cb3c061..c99186441 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:10:05 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:09:16 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1915492819000 because m5_exit instruction encountered +Exiting @ tick 1920852274000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index abedba373..8d476d641 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.915493 # Number of seconds simulated -sim_ticks 1915492819000 # Number of ticks simulated -final_tick 1915492819000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.920852 # Number of seconds simulated +sim_ticks 1920852274000 # Number of ticks simulated +final_tick 1920852274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1853108 # Simulator instruction rate (inst/s) -host_op_rate 1853107 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63179819624 # Simulator tick rate (ticks/s) -host_mem_usage 294892 # Number of bytes of host memory used -host_seconds 30.32 # Real time elapsed on the host -sim_insts 56182681 # Number of instructions simulated -sim_ops 56182681 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24846208 # Number of bytes read from this memory +host_inst_rate 1904642 # Simulator instruction rate (inst/s) +host_op_rate 1904641 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65112526106 # Simulator tick rate (ticks/s) +host_mem_usage 294856 # Number of bytes of host memory used +host_seconds 29.50 # Real time elapsed on the host +sim_insts 56187824 # Number of instructions simulated +sim_ops 56187824 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24847552 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28349056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7388480 # Number of bytes written to this memory -system.physmem.bytes_written::total 7388480 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388222 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28350592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850688 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7389056 # Number of bytes written to this memory +system.physmem.bytes_written::total 7389056 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13292 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388243 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 442954 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115445 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115445 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 444009 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12971183 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1384684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14799876 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 444009 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 444009 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3857221 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3857221 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3857221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 444009 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12971183 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1384684 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18657097 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 336041 # number of replacements -system.l2c.tagsinuse 65311.191779 # Cycle average of tags in use -system.l2c.total_refs 2447812 # Total number of references to valid blocks. -system.l2c.sampled_refs 401203 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.101181 # Average number of references to valid blocks. -system.l2c.warmup_cycle 5933228000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55666.496606 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 4774.109125 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 4870.586047 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.849403 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.072847 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.074319 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996570 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 915368 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 814896 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1730264 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835591 # number of Writeback hits -system.l2c.Writeback_hits::total 835591 # number of Writeback hits +system.physmem.num_reads::total 442978 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115454 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115454 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442870 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12935691 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1380820 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14759382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442870 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442870 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3846759 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3846759 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3846759 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442870 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12935691 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1380820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18606141 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 336066 # number of replacements +system.l2c.tagsinuse 65311.816256 # Cycle average of tags in use +system.l2c.total_refs 2448229 # Total number of references to valid blocks. +system.l2c.sampled_refs 401229 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.101825 # Average number of references to valid blocks. +system.l2c.warmup_cycle 5946056000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 55675.740322 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 4768.394145 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 4867.681789 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.849544 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.072760 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.074275 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.996579 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 916210 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 814879 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1731089 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835223 # number of Writeback hits +system.l2c.Writeback_hits::total 835223 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 6 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 6 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 187658 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 187658 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 915368 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1002554 # number of demand (read+write) hits -system.l2c.demand_hits::total 1917922 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 915368 # number of overall hits -system.l2c.overall_hits::cpu.data 1002554 # number of overall hits -system.l2c.overall_hits::total 1917922 # number of overall hits -system.l2c.ReadReq_misses::cpu.inst 13289 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 271916 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285205 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 7 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 116692 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 116692 # number of ReadExReq misses -system.l2c.demand_misses::cpu.inst 13289 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 388608 # number of demand (read+write) misses -system.l2c.demand_misses::total 401897 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.inst 13289 # number of overall misses -system.l2c.overall_misses::cpu.data 388608 # number of overall misses -system.l2c.overall_misses::total 401897 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.inst 691068000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 14144627000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 14835695000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 248000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 248000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6068427000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6068427000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.inst 691068000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 20213054000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 20904122000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.inst 691068000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 20213054000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 20904122000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.inst 928657 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1086812 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2015469 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 835591 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835591 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 304350 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 304350 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.inst 928657 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1391162 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2319819 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.inst 928657 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1391162 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2319819 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.014310 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.250196 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.141508 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.538462 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.538462 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.383414 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.383414 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.inst 0.014310 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.279341 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.173245 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.inst 0.014310 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.279341 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.173245 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52003.010008 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52018.369644 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52017.653968 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 35428.571429 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 35428.571429 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52003.796319 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52003.796319 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52003.010008 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52013.993536 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52013.630358 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52003.010008 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52013.993536 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52013.630358 # average overall miss latency +system.l2c.ReadExReq_hits::cpu.data 187457 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 187457 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 916210 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1002336 # number of demand (read+write) hits +system.l2c.demand_hits::total 1918546 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.inst 916210 # number of overall hits +system.l2c.overall_hits::cpu.data 1002336 # number of overall hits +system.l2c.overall_hits::total 1918546 # number of overall hits +system.l2c.ReadReq_misses::cpu.inst 13292 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 271915 # number of ReadReq misses +system.l2c.ReadReq_misses::total 285207 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 8 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 116714 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 116714 # number of ReadExReq misses +system.l2c.demand_misses::cpu.inst 13292 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 388629 # number of demand (read+write) misses +system.l2c.demand_misses::total 401921 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.inst 13292 # number of overall misses +system.l2c.overall_misses::cpu.data 388629 # number of overall misses +system.l2c.overall_misses::total 401921 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.inst 691773000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 14144855000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 14836628000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 320000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 320000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6069807000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6069807000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.inst 691773000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 20214662000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 20906435000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.inst 691773000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 20214662000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 20906435000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.inst 929502 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1086794 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2016296 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 835223 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 835223 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 14 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 14 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 304171 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 304171 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.inst 929502 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1390965 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2320467 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.inst 929502 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1390965 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2320467 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.014300 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.250199 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.141451 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.571429 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.571429 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.383712 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.383712 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.inst 0.014300 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.279395 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.173207 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.inst 0.014300 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.279395 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.173207 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52044.312368 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.399445 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52020.560505 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 40000 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 40000 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.817640 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52005.817640 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52044.312368 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52015.320524 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52016.279319 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52044.312368 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52015.320524 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52016.279319 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -141,66 +141,66 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 73933 # number of writebacks -system.l2c.writebacks::total 73933 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu.inst 13289 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 271916 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 285205 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 7 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 7 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 116692 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 116692 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 13289 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 388608 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 401897 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 13289 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 388608 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 401897 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 531597000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 10881635000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 11413232000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 320000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 320000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4668123000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4668123000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 531597000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 15549758000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16081355000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 531597000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 15549758000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16081355000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 772673000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 772673000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1083816500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1083816500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 1856489500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1856489500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014310 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250196 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.141508 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.538462 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.538462 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383414 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.383414 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.014310 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.279341 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.173245 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.014310 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.279341 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173245 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.784258 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40018.369644 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40017.643449 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 45714.285714 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 45714.285714 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40003.796319 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40003.796319 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40002.784258 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40013.993536 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40013.622893 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40002.784258 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40013.993536 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40013.622893 # average overall mshr miss latency +system.l2c.writebacks::writebacks 73942 # number of writebacks +system.l2c.writebacks::total 73942 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu.inst 13292 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 271915 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 285207 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 116714 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 116714 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 13292 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 388629 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 401921 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 13292 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 388629 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 401921 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 532266000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 10881875000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 11414141000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 380000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 380000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4669239000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4669239000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 532266000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 15551114000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16083380000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 532266000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 15551114000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16083380000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 772639030 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 772639030 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1072677000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1072677000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 1845316030 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1845316030 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250199 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.141451 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.571429 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.571429 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383712 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.383712 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.279395 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173207 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.279395 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173207 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40044.086669 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.399445 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.549987 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 47500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 47500 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.817640 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.817640 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40044.086669 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.320524 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40016.271854 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40044.086669 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.320524 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40016.271854 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -209,14 +209,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.340010 # Cycle average of tags in use +system.iocache.tagsinuse 1.356962 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1750543570000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.340010 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.083751 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.083751 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1753491316000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.356962 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.084810 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.084810 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -225,14 +225,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 19939998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 19939998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5720017806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5720017806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5739957804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5739957804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5739957804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5739957804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 7638105806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 7638105806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 7658778804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7658778804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 7658778804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7658778804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -249,19 +249,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115260.104046 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 115260.104046 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137659.265643 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 137659.265643 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137566.394344 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 137566.394344 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137566.394344 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 137566.394344 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64633068 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183820.413121 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 183820.413121 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 183553.716093 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183553.716093 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 183553.716093 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183553.716093 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7453000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7118 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6169.632302 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 1047.063782 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -275,14 +275,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10943998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 10943998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3559163998 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3559163998 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3570107996 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3570107996 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3570107996 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3570107996 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5477251000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 5477251000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5488927000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5488927000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5488927000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5488927000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -291,14 +291,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63260.104046 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 63260.104046 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85655.660329 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 85655.660329 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85562.803978 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 85562.803978 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85562.803978 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 85562.803978 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131816.783789 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 131816.783789 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131550.077891 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131550.077891 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131550.077891 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131550.077891 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -316,22 +316,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9064877 # DTB read hits -system.cpu.dtb.read_misses 10317 # DTB read misses +system.cpu.dtb.read_hits 9065773 # DTB read hits +system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728824 # DTB read accesses -system.cpu.dtb.write_hits 6356219 # DTB write hits -system.cpu.dtb.write_misses 1140 # DTB write misses +system.cpu.dtb.read_accesses 728856 # DTB read accesses +system.cpu.dtb.write_hits 6357048 # DTB write hits +system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291929 # DTB write accesses -system.cpu.dtb.data_hits 15421096 # DTB hits -system.cpu.dtb.data_misses 11457 # DTB misses +system.cpu.dtb.write_accesses 291931 # DTB write accesses +system.cpu.dtb.data_hits 15422821 # DTB hits +system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020753 # DTB accesses -system.cpu.itb.fetch_hits 4974034 # ITB hits -system.cpu.itb.fetch_misses 4997 # ITB misses +system.cpu.dtb.data_accesses 1020787 # DTB accesses +system.cpu.itb.fetch_hits 4975760 # ITB hits +system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979031 # ITB accesses +system.cpu.itb.fetch_accesses 4980766 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -344,51 +344,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3830985638 # number of cpu cycles simulated +system.cpu.numCycles 3841704548 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56182681 # Number of instructions committed -system.cpu.committedOps 56182681 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52054721 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses -system.cpu.num_func_calls 1483282 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6468098 # number of instructions that are conditional controls -system.cpu.num_int_insts 52054721 # number of integer instructions -system.cpu.num_fp_insts 324259 # number of float instructions -system.cpu.num_int_register_reads 71321767 # number of times the integer registers were read -system.cpu.num_int_register_writes 38521612 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written -system.cpu.num_mem_refs 15473677 # number of memory refs -system.cpu.num_load_insts 9101706 # Number of load instructions -system.cpu.num_store_insts 6371971 # Number of store instructions -system.cpu.num_idle_cycles 3589415321.998127 # Number of idle cycles -system.cpu.num_busy_cycles 241570316.001874 # Number of busy cycles -system.cpu.not_idle_fraction 0.063057 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.936943 # Percentage of idle cycles +system.cpu.committedInsts 56187824 # Number of instructions committed +system.cpu.committedOps 56187824 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52059470 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses +system.cpu.num_func_calls 1483670 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6469221 # number of instructions that are conditional controls +system.cpu.num_int_insts 52059470 # number of integer instructions +system.cpu.num_fp_insts 324460 # number of float instructions +system.cpu.num_int_register_reads 71329755 # number of times the integer registers were read +system.cpu.num_int_register_writes 38524240 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written +system.cpu.num_mem_refs 15475451 # number of memory refs +system.cpu.num_load_insts 9102635 # Number of load instructions +system.cpu.num_store_insts 6372816 # Number of store instructions +system.cpu.num_idle_cycles 3589583028.998131 # Number of idle cycles +system.cpu.num_busy_cycles 252121519.001869 # Number of busy cycles +system.cpu.not_idle_fraction 0.065628 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934372 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211976 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74903 40.89% 40.89% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1931 1.05% 42.02% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106219 57.98% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183184 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73536 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212104 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74929 40.88% 40.88% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1936 1.06% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106285 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183281 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73562 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73536 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149134 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857766748000 96.99% 96.99% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 79985500 0.00% 96.99% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 554565500 0.03% 97.02% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 57090762000 2.98% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1915492061000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981750 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1936 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73562 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149191 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1861395067500 96.90% 96.90% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 90398000 0.00% 96.91% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 587303500 0.03% 96.94% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 58778672000 3.06% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1920851441000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692306 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814121 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692120 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814001 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -424,33 +424,33 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175965 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 176052 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6837 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5161 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192907 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5900 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1740 -system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.323559 # fraction of useful protection mode switches +system.cpu.kern.callpal::total 193007 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5906 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1738 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.323061 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392153 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 45078055000 2.35% 2.35% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5087693000 0.27% 2.62% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1865326311000 97.38% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4175 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.391706 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46234544000 2.41% 2.41% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5257252000 0.27% 2.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1869359638000 97.32% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -482,51 +482,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 928006 # number of replacements -system.cpu.icache.tagsinuse 508.737243 # Cycle average of tags in use -system.cpu.icache.total_refs 55265829 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 928517 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.520535 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 35693107000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 508.737243 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.993627 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.993627 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55265829 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55265829 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55265829 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55265829 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55265829 # number of overall hits -system.cpu.icache.overall_hits::total 55265829 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928677 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928677 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928677 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 928677 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 928677 # number of overall misses -system.cpu.icache.overall_misses::total 928677 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13560162500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13560162500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13560162500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13560162500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13560162500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13560162500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56194506 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56194506 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56194506 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56194506 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56194506 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56194506 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016526 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016526 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016526 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016526 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016526 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016526 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14601.591834 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14601.591834 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14601.591834 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14601.591834 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14601.591834 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14601.591834 # average overall miss latency +system.cpu.icache.replacements 928851 # number of replacements +system.cpu.icache.tagsinuse 508.732124 # Cycle average of tags in use +system.cpu.icache.total_refs 55270141 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 929362 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 59.471058 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 35877190000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 508.732124 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.993617 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.993617 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55270141 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55270141 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55270141 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55270141 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55270141 # number of overall hits +system.cpu.icache.overall_hits::total 55270141 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929522 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929522 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929522 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929522 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929522 # number of overall misses +system.cpu.icache.overall_misses::total 929522 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13854472500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13854472500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13854472500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13854472500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13854472500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13854472500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56199663 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56199663 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56199663 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56199663 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56199663 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56199663 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016540 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016540 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016540 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016540 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016540 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.943078 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14904.943078 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.943078 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14904.943078 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.943078 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14904.943078 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -537,104 +537,104 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 85 # number of writebacks system.cpu.icache.writebacks::total 85 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928677 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 928677 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 928677 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 928677 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 928677 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 928677 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10773446000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10773446000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10773446000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10773446000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10773446000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10773446000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016526 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016526 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016526 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016526 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016526 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016526 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11600.853688 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11600.853688 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11600.853688 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11600.853688 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11600.853688 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11600.853688 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929522 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 929522 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 929522 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 929522 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 929522 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 929522 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11065220000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11065220000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11065220000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11065220000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11065220000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11065220000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016540 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016540 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016540 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11904.204527 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11904.204527 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11904.204527 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11904.204527 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11904.204527 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11904.204527 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1390840 # number of replacements -system.cpu.dcache.tagsinuse 511.984022 # Cycle average of tags in use -system.cpu.dcache.total_refs 14048762 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1391352 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.097202 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 84029000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.984022 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999969 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999969 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7814456 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7814456 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5852131 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5852131 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182935 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182935 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199223 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199223 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13666587 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13666587 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13666587 # number of overall hits -system.cpu.dcache.overall_hits::total 13666587 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069547 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069547 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304513 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304513 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17311 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17311 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1374060 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1374060 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1374060 # number of overall misses -system.cpu.dcache.overall_misses::total 1374060 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26396026000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26396026000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9163670000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9163670000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 245084000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 245084000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35559696000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35559696000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35559696000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35559696000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8884003 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8884003 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6156644 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6156644 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200246 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200246 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199223 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199223 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15040647 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15040647 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15040647 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15040647 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120390 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120390 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049461 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049461 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086449 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086449 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091356 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091356 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091356 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091356 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24679.631657 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24679.631657 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30092.869598 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30092.869598 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14157.703195 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14157.703195 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25879.289114 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25879.289114 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25879.289114 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25879.289114 # average overall miss latency +system.cpu.dcache.replacements 1390643 # number of replacements +system.cpu.dcache.tagsinuse 511.983813 # Cycle average of tags in use +system.cpu.dcache.total_refs 14050710 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1391155 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.100032 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 85768000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.983813 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999968 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7815347 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7815347 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5853082 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5853082 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182979 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182979 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199284 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199284 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13668429 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13668429 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13668429 # number of overall hits +system.cpu.dcache.overall_hits::total 13668429 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069514 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069514 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304335 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304335 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17326 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17326 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373849 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373849 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373849 # number of overall misses +system.cpu.dcache.overall_misses::total 1373849 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26655510000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26655510000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9230954000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9230954000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 248493000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 248493000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35886464000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35886464000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35886464000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35886464000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8884861 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8884861 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6157417 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157417 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200305 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200305 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199284 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199284 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15042278 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15042278 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15042278 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15042278 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120375 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120375 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049426 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049426 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086498 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086498 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091333 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091333 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091333 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091333 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.011760 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.011760 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30331.555687 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30331.555687 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14342.202470 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14342.202470 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26121.112291 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26121.112291 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26121.112291 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26121.112291 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -643,54 +643,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835506 # number of writebacks -system.cpu.dcache.writebacks::total 835506 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069547 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069547 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304513 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304513 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17311 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17311 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1374060 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1374060 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1374060 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1374060 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23187340000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23187340000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8250131000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8250131000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193151000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193151000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31437471000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31437471000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31437471000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31437471000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 862763000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 862763000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1199604500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1199604500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2062367500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 2062367500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120390 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120390 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049461 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049461 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086449 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086449 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091356 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091356 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091356 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091356 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21679.589583 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21679.589583 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27092.869598 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27092.869598 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11157.703195 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11157.703195 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22879.256364 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22879.256364 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22879.256364 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22879.256364 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 835138 # number of writebacks +system.cpu.dcache.writebacks::total 835138 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069514 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069514 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304335 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304335 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17326 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17326 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373849 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373849 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373849 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373849 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23446923000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23446923000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8317949000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8317949000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 196515000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196515000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31764872000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31764872000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31764872000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31764872000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 862831000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 862831000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1190523500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1190523500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2053354500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 2053354500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120375 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120375 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049426 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049426 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086498 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086498 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091333 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091333 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21922.969685 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21922.969685 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27331.555687 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27331.555687 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11342.202470 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11342.202470 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23121.079536 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23121.079536 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23121.079536 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23121.079536 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |