diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
| commit | c49e739352b6d6bd665c78c560602d0cff1e6a1a (patch) | |
| tree | 5d32efd82f884376573604727d971a80458ed04a /tests/quick/fs/10.linux-boot/ref/alpha/linux | |
| parent | e5f0d6016ba768c06b36d8b3d54f3ea700a4aa58 (diff) | |
| download | gem5-c49e739352b6d6bd665c78c560602d0cff1e6a1a.tar.xz | |
all: Update stats for memory per master and total fix.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux')
12 files changed, 424 insertions, 102 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 631fa3b25..08fd1ccfb 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -282,9 +282,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=true @@ -344,10 +343,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -403,9 +401,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index 8c9800a70..06d87b670 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:56 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:39:49 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index b34633a17..b45122ce6 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,23 +4,50 @@ sim_seconds 1.870336 # Nu sim_ticks 1870335522500 # Number of ticks simulated final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1989571 # Simulator instruction rate (inst/s) -host_op_rate 1989570 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58921958204 # Simulator tick rate (ticks/s) -host_mem_usage 298304 # Number of bytes of host memory used -host_seconds 31.74 # Real time elapsed on the host +host_inst_rate 2870976 # Simulator instruction rate (inst/s) +host_op_rate 2870973 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 85025108641 # Simulator tick rate (ticks/s) +host_mem_usage 298608 # Number of bytes of host memory used +host_seconds 22.00 # Real time elapsed on the host sim_insts 63154034 # Number of instructions simulated sim_ops 63154034 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 72297472 # Number of bytes read from this memory -system.physmem.bytes_inst_read 995008 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10452352 # Number of bytes written to this memory -system.physmem.num_reads 1129648 # Number of read requests responded to by this memory -system.physmem.num_writes 163318 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 38654814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 531994 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5588490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 44243304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0.inst 855168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 67882688 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 139840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 770176 # Number of bytes read from this memory +system.physmem.bytes_read::total 72297472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 855168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 139840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 995008 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10452352 # Number of bytes written to this memory +system.physmem.bytes_written::total 10452352 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13362 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1060667 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2185 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 12034 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1129648 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 163318 # Number of write requests responded to by this memory +system.physmem.num_writes::total 163318 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 457227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 36294391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 74767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 411785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 38654814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 457227 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 74767 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 531994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5588490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5588490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5588490 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 457227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 36294391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 74767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 411785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 44243304 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 1051788 # number of replacements system.l2c.tagsinuse 34117.721410 # Cycle average of tags in use system.l2c.total_refs 2341203 # Total number of references to valid blocks. @@ -118,20 +145,26 @@ system.l2c.ReadReq_miss_rate::cpu0.inst 0.015099 # mi system.l2c.ReadReq_miss_rate::cpu0.data 0.557511 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.021085 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.061193 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.353588 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947961 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.935644 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.945615 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.812500 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.918182 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.873684 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.416750 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.410237 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.416240 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.015099 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.537413 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.021085 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.196117 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.359923 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.015099 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.537413 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.021085 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.196117 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.359923 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -169,9 +202,13 @@ system.iocache.demand_accesses::total 41727 # nu system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -275,6 +312,7 @@ system.cpu0.kern.ipl_used::21 1 # fr system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808753 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed @@ -333,7 +371,7 @@ system.cpu0.kern.mode_good::idle 0 system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total nan # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.280640 # fraction of useful protection mode switches system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode @@ -397,8 +435,11 @@ system.cpu0.icache.demand_accesses::total 57230132 # n system.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.015464 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.015464 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -456,11 +497,17 @@ system.cpu0.dcache.demand_accesses::total 14729930 # n system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187444 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.187444 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049753 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049753 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085817 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085817 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003753 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003753 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133711 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.133711 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133711 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.133711 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -548,6 +595,7 @@ system.cpu1.kern.ipl_used::0 0.999032 # fr system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed @@ -593,7 +641,7 @@ system.cpu1.kern.mode_good::idle 32 system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.608089 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode @@ -626,8 +674,11 @@ system.cpu1.icache.demand_accesses::total 5935766 # n system.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017459 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.017459 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017459 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.017459 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017459 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.017459 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -685,11 +736,17 @@ system.cpu1.dcache.demand_accesses::total 1884270 # n system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036187 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036187 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035266 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.035266 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078511 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078511 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044784 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044784 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035829 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.035829 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035829 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035829 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 3d4adbd35..3950ce4a4 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -185,9 +185,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=true @@ -247,10 +246,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -306,9 +304,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index f348f1381..92dc7ad3d 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:42:39 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:07:23 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 1b6d7ca40..4492aa0b0 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,23 +4,40 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332258000 # Number of ticks simulated final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1921293 # Simulator instruction rate (inst/s) -host_op_rate 1921291 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58540553267 # Simulator tick rate (ticks/s) -host_mem_usage 295828 # Number of bytes of host memory used -host_seconds 31.25 # Real time elapsed on the host +host_inst_rate 2878195 # Simulator instruction rate (inst/s) +host_op_rate 2878193 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 87696777763 # Simulator tick rate (ticks/s) +host_mem_usage 296144 # Number of bytes of host memory used +host_seconds 20.86 # Real time elapsed on the host sim_insts 60038305 # Number of instructions simulated sim_ops 60038305 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 71650816 # Number of bytes read from this memory -system.physmem.bytes_inst_read 955904 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10156864 # Number of bytes written to this memory -system.physmem.num_reads 1119544 # Number of read requests responded to by this memory -system.physmem.num_writes 158701 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 39167743 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 522543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5552225 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 44719968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 955904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 68042304 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652608 # Number of bytes read from this memory +system.physmem.bytes_read::total 71650816 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 955904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 955904 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10156864 # Number of bytes written to this memory +system.physmem.bytes_written::total 10156864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 14936 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1063161 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41447 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1119544 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 158701 # Number of write requests responded to by this memory +system.physmem.num_writes::total 158701 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 522543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 37195159 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1450042 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 39167743 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 522543 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 522543 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5552225 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5552225 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5552225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 522543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 37195159 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1450042 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 44719968 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 1045877 # number of replacements system.l2c.tagsinuse 33807.015903 # Cycle average of tags in use system.l2c.total_refs 2291835 # Total number of references to valid blocks. @@ -79,12 +96,17 @@ system.l2c.overall_accesses::cpu.data 2043063 # nu system.l2c.overall_accesses::total 2963266 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.016231 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.543295 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.360895 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.923077 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.923077 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.390673 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.390673 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.inst 0.016231 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.520567 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.363952 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.inst 0.016231 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.520567 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.363952 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -122,9 +144,13 @@ system.iocache.demand_accesses::total 41726 # nu system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -224,6 +250,7 @@ system.cpu.kern.ipl_used::0 0.981732 # fr system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -281,7 +308,7 @@ system.cpu.kern.mode_good::idle 171 system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.402439 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode @@ -345,8 +372,11 @@ system.cpu.icache.demand_accesses::total 60050143 # nu system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -402,10 +432,15 @@ system.cpu.dcache.demand_accesses::total 15682061 # nu system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180671 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180671 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.129196 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129196 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.129196 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129196 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 6299f010e..090f52454 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -274,9 +274,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=true @@ -336,10 +335,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -395,9 +393,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index dc632ce62..b3456c80f 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:41:25 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:42:45 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 7ab3bb0af..e92359043 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -4,23 +4,50 @@ sim_seconds 1.958647 # Nu sim_ticks 1958647095000 # Number of ticks simulated final_tick 1958647095000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 669282 # Simulator instruction rate (inst/s) -host_op_rate 669282 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22085281308 # Simulator tick rate (ticks/s) -host_mem_usage 295084 # Number of bytes of host memory used -host_seconds 88.69 # Real time elapsed on the host +host_inst_rate 1245422 # Simulator instruction rate (inst/s) +host_op_rate 1245421 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41097010927 # Simulator tick rate (ticks/s) +host_mem_usage 295412 # Number of bytes of host memory used +host_seconds 47.66 # Real time elapsed on the host sim_insts 59355643 # Number of instructions simulated sim_ops 59355643 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 30050624 # Number of bytes read from this memory -system.physmem.bytes_inst_read 971200 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10333120 # Number of bytes written to this memory -system.physmem.num_reads 469541 # Number of read requests responded to by this memory -system.physmem.num_writes 161455 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 15342541 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 495852 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5275642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 20618183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0.inst 919744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 25960192 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 51456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 468416 # Number of bytes read from this memory +system.physmem.bytes_read::total 30050624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 919744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 51456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 971200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10333120 # Number of bytes written to this memory +system.physmem.bytes_written::total 10333120 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 14371 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 405628 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 804 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 7319 # Number of read requests responded to by this memory +system.physmem.num_reads::total 469541 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 161455 # Number of write requests responded to by this memory +system.physmem.num_writes::total 161455 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 469581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13254145 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1353391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26271 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 239153 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15342541 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 469581 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26271 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 495852 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5275642 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5275642 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5275642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 469581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13254145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1353391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 26271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 239153 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 20618183 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 393576 # number of replacements system.l2c.tagsinuse 34487.800710 # Cycle average of tags in use system.l2c.total_refs 2371449 # Total number of references to valid blocks. @@ -142,38 +169,50 @@ system.l2c.ReadReq_miss_rate::cpu0.inst 0.015693 # mi system.l2c.ReadReq_miss_rate::cpu0.data 0.275649 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.009368 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.033331 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.146292 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.934476 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.903285 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.929089 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.454545 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.795699 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.706349 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.408381 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.330189 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.403596 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.015693 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.304282 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.009368 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.138621 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.179301 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.015693 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.304282 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.009368 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.138621 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.179301 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52003.653190 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52017.316332 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51980.981595 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 52042.179262 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52016.667760 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 914.798206 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1575.757576 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1025.780190 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6933.333333 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4216.216216 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 4674.157303 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.458612 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000.806972 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52002.375911 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 52003.653190 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 52013.014714 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 51980.981595 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 52007.226616 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52012.540780 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52003.653190 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 52013.014714 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 51980.981595 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 52007.226616 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52012.540780 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -251,44 +290,59 @@ system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015693 system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.275649 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.033331 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.146287 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.934476 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.903285 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.929089 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.454545 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.795699 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.706349 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.408381 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.330189 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.403596 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.304282 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.138621 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.179296 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.304282 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.138621 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.179296 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40017.316332 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40042.179262 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40016.717580 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40024.867509 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40020.691995 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.458612 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000.806972 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.375911 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.014714 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40007.226616 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40012.576107 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.014714 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40007.226616 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40012.576107 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41694 # number of replacements system.iocache.tagsinuse 0.563721 # Cycle average of tags in use @@ -324,13 +378,21 @@ system.iocache.demand_accesses::total 41726 # nu system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.114943 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 115247.114943 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137701.766606 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137701.766606 # average WriteReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137608.129320 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137608.129320 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 64596068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked @@ -358,13 +420,21 @@ system.iocache.demand_mshr_miss_latency::total 3571932998 system.iocache.overall_mshr_miss_latency::tsunami.ide 3571932998 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 3571932998 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.114943 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 63247.114943 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85698.113208 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85698.113208 # average WriteReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85604.491157 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85604.491157 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85604.491157 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85604.491157 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -458,6 +528,7 @@ system.cpu0.kern.ipl_used::21 1 # fr system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::31 0.684822 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808938 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -515,7 +586,7 @@ system.cpu0.kern.mode_good::idle 0 system.cpu0.kern.mode_switch_good::kernel 0.175705 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total nan # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.298893 # fraction of useful protection mode switches system.cpu0.kern.mode_ticks::kernel 1954355762000 99.83% 99.83% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::user 3390072000 0.17% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode @@ -585,11 +656,17 @@ system.cpu0.icache.demand_accesses::total 54081252 # n system.cpu0.icache.overall_accesses::cpu0.inst 54081252 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 54081252 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016933 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.016933 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016933 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.016933 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016933 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.016933 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14664.130944 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14664.130944 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14664.130944 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14664.130944 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -613,11 +690,17 @@ system.cpu0.icache.demand_mshr_miss_latency::total 10681093500 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10681093500 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 10681093500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016933 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.016933 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.016933 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11663.370937 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11663.370937 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11663.370937 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 1338438 # number of replacements system.cpu0.dcache.tagsinuse 503.524900 # Cycle average of tags in use @@ -677,17 +760,29 @@ system.cpu0.dcache.demand_accesses::total 14308776 # n system.cpu0.dcache.overall_accesses::cpu0.data 14308776 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14308776 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122512 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.122512 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049821 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049821 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085698 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085698 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002134 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002134 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092785 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092785 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092785 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092785 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25644.487844 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25644.487844 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31248.127161 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 31248.127161 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14201.462766 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14201.462766 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7251.219512 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7251.219512 # average StoreCondReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26874.991809 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 26874.991809 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -729,20 +824,35 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1242107000 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2126577000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2126577000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122512 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122512 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049821 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049821 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085698 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085698 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002134 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002134 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092785 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092785 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092785 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092785 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22644.451168 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22644.451168 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28248.127161 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28248.127161 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11201.462766 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11201.462766 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4251.219512 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4251.219512 # average StoreCondReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23874.963186 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23874.963186 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses @@ -820,6 +930,7 @@ system.cpu1.kern.ipl_used::0 0.998923 # fr system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::31 0.523674 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.710351 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -860,7 +971,7 @@ system.cpu1.kern.mode_good::idle 13 system.cpu1.kern.mode_switch_good::kernel 0.593284 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.006298 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.599582 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.286315 # fraction of useful protection mode switches system.cpu1.kern.mode_ticks::kernel 3571416000 0.18% 0.18% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 1745054000 0.09% 0.27% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 1953329865000 99.73% 100.00% # number of ticks spent at the given mode @@ -899,11 +1010,17 @@ system.cpu1.icache.demand_accesses::total 5286354 # n system.cpu1.icache.overall_accesses::cpu1.inst 5286354 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 5286354 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016458 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.016458 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016458 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.016458 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016458 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.016458 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14488.908683 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14488.908683 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14488.908683 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14488.908683 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -927,11 +1044,17 @@ system.cpu1.icache.demand_mshr_miss_latency::total 999558500 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 999558500 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::total 999558500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016458 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.016458 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.016458 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11488.517901 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11488.517901 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11488.517901 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 52960 # number of replacements system.cpu1.dcache.tagsinuse 389.521271 # Cycle average of tags in use @@ -991,17 +1114,29 @@ system.cpu1.dcache.demand_accesses::total 1677594 # n system.cpu1.dcache.overall_accesses::cpu1.data 1677594 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 1677594 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035676 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035676 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032042 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.032042 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.076923 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.076923 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.041975 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.041975 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034296 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.034296 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034296 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.034296 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14368.630938 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14368.630938 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27265.853778 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 27265.853778 # average WriteReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13318.737271 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13318.737271 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12704.950495 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 12704.950495 # average StoreCondReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18946.344770 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18946.344770 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18946.344770 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18946.344770 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1043,20 +1178,35 @@ system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 298050500 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 309464000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 309464000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035676 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035676 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032042 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032042 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.076923 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.076923 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.041975 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.041975 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.034296 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034296 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11368.577048 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11368.577048 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24265.853778 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24265.853778 # average WriteReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10318.737271 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10318.737271 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9704.950495 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9704.950495 # average StoreCondReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15946.310008 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15946.310008 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index d5815e263..d6cd88975 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -181,9 +181,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=true @@ -243,10 +242,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -302,9 +300,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index 7b3033c70..33fb3404f 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:07 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:23:20 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index d0852c317..42fcfede1 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,23 +4,40 @@ sim_seconds 1.915549 # Nu sim_ticks 1915548867000 # Number of ticks simulated final_tick 1915548867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 646342 # Simulator instruction rate (inst/s) -host_op_rate 646342 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22054916762 # Simulator tick rate (ticks/s) -host_mem_usage 292620 # Number of bytes of host memory used -host_seconds 86.85 # Real time elapsed on the host +host_inst_rate 1238015 # Simulator instruction rate (inst/s) +host_op_rate 1238014 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42244373047 # Simulator tick rate (ticks/s) +host_mem_usage 292960 # Number of bytes of host memory used +host_seconds 45.34 # Real time elapsed on the host sim_insts 56137087 # Number of instructions simulated sim_ops 56137087 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 29663360 # Number of bytes read from this memory -system.physmem.bytes_inst_read 943040 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10122368 # Number of bytes written to this memory -system.physmem.num_reads 463490 # Number of read requests responded to by this memory -system.physmem.num_writes 158162 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 15485567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 492308 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5284317 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 20769884 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 943040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 26067904 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652416 # Number of bytes read from this memory +system.physmem.bytes_read::total 29663360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 943040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 943040 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10122368 # Number of bytes written to this memory +system.physmem.bytes_written::total 10122368 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 14735 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 407311 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41444 # Number of read requests responded to by this memory +system.physmem.num_reads::total 463490 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 158162 # Number of write requests responded to by this memory +system.physmem.num_writes::total 158162 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 492308 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13608582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1384677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15485567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 492308 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 492308 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5284317 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5284317 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5284317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 492308 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13608582 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1384677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 20769884 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 389289 # number of replacements system.l2c.tagsinuse 34352.038344 # Cycle average of tags in use system.l2c.total_refs 2311163 # Total number of references to valid blocks. @@ -92,20 +109,30 @@ system.l2c.overall_accesses::cpu.data 1390437 # nu system.l2c.overall_accesses::total 2318771 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.015873 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.266420 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.150967 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.538462 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.538462 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.388905 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.388905 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.inst 0.015873 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.293215 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.182179 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.inst 0.015873 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.293215 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.182179 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.inst 52002.816423 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.data 52017.238937 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52016.540189 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu.data 35428.571429 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 35428.571429 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu.data 52003.930884 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52003.930884 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52013.009194 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52013.009194 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -150,23 +177,36 @@ system.l2c.overall_mshr_uncacheable_latency::cpu.data 1856492500 system.l2c.overall_mshr_uncacheable_latency::total 1856492500 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.266420 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.150967 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.538462 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.538462 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.388905 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.388905 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.182179 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.182179 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.443163 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40017.238937 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40016.522105 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 45714.285714 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 45714.285714 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40003.930884 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40003.930884 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40012.996175 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40012.996175 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements system.iocache.tagsinuse 1.340325 # Cycle average of tags in use @@ -202,13 +242,21 @@ system.iocache.demand_accesses::total 41725 # nu system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115265.884393 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 115265.884393 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137714.208847 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137714.208847 # average WriteReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137621.133709 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137621.133709 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 64604060 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked @@ -236,13 +284,21 @@ system.iocache.demand_mshr_miss_latency::total 3572392988 system.iocache.overall_mshr_miss_latency::tsunami.ide 3572392988 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 3572392988 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63265.884393 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 63265.884393 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85710.627407 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85710.627407 # average WriteReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85617.567118 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85617.567118 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -332,6 +388,7 @@ system.cpu.kern.ipl_used::0 0.981746 # fr system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::31 0.692298 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814116 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -389,7 +446,7 @@ system.cpu.kern.mode_good::idle 168 system.cpu.kern.mode_switch_good::kernel 0.322887 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.080306 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.403193 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.391657 # fraction of useful protection mode switches system.cpu.kern.mode_ticks::kernel 45253274000 2.36% 2.36% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::user 5124228000 0.27% 2.63% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::idle 1865170605000 97.37% 100.00% # number of ticks spent at the given mode @@ -459,11 +516,17 @@ system.cpu.icache.demand_accesses::total 56148907 # nu system.cpu.icache.overall_accesses::cpu.inst 56148907 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 56148907 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016534 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016534 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.016534 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016534 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.016534 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016534 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14667.218001 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14667.218001 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14667.218001 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14667.218001 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -487,11 +550,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 10830625500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10830625500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 10830625500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016534 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016534 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016534 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11666.482290 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11666.482290 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11666.482290 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11666.482290 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1390115 # number of replacements system.cpu.dcache.tagsinuse 511.984023 # Cycle average of tags in use @@ -547,15 +616,25 @@ system.cpu.dcache.demand_accesses::total 15029535 # nu system.cpu.dcache.overall_accesses::cpu.data 15029535 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15029535 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120441 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120441 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049462 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049462 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085908 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085908 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.091383 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091383 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.091383 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091383 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25368.690313 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25368.690313 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30323.439631 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30323.439631 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14300.331376 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14300.331376 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26466.589124 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26466.589124 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,18 +672,31 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1199607500 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2062370500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 2062370500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120441 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120441 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049462 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049462 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085908 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085908 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091383 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091383 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22368.647754 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22368.647754 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27323.439631 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27323.439631 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11300.331376 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11300.331376 # average LoadLockedReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23466.555996 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23466.555996 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |