diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-12-05 16:48:34 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-12-05 16:48:34 -0500 |
| commit | ebd9018a139178aed432b257ff4ce6dc2d5f795f (patch) | |
| tree | 0d844028751908a7c7f66f82e5bd9564467086c9 /tests/quick/fs/10.linux-boot/ref/alpha | |
| parent | 9e57e4e89d3c6b6d7e0f0f182bfd01c5585c16c5 (diff) | |
| download | gem5-ebd9018a139178aed432b257ff4ce6dc2d5f795f.tar.xz | |
stats: Update stats to reflect cache changes
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha')
4 files changed, 1900 insertions, 1896 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 279bf5056..54bff4f85 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.869358 # Number of seconds simulated -sim_ticks 1869357999000 # Number of ticks simulated -final_tick 1869357999000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1869358054000 # Number of ticks simulated +final_tick 1869358054000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2913867 # Simulator instruction rate (inst/s) -host_op_rate 2913866 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 83800980413 # Simulator tick rate (ticks/s) -host_mem_usage 338264 # Number of bytes of host memory used -host_seconds 22.31 # Real time elapsed on the host +host_inst_rate 2951277 # Simulator instruction rate (inst/s) +host_op_rate 2951276 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 84876880961 # Simulator tick rate (ticks/s) +host_mem_usage 336132 # Number of bytes of host memory used +host_seconds 22.02 # Real time elapsed on the host sim_insts 64999904 # Number of instructions simulated sim_ops 64999904 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.inst 758272 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 66535744 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 106112 # Number of bytes read from this memory @@ -34,11 +34,11 @@ system.physmem.num_reads::total 1065117 # Nu system.physmem.num_writes::writebacks 122467 # Number of write requests responded to by this memory system.physmem.num_writes::total 122467 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.inst 405632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35592831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35592830 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 56764 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 409980 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36465721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36465720 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 405632 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 56764 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 462396 # Instruction read bandwidth from this memory (bytes/s) @@ -46,13 +46,13 @@ system.physmem.bw_write::writebacks 4192823 # Wr system.physmem.bw_write::total 4192823 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 4192823 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 405632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35592831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35592830 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 56764 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 409980 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40658545 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.physmem.bw_total::total 40658544 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses @@ -88,15 +88,15 @@ system.cpu0.itb.data_acv 0 # DT system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.numPwrStateTransitions 13588 # Number of power state transitions system.cpu0.pwrStateClkGateDist::samples 6794 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 271506704.857374 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 434955692.191892 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 271506712.952752 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 434955679.637595 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1000-5e+10 6794 100.00% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 21000 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::total 6794 # Distribution of time spent in the clock gated state system.cpu0.pwrStateResidencyTicks::ON 24741446199 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1844616552801 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 3738722793 # number of cpu cycles simulated +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1844616607801 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 3738722903 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed @@ -114,12 +114,12 @@ system.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # nu system.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1853222732000 99.14% 99.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1853222787000 99.14% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::31 15975327000 0.85% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1869357791500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1869357846500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -154,7 +154,7 @@ system.cpu0.kern.mode_switch_good::kernel 0.177764 # f system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.301957 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1868349163500 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1868349218500 99.95% 99.95% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::user 1008627000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 2744 # number of times the context was actually changed @@ -173,8 +173,8 @@ system.cpu0.num_fp_register_writes 98967 # nu system.cpu0.num_mem_refs 12536107 # number of memory refs system.cpu0.num_load_insts 7783754 # Number of load instructions system.cpu0.num_store_insts 4752353 # Number of store instructions -system.cpu0.num_idle_cycles 3689239810.666409 # Number of idle cycles -system.cpu0.num_busy_cycles 49482982.333591 # Number of busy cycles +system.cpu0.num_idle_cycles 3689239920.666412 # Number of idle cycles +system.cpu0.num_busy_cycles 49482982.333588 # Number of busy cycles system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles system.cpu0.Branches 7530826 # Number of branches fetched @@ -217,14 +217,14 @@ system.cpu0.op_class::FloatMemWrite 81881 0.17% 98.63% # Cl system.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 49485886 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 1781367 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.187330 # Cycle average of tags in use +system.cpu0.dcache.tags.tagsinuse 506.187332 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 10705767 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 1781879 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 6.008134 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187330 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187332 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -234,7 +234,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 51822038 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 51822038 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 6068885 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 6068885 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 4360096 # number of WriteReq hits @@ -291,7 +291,7 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.writebacks::writebacks 633925 # number of writebacks system.cpu0.dcache.writebacks::total 633925 # number of writebacks -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 618292 # number of replacements system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks. @@ -308,7 +308,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::2 333 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 50104825 # Number of tag accesses system.cpu0.icache.tags.data_accesses 50104825 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.cpu0.icache.ReadReq_hits::cpu0.inst 48866947 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 48866947 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 48866947 # number of demand (read+write) hits @@ -375,15 +375,15 @@ system.cpu1.itb.data_acv 0 # DT system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.numPwrStateTransitions 5407 # Number of power state transitions system.cpu1.pwrStateClkGateDist::samples 2704 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 688459933.247041 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 437290592.854298 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 688459953.587278 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 437290552.872181 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1000-5e+10 2704 100.00% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::max_value 976035500 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::total 2704 # Distribution of time spent in the clock gated state system.cpu1.pwrStateResidencyTicks::ON 7762339500 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1861595659500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 3738296609 # number of cpu cycles simulated +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1861595714500 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 3738296719 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -399,11 +399,11 @@ system.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # nu system.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1856123501500 99.30% 99.30% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::0 1856123556500 99.30% 99.30% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::31 12870743500 0.69% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1869146939500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1869146994500 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl @@ -439,7 +439,7 @@ system.cpu1.kern.mode_switch_good::idle 0.177356 # fr system.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches system.cpu1.kern.mode_ticks::kernel 5986368000 0.32% 0.32% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1862102413500 99.66% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1862102446500 99.66% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2507 # number of times the context was actually changed system.cpu1.committedInsts 15522159 # Number of instructions committed system.cpu1.committedOps 15522159 # Number of ops (including micro ops) committed @@ -456,8 +456,8 @@ system.cpu1.num_fp_register_writes 104129 # nu system.cpu1.num_mem_refs 4961786 # number of memory refs system.cpu1.num_load_insts 2849090 # Number of load instructions system.cpu1.num_store_insts 2112696 # Number of store instructions -system.cpu1.num_idle_cycles 3722773671.474783 # Number of idle cycles -system.cpu1.num_busy_cycles 15522937.525217 # Number of busy cycles +system.cpu1.num_idle_cycles 3722773781.474732 # Number of idle cycles +system.cpu1.num_busy_cycles 15522937.525268 # Number of busy cycles system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles system.cpu1.Branches 2214163 # Number of branches fetched @@ -500,14 +500,14 @@ system.cpu1.op_class::FloatMemWrite 90649 0.58% 97.27% # Cl system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 15525875 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.tags.replacements 201757 # number of replacements -system.cpu1.dcache.tags.tagsinuse 497.601962 # Cycle average of tags in use +system.cpu1.dcache.tags.tagsinuse 497.601957 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 4718401 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 202065 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 23.350907 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601962 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601957 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971879 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.971879 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id @@ -516,7 +516,7 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.601562 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 20020608 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 20020608 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.ReadReq_hits::cpu1.data 2632688 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 2632688 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 1954647 # number of WriteReq hits @@ -573,14 +573,14 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.writebacks::writebacks 144832 # number of writebacks system.cpu1.dcache.writebacks::total 144832 # number of writebacks -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.cpu1.icache.tags.replacements 380647 # number of replacements -system.cpu1.icache.tags.tagsinuse 453.133719 # Cycle average of tags in use +system.cpu1.icache.tags.tagsinuse 453.133721 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 381159 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 39.733253 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1859777195500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133719 # Average occupied blocks per requestor +system.cpu1.icache.tags.warmup_cycle 1859777228500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133721 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -589,7 +589,7 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.icache.tags.tag_accesses 15907063 # Number of tag accesses system.cpu1.icache.tags.data_accesses 15907063 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.cpu1.icache.ReadReq_hits::cpu1.inst 15144687 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 15144687 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 15144687 # number of demand (read+write) hits @@ -634,7 +634,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7628 # Transaction distribution system.iobus.trans_dist::ReadResp 7628 # Transaction distribution system.iobus.trans_dist::WriteReq 56140 # Transaction distribution @@ -665,7 +665,7 @@ system.iobus.pkt_size_system.bridge.master::total 86162 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2747818 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41699 # number of replacements system.iocache.tags.tagsinuse 0.434096 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -680,7 +680,7 @@ system.iocache.tags.age_task_id_blocks_1023::2 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375579 # Number of tag accesses system.iocache.tags.data_accesses 375579 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses system.iocache.ReadReq_misses::total 179 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -713,18 +713,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 999962 # number of replacements -system.l2c.tags.tagsinuse 65520.418446 # Cycle average of tags in use -system.l2c.tags.total_refs 4560628 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 65520.418445 # Cycle average of tags in use +system.l2c.tags.total_refs 4560627 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 1065470 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.280391 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 4.280390 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 618103500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 304.654016 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4865.757369 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58473.870947 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 175.171504 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1700.964609 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 304.654012 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4865.757484 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58473.870624 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 175.171542 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1700.964784 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.004649 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.074246 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.892240 # Average percentage of cache occupancy @@ -738,13 +738,13 @@ system.l2c.tags.age_task_id_blocks_1024::2 2462 # system.l2c.tags.age_task_id_blocks_1024::3 9328 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 50633 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.999573 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 46077158 # Number of tag accesses -system.l2c.tags.data_accesses 46077158 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.l2c.tags.tag_accesses 46077150 # Number of tag accesses +system.l2c.tags.data_accesses 46077150 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.l2c.WritebackDirty_hits::writebacks 778757 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 778757 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 721480 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 721480 # number of WritebackClean hits +system.l2c.WritebackClean_hits::writebacks 721479 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 721479 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 3102 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 2744 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 5846 # number of UpgradeReq hits @@ -796,8 +796,8 @@ system.l2c.overall_misses::cpu1.data 12080 # nu system.l2c.overall_misses::total 1065509 # number of overall misses system.l2c.WritebackDirty_accesses::writebacks 778757 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackDirty_accesses::total 778757 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 721480 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 721480 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 721479 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 721479 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 3106 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 2746 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 5852 # number of UpgradeReq accesses(hits+misses) @@ -856,12 +856,12 @@ system.l2c.avg_blocked_cycles::no_targets nan # a system.l2c.writebacks::writebacks 80947 # number of writebacks system.l2c.writebacks::total 80947 # number of writebacks system.membus.snoop_filter.tot_requests 2174394 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1068384 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 430 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 1068314 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 544 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7449 # Transaction distribution system.membus.trans_dist::ReadResp 948786 # Transaction distribution system.membus.trans_dist::WriteReq 14588 # Transaction distribution @@ -891,24 +891,24 @@ system.membus.pkt_size::total 76119890 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 2196431 # Request fanout histogram -system.membus.snoop_fanout::mean 0.000519 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.022766 # Request fanout histogram +system.membus.snoop_fanout::mean 0.000560 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.023658 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2195292 99.95% 99.95% # Request fanout histogram -system.membus.snoop_fanout::1 1139 0.05% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2195201 99.94% 99.94% # Request fanout histogram +system.membus.snoop_fanout::1 1230 0.06% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 2196431 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.toL2Bus.snoop_filter.tot_requests 6035809 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 3018662 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 374456 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1621 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1531 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_single_requests 3010644 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 386637 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1627 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1537 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2732152 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution @@ -933,25 +933,25 @@ system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1558 system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 48757440 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23377367 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 307135186 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1000983 # Total snoops (count) -system.toL2Bus.snoopTraffic 5197312 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 7058665 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.106769 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.309069 # Request fanout histogram +system.toL2Bus.snoops 1001076 # Total snoops (count) +system.toL2Bus.snoopTraffic 5203008 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 7058756 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.107956 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.310579 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 6305559 89.33% 89.33% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 752566 10.66% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 6297275 89.21% 89.21% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 760929 10.78% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 550 0.01% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7058665 # Request fanout histogram -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_fanout::total 7058756 # Request fanout histogram +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -983,28 +983,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 5428662b5..50044fb27 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.829332 # Number of seconds simulated -sim_ticks 1829332003500 # Number of ticks simulated -final_tick 1829332003500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1829332014500 # Number of ticks simulated +final_tick 1829332014500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2961606 # Simulator instruction rate (inst/s) -host_op_rate 2961604 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90238056091 # Simulator tick rate (ticks/s) -host_mem_usage 333656 # Number of bytes of host memory used -host_seconds 20.27 # Real time elapsed on the host +host_inst_rate 3082632 # Simulator instruction rate (inst/s) +host_op_rate 3082630 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 93925630949 # Simulator tick rate (ticks/s) +host_mem_usage 334080 # Number of bytes of host memory used +host_seconds 19.48 # Real time elapsed on the host sim_insts 60038469 # Number of instructions simulated sim_ops 60038469 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 66835072 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory @@ -29,7 +29,7 @@ system.physmem.num_reads::total 1057602 # Nu system.physmem.num_writes::writebacks 115871 # Number of write requests responded to by this memory system.physmem.num_writes::total 115871 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 464922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36535234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36535233 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 37000680 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 464922 # Instruction read bandwidth from this memory (bytes/s) @@ -38,11 +38,11 @@ system.physmem.bw_write::writebacks 4053799 # Wr system.physmem.bw_write::total 4053799 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 4053799 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 464922 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36535234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36535233 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 41054479 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -78,15 +78,15 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.numPwrStateTransitions 12714 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 6357 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 283043477.146767 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 441371906.848107 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 283043478.877143 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 441371901.217911 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 6357 100.00% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 386000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 6357 # Distribution of time spent in the clock gated state system.cpu.pwrStateResidencyTicks::ON 30024619278 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1799307384222 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 3658670365 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::CLK_GATED 1799307395222 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 3658670387 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed @@ -102,11 +102,11 @@ system.cpu.kern.ipl_good::21 243 0.16% 49.46% # nu system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1811929137500 99.05% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1811929148500 99.05% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1829331796000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1829331807000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -141,7 +141,7 @@ system.cpu.kern.mode_switch_good::idle 0.081545 # fr system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1801033409500 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1801033420500 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.committedInsts 60038469 # Number of instructions committed system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed @@ -158,8 +158,8 @@ system.cpu.num_fp_register_writes 166520 # nu system.cpu.num_mem_refs 16115703 # number of memory refs system.cpu.num_load_insts 9747509 # Number of load instructions system.cpu.num_store_insts 6368194 # Number of store instructions -system.cpu.num_idle_cycles 3598621022.088898 # Number of idle cycles -system.cpu.num_busy_cycles 60049342.911102 # Number of busy cycles +system.cpu.num_idle_cycles 3598621044.088899 # Number of idle cycles +system.cpu.num_busy_cycles 60049342.911101 # Number of busy cycles system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983587 # Percentage of idle cycles system.cpu.Branches 9064428 # Number of branches fetched @@ -202,12 +202,12 @@ system.cpu.op_class::FloatMemWrite 138108 0.23% 98.42% # Cl system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 60050307 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2042707 # number of replacements +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2042708 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14038420 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2043219 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 6.870737 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 14038419 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2043220 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 6.870733 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy @@ -217,31 +217,31 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 66369780 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 66369780 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7807772 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807772 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 66369781 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 66369781 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 5848209 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 5848209 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655981 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655981 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655981 # number of overall hits -system.cpu.dcache.overall_hits::total 13655981 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721711 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721711 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 13655980 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655980 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655980 # number of overall hits +system.cpu.dcache.overall_hits::total 13655980 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304363 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 304363 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses -system.cpu.dcache.overall_misses::total 2026074 # number of overall misses +system.cpu.dcache.demand_misses::cpu.data 2026075 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026075 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026075 # number of overall misses +system.cpu.dcache.overall_misses::total 2026075 # number of overall misses system.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses) @@ -272,12 +272,12 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 833476 # number of writebacks system.cpu.dcache.writebacks::total 833476 # number of writebacks -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 919606 # number of replacements +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 919605 # number of replacements system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 59130074 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 920118 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 64.263577 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 59130075 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 920117 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 64.263648 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy @@ -287,21 +287,21 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 63 system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60970540 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60970540 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 59130074 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59130074 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59130074 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59130074 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59130074 # number of overall hits -system.cpu.icache.overall_hits::total 59130074 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 920233 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 920233 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 920233 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 920233 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 920233 # number of overall misses -system.cpu.icache.overall_misses::total 920233 # number of overall misses +system.cpu.icache.tags.tag_accesses 60970539 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60970539 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 59130075 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59130075 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59130075 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59130075 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59130075 # number of overall hits +system.cpu.icache.overall_hits::total 59130075 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 920232 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 920232 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 920232 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 920232 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 920232 # number of overall misses +system.cpu.icache.overall_misses::total 920232 # number of overall misses system.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses @@ -320,18 +320,18 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 919606 # number of writebacks -system.cpu.icache.writebacks::total 919606 # number of writebacks -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states +system.cpu.icache.writebacks::writebacks 919605 # number of writebacks +system.cpu.icache.writebacks::total 919605 # number of writebacks +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 992419 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65520.104765 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 65520.104764 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4865571 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1057941 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.599095 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 264.552906 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4852.732213 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 60402.819646 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4852.732204 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 60402.819654 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.004037 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074047 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.921674 # Average percentage of cache occupancy @@ -345,24 +345,24 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55077 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 48449706 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 48449706 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 833476 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 833476 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 919354 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 919354 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::writebacks 919353 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 919353 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 12 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 12 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 187293 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 187293 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906926 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 906926 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811229 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 811229 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906926 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998522 # number of demand (read+write) hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906925 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 906925 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811230 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 811230 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 906925 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998523 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1905448 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906926 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998522 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 906925 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998523 # number of overall hits system.cpu.l2cache.overall_hits::total 1905448 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 4 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 4 # number of UpgradeReq misses @@ -380,21 +380,21 @@ system.cpu.l2cache.overall_misses::cpu.data 1044698 # system.cpu.l2cache.overall_misses::total 1057987 # number of overall misses system.cpu.l2cache.WritebackDirty_accesses::writebacks 833476 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 833476 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 919354 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 919354 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 919353 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 919353 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 304347 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 304347 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920215 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 920215 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738873 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1738873 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 920215 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920214 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 920214 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738874 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1738874 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 920214 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2043221 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 2963435 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 920215 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 920214 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2043221 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2963435 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.250000 # miss rate for UpgradeReq accesses @@ -419,44 +419,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.writebacks::writebacks 74359 # number of writebacks system.cpu.l2cache.writebacks::total 74359 # number of writebacks system.cpu.toL2Bus.snoop_filter.tot_requests 5925782 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962435 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1834 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962349 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2223 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1449 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1449 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2666290 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 833476 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 919606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1209231 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 919605 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1209232 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 304347 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 304347 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 920233 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738873 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760072 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163223 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 920232 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738874 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760069 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163226 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 8923295 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117749696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184154670 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 301904366 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 993364 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4774656 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 6936011 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000753 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.027431 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117749568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184154734 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 301904302 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 993442 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4779456 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 6936088 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000848 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.029106 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6930788 99.92% 99.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5223 0.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6930207 99.92% 99.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5881 0.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6936011 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 6936088 # Request fanout histogram system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -469,7 +469,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7358 # Transaction distribution system.iobus.trans_dist::ReadResp 7358 # Transaction distribution system.iobus.trans_dist::WriteReq 51390 # Transaction distribution @@ -500,14 +500,14 @@ system.iobus.pkt_size_system.bridge.master::total 46126 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41686 # number of replacements -system.iocache.tags.tagsinuse 1.225569 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 1685780588017 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.225569 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -515,7 +515,7 @@ system.iocache.tags.age_task_id_blocks_1023::2 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375534 # Number of tag accesses system.iocache.tags.data_accesses 375534 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -549,12 +549,12 @@ system.iocache.avg_blocked_cycles::no_targets nan system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks system.membus.snoop_filter.tot_requests 2132776 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1034179 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 408 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 1034104 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 505 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7184 # Transaction distribution system.membus.trans_dist::ReadResp 948291 # Transaction distribution system.membus.trans_dist::WriteReq 9838 # Transaction distribution @@ -583,21 +583,21 @@ system.membus.pkt_size::total 75175918 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 2149798 # Request fanout histogram -system.membus.snoop_fanout::mean 0.000494 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.022210 # Request fanout histogram +system.membus.snoop_fanout::mean 0.000529 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.023002 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2148737 99.95% 99.95% # Request fanout histogram -system.membus.snoop_fanout::1 1061 0.05% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2148660 99.95% 99.95% # Request fanout histogram +system.membus.snoop_fanout::1 1138 0.05% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 2149798 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -629,28 +629,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 66d295a56..5f20e9468 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,65 +1,65 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.966742 # Number of seconds simulated -sim_ticks 1966741627000 # Number of ticks simulated -final_tick 1966741627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1966742176000 # Number of ticks simulated +final_tick 1966742176000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1661877 # Simulator instruction rate (inst/s) -host_op_rate 1661877 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53617278530 # Simulator tick rate (ticks/s) -host_mem_usage 335968 # Number of bytes of host memory used -host_seconds 36.68 # Real time elapsed on the host -sim_insts 60959478 # Number of instructions simulated -sim_ops 60959478 # Number of ops (including micro ops) simulated +host_inst_rate 1742915 # Simulator instruction rate (inst/s) +host_op_rate 1742915 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56229643103 # Simulator tick rate (ticks/s) +host_mem_usage 335876 # Number of bytes of host memory used +host_seconds 34.98 # Real time elapsed on the host +sim_insts 60961842 # Number of instructions simulated +sim_ops 60961842 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 796480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24829632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 62464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 430848 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 796800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24828736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 62272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 430784 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26120384 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 796480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 62464 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 858944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7775296 # Number of bytes written to this memory -system.physmem.bytes_written::total 7775296 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12445 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387963 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 976 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6732 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26119552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 796800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 62272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 859072 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7774400 # Number of bytes written to this memory +system.physmem.bytes_written::total 7774400 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12450 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387949 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 973 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6731 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 408131 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121489 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121489 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 404974 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12624755 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 31760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 219067 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 408118 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121475 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121475 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 405137 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12624296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 31663 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 219034 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13281045 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 404974 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 31760 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 436735 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3953390 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3953390 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3953390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 404974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12624755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 31760 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 219067 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13280618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 405137 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 31663 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 436800 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3952933 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3952933 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3952933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 405137 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12624296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 31663 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 219034 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17234435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 408131 # Number of read requests accepted -system.physmem.writeReqs 121489 # Number of write requests accepted -system.physmem.readBursts 408131 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121489 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26113216 # Total number of bytes read from DRAM +system.physmem.bw_total::total 17233551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 408118 # Number of read requests accepted +system.physmem.writeReqs 121475 # Number of write requests accepted +system.physmem.readBursts 408118 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121475 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26112384 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue -system.physmem.bytesWritten 7773568 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26120384 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7775296 # Total written bytes from the system interface side +system.physmem.bytesWritten 7772672 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26119552 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7774400 # Total written bytes from the system interface side system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write @@ -73,12 +73,12 @@ system.physmem.perBankRdBursts::6 26012 # Pe system.physmem.perBankRdBursts::7 25110 # Per bank write bursts system.physmem.perBankRdBursts::8 25002 # Per bank write bursts system.physmem.perBankRdBursts::9 25326 # Per bank write bursts -system.physmem.perBankRdBursts::10 25348 # Per bank write bursts +system.physmem.perBankRdBursts::10 25349 # Per bank write bursts system.physmem.perBankRdBursts::11 25350 # Per bank write bursts -system.physmem.perBankRdBursts::12 25736 # Per bank write bursts -system.physmem.perBankRdBursts::13 25396 # Per bank write bursts +system.physmem.perBankRdBursts::12 25737 # Per bank write bursts +system.physmem.perBankRdBursts::13 25386 # Per bank write bursts system.physmem.perBankRdBursts::14 25673 # Per bank write bursts -system.physmem.perBankRdBursts::15 25838 # Per bank write bursts +system.physmem.perBankRdBursts::15 25833 # Per bank write bursts system.physmem.perBankWrBursts::0 7888 # Per bank write bursts system.physmem.perBankWrBursts::1 7973 # Per bank write bursts system.physmem.perBankWrBursts::2 7891 # Per bank write bursts @@ -89,30 +89,30 @@ system.physmem.perBankWrBursts::6 8079 # Pe system.physmem.perBankWrBursts::7 7030 # Per bank write bursts system.physmem.perBankWrBursts::8 7056 # Per bank write bursts system.physmem.perBankWrBursts::9 7058 # Per bank write bursts -system.physmem.perBankWrBursts::10 7243 # Per bank write bursts +system.physmem.perBankWrBursts::10 7244 # Per bank write bursts system.physmem.perBankWrBursts::11 7671 # Per bank write bursts system.physmem.perBankWrBursts::12 7657 # Per bank write bursts -system.physmem.perBankWrBursts::13 7555 # Per bank write bursts +system.physmem.perBankWrBursts::13 7545 # Per bank write bursts system.physmem.perBankWrBursts::14 7813 # Per bank write bursts -system.physmem.perBankWrBursts::15 7948 # Per bank write bursts +system.physmem.perBankWrBursts::15 7943 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 71 # Number of times write queue was full causing retry -system.physmem.totGap 1966734334500 # Total gap between requests +system.physmem.totGap 1966734882500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 408131 # Read request sizes (log2) +system.physmem.readPktSize::6 408118 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 121489 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407926 # What read queue length does an incoming req see +system.physmem.writePktSize::6 121475 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407913 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 80 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -159,118 +159,118 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8059 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 7676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 293 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 248 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 163 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65984 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 513.560621 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 309.956643 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.656575 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15493 23.48% 23.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12381 18.76% 42.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4640 7.03% 49.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3311 5.02% 54.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3269 4.95% 59.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1542 2.34% 61.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1639 2.48% 64.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1098 1.66% 65.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22611 34.27% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65984 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5405 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.487327 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2871.274927 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5402 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::58 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 156 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65997 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 513.433277 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 309.806046 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.661980 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15519 23.51% 23.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12333 18.69% 42.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4691 7.11% 49.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3281 4.97% 54.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3296 4.99% 59.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1531 2.32% 61.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1650 2.50% 64.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1071 1.62% 65.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22625 34.28% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65997 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5403 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.512863 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2871.806103 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5400 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5405 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5405 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.472155 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.786030 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.242091 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4888 90.43% 90.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 28 0.52% 90.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 175 3.24% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 6 0.11% 94.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 5 0.09% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 18 0.33% 94.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 9 0.17% 94.89% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5403 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5403 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.477883 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.790649 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.259878 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4886 90.43% 90.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 27 0.50% 90.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 174 3.22% 94.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 7 0.13% 94.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 5 0.09% 94.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 18 0.33% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 10 0.19% 94.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-79 2 0.04% 94.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 25 0.46% 95.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.09% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 152 2.81% 98.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 23 0.43% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 6 0.11% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 26 0.48% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 6 0.11% 95.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 152 2.81% 98.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 23 0.43% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 4 0.07% 98.83% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::120-127 3 0.06% 98.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-135 4 0.07% 98.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::136-143 5 0.09% 99.06% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::144-151 2 0.04% 99.09% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::152-159 1 0.02% 99.11% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-167 1 0.02% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 6 0.11% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 7 0.13% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 9 0.17% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 5 0.09% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 7 0.13% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 10 0.19% 99.54% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::192-199 7 0.13% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 4 0.07% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 6 0.11% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 3 0.06% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 3 0.06% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 6 0.11% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.07% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::256-263 2 0.04% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::336-343 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5405 # Writes before turning the bus around for reads -system.physmem.totQLat 6252046750 # Total ticks spent queuing -system.physmem.totMemAccLat 13902403000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2040095000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15322.93 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5403 # Writes before turning the bus around for reads +system.physmem.totQLat 6253232750 # Total ticks spent queuing +system.physmem.totMemAccLat 13903345250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2040030000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15326.33 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34072.93 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 34076.33 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.28 # Average system read bandwidth in MiByte/s @@ -280,74 +280,74 @@ system.physmem.busUtil 0.13 # Da system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.83 # Average write queue length when enqueuing -system.physmem.readRowHits 365911 # Number of row buffer hits during reads +system.physmem.avgWrQLen 22.81 # Average write queue length when enqueuing +system.physmem.readRowHits 365871 # Number of row buffer hits during reads system.physmem.writeRowHits 97586 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.32 # Row buffer hit rate for writes -system.physmem.avgGap 3713482.00 # Average gap between requests +system.physmem.readRowHitRate 89.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.33 # Row buffer hit rate for writes +system.physmem.avgGap 3713672.35 # Average gap between requests system.physmem.pageHitRate 87.53 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 236241180 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125565165 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 236455380 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125679015 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 1459059000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 320826420 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5643624480.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5139412980 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 370844640 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 13440056220 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 6440902560 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 458973488295 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 492152011950 # Total energy per rank (pJ) -system.physmem_0.averagePower 250.237247 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1954499558250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 615960500 # Time in different power states -system.physmem_0.memoryStateTime::REF 2400520000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1908253811750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 16773151500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9224451750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 29473731500 # Time in different power states -system.physmem_1.actEnergy 234884580 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 124844115 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1454196660 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 313205220 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5773313520.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5158429890 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 364374240 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 13818451860 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 6703686720 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 458612092095 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 492560034510 # Total energy per rank (pJ) -system.physmem_1.averagePower 250.444709 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1954406570250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 598675750 # Time in different power states -system.physmem_1.memoryStateTime::REF 2455572000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1906713566750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 17457468500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9212976500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 30303367500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.physmem_0.refreshEnergy 5647926960.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5154923820 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 376838880 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 13418648160 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 6443555040 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 458974810065 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 492161345970 # Total energy per rank (pJ) +system.physmem_0.averagePower 250.241923 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1954449369000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 631981750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2402382000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1908243357500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 16780134250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9257305750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 29427014750 # Time in different power states +system.physmem_1.actEnergy 234763200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 124779600 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1454103840 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 313132140 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5778230640.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5151828720 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 364649760 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 13829543490 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 6726228480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 458595076560 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 492575015880 # Total energy per rank (pJ) +system.physmem_1.averagePower 250.452256 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1954420956750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 598934250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2457676000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1906644575500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 17516296750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9196775500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 30327918000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7479115 # DTB read hits +system.cpu0.dtb.read_hits 7479524 # DTB read hits system.cpu0.dtb.read_misses 7764 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 524068 # DTB read accesses -system.cpu0.dtb.write_hits 5079820 # DTB write hits +system.cpu0.dtb.write_hits 5079926 # DTB write hits system.cpu0.dtb.write_misses 909 # DTB write misses system.cpu0.dtb.write_acv 133 # DTB write access violations system.cpu0.dtb.write_accesses 202594 # DTB write accesses -system.cpu0.dtb.data_hits 12558935 # DTB hits +system.cpu0.dtb.data_hits 12559450 # DTB hits system.cpu0.dtb.data_misses 8673 # DTB misses system.cpu0.dtb.data_acv 343 # DTB access violations system.cpu0.dtb.data_accesses 726662 # DTB accesses -system.cpu0.itb.fetch_hits 3638634 # ITB hits +system.cpu0.itb.fetch_hits 3638587 # ITB hits system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3642618 # ITB accesses +system.cpu0.itb.fetch_accesses 3642571 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -360,55 +360,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 13588 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6794 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 272289101.854578 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 432882462.064242 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6794 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 249000 # Distribution of time spent in the clock gated state +system.cpu0.numPwrStateTransitions 13586 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 6793 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 272328046.518475 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 432907003.390448 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 6793 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 169000 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6794 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 116809469000 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849932158000 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 3933483254 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::total 6793 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 116817756000 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849924420000 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 3933484352 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 163850 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56218 40.17% 40.17% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6793 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 163848 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56217 40.17% 40.17% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 131 0.09% 40.26% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1975 1.41% 41.67% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 433 0.31% 41.98% # number of times we switched to this ipl system.cpu0.kern.ipl_count::31 81195 58.02% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 139952 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 55706 49.07% 49.07% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::total 139951 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 55705 49.07% 49.07% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1975 1.74% 50.93% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 433 0.38% 51.31% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55273 48.69% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 113518 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1903167810000 96.77% 96.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 93266000 0.00% 96.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 790441500 0.04% 96.81% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 321171500 0.02% 96.83% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 62368212000 3.17% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1966740901000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990893 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 55272 48.69% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 113516 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1903162232500 96.77% 96.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 93267000 0.00% 96.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 789745000 0.04% 96.81% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 321096500 0.02% 96.83% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 62375109000 3.17% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1966741450000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990892 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.680744 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811121 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.680732 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811112 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wripir 525 0.35% 0.36% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3064 2.07% 2.43% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3063 2.07% 2.43% # number of callpals executed system.cpu0.kern.callpal::tbi 51 0.03% 2.46% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.46% # number of callpals executed -system.cpu0.kern.callpal::swpipl 133000 89.79% 92.25% # number of callpals executed +system.cpu0.kern.callpal::swpipl 132999 89.79% 92.25% # number of callpals executed system.cpu0.kern.callpal::rdps 6513 4.40% 96.65% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.65% # number of callpals executed system.cpu0.kern.callpal::wrusp 4 0.00% 96.65% # number of callpals executed @@ -417,247 +417,247 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.66% # nu system.cpu0.kern.callpal::rti 4412 2.98% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 394 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 148125 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6988 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1369 # number of protection mode switches +system.cpu0.kern.callpal::total 148123 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6987 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1368 -system.cpu0.kern.mode_good::user 1369 +system.cpu0.kern.mode_good::kernel 1369 +system.cpu0.kern.mode_good::user 1370 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.195764 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.195935 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.327510 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1962821824500 99.80% 99.80% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3919074500 0.20% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.327749 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1962822047500 99.80% 99.80% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3919400500 0.20% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3065 # number of times the context was actually changed -system.cpu0.committedInsts 47690735 # Number of instructions committed -system.cpu0.committedOps 47690735 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44243506 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 210072 # Number of float alu accesses -system.cpu0.num_func_calls 1190980 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5607273 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44243506 # number of integer instructions -system.cpu0.num_fp_insts 210072 # number of float instructions -system.cpu0.num_int_register_reads 60857324 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32955789 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 102653 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 104432 # number of times the floating registers were written -system.cpu0.num_mem_refs 12599733 # number of memory refs -system.cpu0.num_load_insts 7506744 # Number of load instructions -system.cpu0.num_store_insts 5092989 # Number of store instructions -system.cpu0.num_idle_cycles 3699864315.998118 # Number of idle cycles -system.cpu0.num_busy_cycles 233618938.001881 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059392 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940608 # Percentage of idle cycles -system.cpu0.Branches 7182999 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2715471 5.69% 5.69% # Class of executed instruction -system.cpu0.op_class::IntAlu 31387897 65.80% 71.50% # Class of executed instruction -system.cpu0.op_class::IntMult 52053 0.11% 71.61% # Class of executed instruction +system.cpu0.kern.swap_context 3064 # number of times the context was actually changed +system.cpu0.committedInsts 47693300 # Number of instructions committed +system.cpu0.committedOps 47693300 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44245928 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 210005 # Number of float alu accesses +system.cpu0.num_func_calls 1191022 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5607802 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44245928 # number of integer instructions +system.cpu0.num_fp_insts 210005 # number of float instructions +system.cpu0.num_int_register_reads 60860766 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32957591 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102620 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 104398 # number of times the floating registers were written +system.cpu0.num_mem_refs 12600240 # number of memory refs +system.cpu0.num_load_insts 7507148 # Number of load instructions +system.cpu0.num_store_insts 5093092 # Number of store instructions +system.cpu0.num_idle_cycles 3699848839.998118 # Number of idle cycles +system.cpu0.num_busy_cycles 233635512.001881 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059397 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940603 # Percentage of idle cycles +system.cpu0.Branches 7183589 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2715591 5.69% 5.69% # Class of executed instruction +system.cpu0.op_class::IntAlu 31389831 65.80% 71.50% # Class of executed instruction +system.cpu0.op_class::IntMult 52060 0.11% 71.61% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 71.61% # Class of executed instruction -system.cpu0.op_class::FloatAdd 26676 0.06% 71.66% # Class of executed instruction +system.cpu0.op_class::FloatAdd 26674 0.06% 71.66% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 71.66% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 71.66% # Class of executed instruction system.cpu0.op_class::FloatMult 0 0.00% 71.66% # Class of executed instruction system.cpu0.op_class::FloatMultAcc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1883 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatMisc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::MemRead 7588274 15.91% 87.57% # Class of executed instruction -system.cpu0.op_class::MemWrite 5010180 10.50% 98.08% # Class of executed instruction -system.cpu0.op_class::FloatMemRead 92589 0.19% 98.27% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 88924 0.19% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 735804 1.54% 100.00% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1883 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::FloatMisc 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::MemRead 7588720 15.91% 87.57% # Class of executed instruction +system.cpu0.op_class::MemWrite 5010315 10.50% 98.08% # Class of executed instruction +system.cpu0.op_class::FloatMemRead 92556 0.19% 98.27% # Class of executed instruction +system.cpu0.op_class::FloatMemWrite 88892 0.19% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 735794 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47699751 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1183172 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.236482 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11369674 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1183684 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.605329 # Average number of references to valid blocks. +system.cpu0.op_class::total 47702316 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 1183155 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.237754 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11370167 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1183667 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.605883 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 121324500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.236482 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986790 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986790 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.237754 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986792 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986792 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51472726 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51472726 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 6400739 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6400739 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4669408 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4669408 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 51474763 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51474763 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 6401125 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6401125 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4669512 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4669512 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138994 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 138994 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 146309 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 146309 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11070147 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11070147 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11070147 # number of overall hits -system.cpu0.dcache.overall_hits::total 11070147 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 938380 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 938380 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 255338 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 255338 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13584 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13584 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 146310 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 146310 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11070637 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11070637 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11070637 # number of overall hits +system.cpu0.dcache.overall_hits::total 11070637 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 938392 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 938392 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 255335 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 255335 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13590 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13590 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5728 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 5728 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1193718 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1193718 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1193718 # number of overall misses -system.cpu0.dcache.overall_misses::total 1193718 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31213946000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 31213946000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12660198000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 12660198000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149666500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 149666500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 31954500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 31954500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 43874144000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 43874144000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 43874144000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 43874144000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7339119 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7339119 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4924746 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4924746 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 152578 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 152578 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 152037 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 152037 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12263865 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12263865 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12263865 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12263865 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127860 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127860 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051848 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051848 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089030 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089030 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_misses::cpu0.data 1193727 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1193727 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1193727 # number of overall misses +system.cpu0.dcache.overall_misses::total 1193727 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31214419000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 31214419000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12662507500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 12662507500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150368000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 150368000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 31952500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 31952500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 43876926500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 43876926500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 43876926500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 43876926500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7339517 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7339517 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4924847 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4924847 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 152584 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 152584 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 152038 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 152038 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12264364 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12264364 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12264364 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12264364 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127855 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127855 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051846 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051846 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089066 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089066 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037675 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037675 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097336 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097336 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097336 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097336 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 33263.652252 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 33263.652252 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 49582.114687 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 49582.114687 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11017.851885 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11017.851885 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5578.648743 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5578.648743 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36754.194877 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36754.194877 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36754.194877 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36754.194877 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097333 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097333 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097333 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097333 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 33263.730935 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 33263.730935 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 49591.742221 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 49591.742221 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11064.606328 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11064.606328 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5578.299581 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5578.299581 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36756.248707 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36756.248707 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36756.248707 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36756.248707 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 681271 # number of writebacks -system.cpu0.dcache.writebacks::total 681271 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938380 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 938380 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 255338 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 255338 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13584 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13584 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 681263 # number of writebacks +system.cpu0.dcache.writebacks::total 681263 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938392 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 938392 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 255335 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 255335 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13590 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13590 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5728 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 5728 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1193718 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1193718 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1193718 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1193718 # number of overall MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1193727 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1193727 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1193727 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1193727 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7073 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7073 # number of ReadReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10752 # number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10752 # number of WriteReq MSHR uncacheable system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17825 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17825 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30275566000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30275566000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12404860000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12404860000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136082500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136082500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 26226500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 26226500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42680426000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 42680426000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42680426000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 42680426000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1572135500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1572135500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1572135500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1572135500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127860 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127860 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051848 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051848 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089030 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089030 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30276027000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30276027000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12407172500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12407172500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136778000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136778000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 26224500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 26224500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42683199500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 42683199500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42683199500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 42683199500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1572134500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1572134500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1572134500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1572134500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127855 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127855 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051846 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051846 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089066 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089066 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037675 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037675 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097336 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097336 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097336 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097336 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32263.652252 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32263.652252 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48582.114687 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48582.114687 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10017.851885 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10017.851885 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4578.648743 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4578.648743 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35754.194877 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35754.194877 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35754.194877 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35754.194877 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222272.797964 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222272.797964 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 88198.345021 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 88198.345021 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 692001 # number of replacements +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097333 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097333 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097333 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097333 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32263.730935 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32263.730935 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48591.742221 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48591.742221 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10064.606328 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10064.606328 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4578.299581 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4578.299581 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35756.248707 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35756.248707 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35756.248707 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35756.248707 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222272.656581 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222272.656581 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 88198.288920 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 88198.288920 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 692168 # number of replacements system.cpu0.icache.tags.tagsinuse 507.922544 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47007113 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 692513 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.879033 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 44813245500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.total_refs 47009511 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 692680 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.866130 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 44813247500 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 507.922544 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992036 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.992036 # Average percentage of cache occupancy @@ -667,97 +667,97 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 2 system.cpu0.icache.tags.age_task_id_blocks_1024::2 435 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48392391 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48392391 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 47007113 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47007113 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47007113 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47007113 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47007113 # number of overall hits -system.cpu0.icache.overall_hits::total 47007113 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 692639 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 692639 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 692639 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 692639 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 692639 # number of overall misses -system.cpu0.icache.overall_misses::total 692639 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10340404000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10340404000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10340404000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10340404000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10340404000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10340404000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47699752 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47699752 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47699752 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47699752 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47699752 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47699752 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014521 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014521 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014521 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014521 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014521 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014521 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14928.994758 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14928.994758 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14928.994758 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14928.994758 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14928.994758 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14928.994758 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48395123 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48395123 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 47009511 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47009511 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47009511 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47009511 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47009511 # number of overall hits +system.cpu0.icache.overall_hits::total 47009511 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 692806 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 692806 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 692806 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 692806 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 692806 # number of overall misses +system.cpu0.icache.overall_misses::total 692806 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10342349000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10342349000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10342349000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10342349000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10342349000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10342349000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47702317 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47702317 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47702317 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47702317 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47702317 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47702317 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014524 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014524 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014524 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014524 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014524 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014524 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14928.203566 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14928.203566 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14928.203566 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14928.203566 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14928.203566 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14928.203566 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 692001 # number of writebacks -system.cpu0.icache.writebacks::total 692001 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 692639 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 692639 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 692639 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 692639 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 692639 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 692639 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9647765000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9647765000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9647765000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9647765000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9647765000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9647765000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014521 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014521 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13928.994758 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13928.994758 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13928.994758 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 692168 # number of writebacks +system.cpu0.icache.writebacks::total 692168 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 692806 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 692806 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 692806 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 692806 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 692806 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 692806 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9649543000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9649543000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9649543000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9649543000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9649543000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9649543000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014524 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014524 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014524 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13928.203566 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13928.203566 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13928.203566 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13928.203566 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13928.203566 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13928.203566 # average overall mshr miss latency system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2442522 # DTB read hits +system.cpu1.dtb.read_hits 2442461 # DTB read hits system.cpu1.dtb.read_misses 2621 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205338 # DTB read accesses -system.cpu1.dtb.write_hits 1749235 # DTB write hits +system.cpu1.dtb.write_hits 1749247 # DTB write hits system.cpu1.dtb.write_misses 236 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89740 # DTB write accesses -system.cpu1.dtb.data_hits 4191757 # DTB hits +system.cpu1.dtb.data_hits 4191708 # DTB hits system.cpu1.dtb.data_misses 2857 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295078 # DTB accesses -system.cpu1.itb.fetch_hits 1826928 # ITB hits +system.cpu1.itb.fetch_hits 1826964 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1827992 # ITB accesses +system.cpu1.itb.fetch_accesses 1828028 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -772,40 +772,40 @@ system.cpu1.itb.data_acv 0 # DT system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.numPwrStateTransitions 5609 # Number of power state transitions system.cpu1.pwrStateClkGateDist::samples 2805 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 692202308.556150 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 417084374.205506 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 692201198.395722 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 417085998.942743 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1000-5e+10 2805 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 82000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 974673500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 61500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 974672500 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::total 2805 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 25114151500 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1941627475500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 3931646339 # number of cpu cycles simulated +system.cpu1.pwrStateResidencyTicks::ON 25117814500 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1941624361500 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 3931646343 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2805 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 79700 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27196 38.42% 38.42% # number of times we switched to this ipl +system.cpu1.kern.inst.hwrei 79704 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 27198 38.42% 38.42% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1969 2.78% 41.20% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 525 0.74% 41.94% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 41097 58.06% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 70787 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26331 48.20% 48.20% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::31 41099 58.06% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 70791 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 26333 48.20% 48.20% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1969 3.60% 51.80% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 525 0.96% 52.76% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25806 47.24% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 54631 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909855366000 97.15% 97.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 731068500 0.04% 97.19% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 371926000 0.02% 97.21% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 54864779000 2.79% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1965823139500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968194 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_good::31 25808 47.24% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 54635 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909855455500 97.15% 97.15% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 731138500 0.04% 97.19% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 371933000 0.02% 97.21% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 54864614500 2.79% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1965823141500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968196 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.627929 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.771766 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.627947 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.771779 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal::wripir 433 0.59% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed @@ -813,7 +813,7 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # nu system.cpu1.kern.callpal::swpctx 2016 2.75% 3.35% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed -system.cpu1.kern.callpal::swpipl 64567 88.14% 91.50% # number of callpals executed +system.cpu1.kern.callpal::swpipl 64571 88.14% 91.50% # number of callpals executed system.cpu1.kern.callpal::rdps 2334 3.19% 94.68% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 94.68% # number of callpals executed system.cpu1.kern.callpal::wrusp 3 0.00% 94.69% # number of callpals executed @@ -822,7 +822,7 @@ system.cpu1.kern.callpal::rti 3725 5.08% 99.78% # nu system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 73259 # number of callpals executed +system.cpu1.kern.callpal::total 73263 # number of callpals executed system.cpu1.kern.mode_switch::kernel 1964 # number of protection mode switches system.cpu1.kern.mode_switch::user 367 # number of protection mode switches system.cpu1.kern.mode_switch::idle 2923 # number of protection mode switches @@ -833,236 +833,236 @@ system.cpu1.kern.mode_switch_good::kernel 0.415479 # f system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.153609 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::total 0.310620 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 18376717500 0.94% 0.94% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1492465500 0.08% 1.01% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1945081083000 98.99% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::kernel 18379231500 0.94% 0.94% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1492112000 0.08% 1.01% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1945079443000 98.99% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2017 # number of times the context was actually changed -system.cpu1.committedInsts 13268743 # Number of instructions committed -system.cpu1.committedOps 13268743 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12224543 # Number of integer alu accesses +system.cpu1.committedInsts 13268542 # Number of instructions committed +system.cpu1.committedOps 13268542 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12224320 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 175144 # Number of float alu accesses -system.cpu1.num_func_calls 423393 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1315452 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12224543 # number of integer instructions +system.cpu1.num_func_calls 423403 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1315333 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12224320 # number of integer instructions system.cpu1.num_fp_insts 175144 # number of float instructions -system.cpu1.num_int_register_reads 16795911 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8988763 # number of times the integer registers were written +system.cpu1.num_int_register_reads 16795598 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8988647 # number of times the integer registers were written system.cpu1.num_fp_register_reads 90944 # number of times the floating registers were read system.cpu1.num_fp_register_writes 92918 # number of times the floating registers were written -system.cpu1.num_mem_refs 4214824 # number of memory refs -system.cpu1.num_load_insts 2456352 # Number of load instructions -system.cpu1.num_store_insts 1758472 # Number of store instructions -system.cpu1.num_idle_cycles 3881441492.340690 # Number of idle cycles -system.cpu1.num_busy_cycles 50204846.659310 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012769 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987231 # Percentage of idle cycles -system.cpu1.Branches 1899015 # Number of branches fetched -system.cpu1.op_class::No_OpClass 719201 5.42% 5.42% # Class of executed instruction -system.cpu1.op_class::IntAlu 7861154 59.23% 64.65% # Class of executed instruction -system.cpu1.op_class::IntMult 22602 0.17% 64.82% # Class of executed instruction +system.cpu1.num_mem_refs 4214775 # number of memory refs +system.cpu1.num_load_insts 2456291 # Number of load instructions +system.cpu1.num_store_insts 1758484 # Number of store instructions +system.cpu1.num_idle_cycles 3881434187.727123 # Number of idle cycles +system.cpu1.num_busy_cycles 50212155.272877 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012771 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987229 # Percentage of idle cycles +system.cpu1.Branches 1898911 # Number of branches fetched +system.cpu1.op_class::No_OpClass 719210 5.42% 5.42% # Class of executed instruction +system.cpu1.op_class::IntAlu 7860972 59.23% 64.65% # Class of executed instruction +system.cpu1.op_class::IntMult 22603 0.17% 64.82% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 64.82% # Class of executed instruction system.cpu1.op_class::FloatAdd 13252 0.10% 64.92% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 64.92% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 64.92% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 64.92% # Class of executed instruction system.cpu1.op_class::FloatMultAcc 0 0.00% 64.92% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1759 0.01% 64.94% # Class of executed instruction -system.cpu1.op_class::FloatMisc 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::MemRead 2447876 18.44% 83.38% # Class of executed instruction -system.cpu1.op_class::MemWrite 1681278 12.67% 96.05% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1759 0.01% 64.93% # Class of executed instruction +system.cpu1.op_class::FloatMisc 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::MemRead 2447819 18.44% 83.38% # Class of executed instruction +system.cpu1.op_class::MemWrite 1681290 12.67% 96.05% # Class of executed instruction system.cpu1.op_class::FloatMemRead 81935 0.62% 96.67% # Class of executed instruction system.cpu1.op_class::FloatMemWrite 78198 0.59% 97.25% # Class of executed instruction -system.cpu1.op_class::IprAccess 364369 2.75% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 364385 2.75% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13271624 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 162095 # number of replacements -system.cpu1.dcache.tags.tagsinuse 484.320037 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4015175 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 162424 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.720331 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 72635663500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.320037 # Average occupied blocks per requestor +system.cpu1.op_class::total 13271423 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 162127 # number of replacements +system.cpu1.dcache.tags.tagsinuse 484.320008 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4015090 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 162456 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.714938 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 72636345500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.320008 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.945938 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.945938 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16996897 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16996897 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 2273870 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2273870 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1634166 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1634166 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 51918 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 51918 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52084 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 52084 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3908036 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3908036 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3908036 # number of overall hits -system.cpu1.dcache.overall_hits::total 3908036 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 118670 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 118670 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 58749 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 58749 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9148 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9148 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6116 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 6116 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 177419 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 177419 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 177419 # number of overall misses -system.cpu1.dcache.overall_misses::total 177419 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1466187000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1466187000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1296760000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1296760000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84020000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 84020000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 34172000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 34172000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2762947000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2762947000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2762947000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2762947000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2392540 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2392540 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1692915 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1692915 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 61066 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 61066 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 58200 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 58200 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4085455 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4085455 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4085455 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4085455 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049600 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049600 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034703 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.034703 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149805 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149805 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105086 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105086 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043427 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.043427 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043427 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.043427 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12355.161372 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12355.161372 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22072.886347 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22072.886347 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9184.521207 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9184.521207 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5587.311969 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5587.311969 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15573.005146 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15573.005146 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15573.005146 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15573.005146 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 16996743 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16996743 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 2273788 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2273788 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1634135 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1634135 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 51915 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 51915 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52085 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 52085 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3907923 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3907923 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3907923 # number of overall hits +system.cpu1.dcache.overall_hits::total 3907923 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 118690 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 118690 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 58791 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 58791 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9152 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9152 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6117 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 6117 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 177481 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 177481 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 177481 # number of overall misses +system.cpu1.dcache.overall_misses::total 177481 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1467443500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1467443500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1300528500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1300528500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84062000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 84062000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 34151000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 34151000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2767972000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2767972000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2767972000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2767972000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2392478 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2392478 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1692926 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1692926 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 61067 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 61067 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 58202 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 58202 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4085404 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4085404 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4085404 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4085404 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049610 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049610 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034727 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.034727 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149868 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149868 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105099 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105099 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043443 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.043443 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043443 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.043443 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12363.665852 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12363.665852 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22121.217533 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22121.217533 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.096154 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.096154 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5582.965506 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5582.965506 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15595.877869 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15595.877869 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15595.877869 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15595.877869 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 111600 # number of writebacks -system.cpu1.dcache.writebacks::total 111600 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118670 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 118670 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58749 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 58749 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9148 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9148 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6116 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 6116 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 177419 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 177419 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 177419 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 177419 # number of overall MSHR misses +system.cpu1.dcache.writebacks::writebacks 111642 # number of writebacks +system.cpu1.dcache.writebacks::total 111642 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118690 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 118690 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58791 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 58791 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9152 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9152 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6117 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 6117 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 177481 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 177481 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 177481 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 177481 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 125 # number of ReadReq MSHR uncacheable system.cpu1.dcache.ReadReq_mshr_uncacheable::total 125 # number of ReadReq MSHR uncacheable system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3371 # number of WriteReq MSHR uncacheable system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3371 # number of WriteReq MSHR uncacheable system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3496 # number of overall MSHR uncacheable misses system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3496 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1347517000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1347517000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238011000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1238011000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74872000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74872000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 28056000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 28056000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2585528000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2585528000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2585528000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2585528000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1348753500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1348753500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1241737500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1241737500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74910000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74910000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 28034000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 28034000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2590491000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2590491000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2590491000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2590491000 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 26291000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 26291000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 26291000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 26291000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049600 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049600 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034703 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034703 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.149805 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.149805 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105086 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105086 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043427 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043427 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043427 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043427 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11355.161372 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11355.161372 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21072.886347 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21072.886347 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8184.521207 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8184.521207 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4587.311969 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4587.311969 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14573.005146 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14573.005146 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14573.005146 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14573.005146 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049610 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049610 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034727 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034727 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.149868 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.149868 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105099 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105099 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043443 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043443 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043443 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043443 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11363.665852 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11363.665852 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21121.217533 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21121.217533 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8185.096154 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8185.096154 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4582.965506 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4582.965506 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14595.877869 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14595.877869 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14595.877869 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14595.877869 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 210328 # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210328 # average ReadReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 7520.308924 # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 7520.308924 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 326538 # number of replacements -system.cpu1.icache.tags.tagsinuse 445.783445 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12944535 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 327049 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.579803 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1960887554500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.783445 # Average occupied blocks per requestor +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 326560 # number of replacements +system.cpu1.icache.tags.tagsinuse 445.783409 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12944312 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 327071 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.576459 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1960887860500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.783409 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870671 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.870671 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -1070,77 +1070,77 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::2 75 system.cpu1.icache.tags.age_task_id_blocks_1024::3 434 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13598713 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13598713 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 12944535 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12944535 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12944535 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12944535 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12944535 # number of overall hits -system.cpu1.icache.overall_hits::total 12944535 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 327089 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 327089 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 327089 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 327089 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 327089 # number of overall misses -system.cpu1.icache.overall_misses::total 327089 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4450039000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4450039000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4450039000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4450039000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4450039000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4450039000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13271624 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13271624 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13271624 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13271624 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13271624 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13271624 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024646 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024646 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024646 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024646 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024646 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024646 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13604.979073 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13604.979073 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13604.979073 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13604.979073 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13604.979073 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13604.979073 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13598534 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13598534 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 12944312 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12944312 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12944312 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12944312 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12944312 # number of overall hits +system.cpu1.icache.overall_hits::total 12944312 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 327111 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 327111 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 327111 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 327111 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 327111 # number of overall misses +system.cpu1.icache.overall_misses::total 327111 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4448984500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4448984500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4448984500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4448984500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4448984500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4448984500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13271423 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13271423 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13271423 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13271423 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13271423 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13271423 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024648 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024648 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024648 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024648 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024648 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024648 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13600.840388 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13600.840388 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13600.840388 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13600.840388 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13600.840388 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13600.840388 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 326538 # number of writebacks -system.cpu1.icache.writebacks::total 326538 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 327089 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 327089 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 327089 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 327089 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 327089 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 327089 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4122950000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4122950000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4122950000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4122950000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4122950000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4122950000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024646 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024646 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024646 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12604.979073 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12604.979073 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12604.979073 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 326560 # number of writebacks +system.cpu1.icache.writebacks::total 326560 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 327111 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 327111 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 327111 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 327111 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 327111 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 327111 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4121873500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4121873500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4121873500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4121873500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4121873500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4121873500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024648 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024648 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024648 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024648 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024648 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024648 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12600.840388 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12600.840388 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12600.840388 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12600.840388 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12600.840388 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12600.840388 # average overall mshr miss latency system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1153,7 +1153,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7376 # Transaction distribution system.iobus.trans_dist::ReadResp 7376 # Transaction distribution system.iobus.trans_dist::WriteReq 55675 # Transaction distribution @@ -1186,7 +1186,7 @@ system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 system.iobus.pkt_size::total 2744042 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 15108500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 758000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 758500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1202,28 +1202,28 @@ system.iobus.reqLayer25.occupancy 6051000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216235265 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216236013 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 28519000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41956000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41698 # number of replacements -system.iocache.tags.tagsinuse 0.568421 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.568425 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1760410342000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.568421 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035526 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035526 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1760410358000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.568425 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035527 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035527 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375570 # Number of tag accesses system.iocache.tags.data_accesses 375570 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses system.iocache.ReadReq_misses::total 178 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1234,12 +1234,12 @@ system.iocache.overall_misses::tsunami.ide 41730 # system.iocache.overall_misses::total 41730 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 22412883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 22412883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4956087382 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4956087382 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4978500265 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4978500265 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4978500265 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4978500265 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4955951130 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4955951130 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4978364013 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4978364013 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4978364013 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4978364013 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1258,12 +1258,12 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125915.073034 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 125915.073034 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119274.340152 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 119274.340152 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 119302.666307 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119302.666307 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 119302.666307 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119302.666307 # average overall miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119271.061080 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 119271.061080 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 119299.401222 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119299.401222 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 119299.401222 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119299.401222 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 1665 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked @@ -1282,12 +1282,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41730 system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13512883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 13512883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2876027417 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2876027417 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2889540300 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2889540300 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2889540300 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2889540300 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2875898127 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2875898127 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2889411010 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2889411010 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2889411010 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2889411010 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1298,29 +1298,29 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75915.073034 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 75915.073034 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69215.138068 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69215.138068 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69243.716751 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 69243.716751 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69243.716751 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 69243.716751 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 342937 # number of replacements -system.l2c.tags.tagsinuse 65389.954388 # Cycle average of tags in use -system.l2c.tags.total_refs 3989146 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 408458 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.766355 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7750506000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 285.827023 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4791.190703 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 59306.187710 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 166.825599 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 839.923352 # Average occupied blocks per requestor +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69212.026545 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69212.026545 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69240.618500 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 69240.618500 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69240.618500 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 69240.618500 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 342924 # number of replacements +system.l2c.tags.tagsinuse 65389.954347 # Cycle average of tags in use +system.l2c.tags.total_refs 3989934 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 408445 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.768596 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 7750508000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 285.827021 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4794.067634 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 59305.224879 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 165.844219 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 838.990595 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.004361 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073108 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.904941 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002546 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.012816 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073152 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.904926 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002531 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.012802 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.997772 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65521 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id @@ -1329,163 +1329,163 @@ system.l2c.tags.age_task_id_blocks_1024::2 1597 # system.l2c.tags.age_task_id_blocks_1024::3 6182 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 57022 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.999771 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 35591920 # Number of tag accesses -system.l2c.tags.data_accesses 35591920 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 792871 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 792871 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 746791 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 746791 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 3150 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2355 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 5505 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 947 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 959 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 1906 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 128503 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 43274 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 171777 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 680173 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 326101 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1006274 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 663284 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 108416 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 771700 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 680173 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 791787 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 326101 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 151690 # number of demand (read+write) hits -system.l2c.demand_hits::total 1949751 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 680173 # number of overall hits -system.l2c.overall_hits::cpu0.data 791787 # number of overall hits -system.l2c.overall_hits::cpu1.inst 326101 # number of overall hits -system.l2c.overall_hits::cpu1.data 151690 # number of overall hits -system.l2c.overall_hits::total 1949751 # number of overall hits +system.l2c.tags.tag_accesses 35598107 # Number of tag accesses +system.l2c.tags.data_accesses 35598107 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 792905 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 792905 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 747283 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 747283 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 3151 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 2387 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 5538 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 946 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 957 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 1903 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 128511 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 43286 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 171797 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 680335 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 326126 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1006461 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 663262 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 108452 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 771714 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 680335 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 791773 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 326126 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 151738 # number of demand (read+write) hits +system.l2c.demand_hits::total 1949972 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 680335 # number of overall hits +system.l2c.overall_hits::cpu0.data 791773 # number of overall hits +system.l2c.overall_hits::cpu1.inst 326126 # number of overall hits +system.l2c.overall_hits::cpu1.data 151738 # number of overall hits +system.l2c.overall_hits::total 1949972 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 5 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 1 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 6 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 116830 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 116816 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 6419 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 123249 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 12445 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 987 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 13432 # number of ReadCleanReq misses +system.l2c.ReadExReq_misses::total 123235 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 12450 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 984 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 13434 # number of ReadCleanReq misses system.l2c.ReadSharedReq_misses::cpu0.data 271517 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 340 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 271857 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 12445 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 388347 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 987 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6759 # number of demand (read+write) misses -system.l2c.demand_misses::total 408538 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 12445 # number of overall misses -system.l2c.overall_misses::cpu0.data 388347 # number of overall misses -system.l2c.overall_misses::cpu1.inst 987 # number of overall misses -system.l2c.overall_misses::cpu1.data 6759 # number of overall misses -system.l2c.overall_misses::total 408538 # number of overall misses +system.l2c.ReadSharedReq_misses::cpu1.data 339 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 271856 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 12450 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 388333 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 984 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 6758 # number of demand (read+write) misses +system.l2c.demand_misses::total 408525 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 12450 # number of overall misses +system.l2c.overall_misses::cpu0.data 388333 # number of overall misses +system.l2c.overall_misses::cpu1.inst 984 # number of overall misses +system.l2c.overall_misses::cpu1.data 6758 # number of overall misses +system.l2c.overall_misses::total 408525 # number of overall misses system.l2c.UpgradeReq_miss_latency::cpu0.data 300000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 28500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 328500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 10622495500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 657559500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 11280055000 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1281839000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 101239000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1383078000 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 21946509000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 42090000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 21988599000 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1281839000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 32569004500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 101239000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 699649500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 34651732000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1281839000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 32569004500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 101239000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 699649500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 34651732000 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 792871 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 792871 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 746791 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 746791 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3155 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2356 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5511 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 947 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 959 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1906 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 245333 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 49693 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 295026 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 692618 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 327088 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1019706 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 934801 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 108756 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1043557 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 692618 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1180134 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 327088 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 158449 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2358289 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 692618 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1180134 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 327088 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 158449 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2358289 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.001585 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.000424 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.001089 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.476210 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.129173 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.417756 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.017968 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.003018 # miss rate for ReadCleanReq accesses +system.l2c.ReadExReq_miss_latency::cpu0.data 10623244500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 659466000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 11282710500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1281529500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 100368000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1381897500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 21945590000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 41766500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 21987356500 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1281529500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 32568834500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 100368000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 701232500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 34651964500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1281529500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 32568834500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 100368000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 701232500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 34651964500 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 792905 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 792905 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 747283 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 747283 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3156 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 2388 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5544 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 946 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 957 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1903 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 245327 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 49705 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295032 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 692785 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 327110 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1019895 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 934779 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 108791 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1043570 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 692785 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1180106 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 327110 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 158496 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2358497 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 692785 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1180106 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 327110 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 158496 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2358497 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.001584 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.000419 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.001082 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.476164 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.129142 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.417700 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.017971 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.003008 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::total 0.013172 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.290454 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.003126 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.260510 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.017968 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.329070 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.003018 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.042657 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.173235 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.017968 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.329070 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.003018 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.042657 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.173235 # miss rate for overall accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.290461 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.003116 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.260506 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.017971 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.329066 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.003008 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.042638 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.173214 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.017971 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.329066 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.003008 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.042638 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.173214 # miss rate for overall accesses system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 60000 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 28500 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 54750 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 90922.669691 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102439.554448 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 91522.486998 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 103000.321414 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 102572.441743 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 102968.880286 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 80829.226163 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 123794.117647 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 80882.960527 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 103000.321414 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 83865.729618 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 102572.441743 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 103513.759432 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 84818.871194 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 103000.321414 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 83865.729618 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 102572.441743 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 103513.759432 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 84818.871194 # average overall miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 90939.978256 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102736.563328 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 91554.432588 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 102934.096386 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 102000 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 102865.676641 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 80825.841476 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 123205.014749 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 80878.687614 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 102934.096386 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 83868.315338 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 102000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 103763.317550 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 84822.139404 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 102934.096386 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 83868.315338 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 102000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 103763.317550 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 84822.139404 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 79969 # number of writebacks -system.l2c.writebacks::total 79969 # number of writebacks +system.l2c.writebacks::writebacks 79955 # number of writebacks +system.l2c.writebacks::total 79955 # number of writebacks system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits @@ -1497,25 +1497,25 @@ system.l2c.CleanEvict_mshr_misses::total 10 # nu system.l2c.UpgradeReq_mshr_misses::cpu0.data 5 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1.data 1 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 116830 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 116816 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 6419 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 123249 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 12445 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 976 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 13421 # number of ReadCleanReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 123235 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 12450 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 973 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 13423 # number of ReadCleanReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.data 271517 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 340 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 271857 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 12445 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 388347 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 976 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 6759 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 408527 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 12445 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 388347 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 976 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 6759 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 408527 # number of overall MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 339 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 271856 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 12450 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 388333 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 973 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 6758 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 408514 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 12450 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 388333 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 973 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 6758 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 408514 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7073 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.data 125 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::total 7198 # number of ReadReq MSHR uncacheable @@ -1528,25 +1528,25 @@ system.l2c.overall_mshr_uncacheable_misses::total 21321 system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 250000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 18500 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 268500 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 9454195500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 593369500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 10047565000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1157389000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 90609000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 1247998000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19231339000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 38690000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 19270029000 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1157389000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 28685534500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 90609000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 632059500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 30565592000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1157389000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 28685534500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 90609000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 632059500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 30565592000 # number of overall MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 9455084500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 595276000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 10050360500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1157029500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 89768000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1246797500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19230420000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 38376500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 19268796500 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1157029500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 28685504500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 89768000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 633652500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 30565954500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1157029500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 28685504500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 89768000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 633652500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 30565954500 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1483681000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 24728000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 1508409000 # number of ReadReq MSHR uncacheable cycles @@ -1555,173 +1555,175 @@ system.l2c.overall_mshr_uncacheable_latency::cpu1.data 24728000 system.l2c.overall_mshr_uncacheable_latency::total 1508409000 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.001585 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.000424 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.001089 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.476210 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.129173 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.417756 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.017968 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002984 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013162 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.290454 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.003126 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260510 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017968 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.329070 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002984 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.042657 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.173230 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017968 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.329070 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002984 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.042657 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173230 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.001584 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.000419 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.001082 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.476164 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.129142 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.417700 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.017971 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002975 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013161 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.290461 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.003116 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260506 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017971 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.329066 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002975 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.042638 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173209 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017971 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.329066 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002975 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.042638 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173209 # mshr miss rate for overall accesses system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 50000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44750 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80922.669691 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92439.554448 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 81522.486998 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 92988.450935 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70829.226163 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113794.117647 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 70882.960527 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73865.729618 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93513.759432 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 74819.025425 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73865.729618 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93513.759432 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 74819.025425 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80939.978256 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92736.563328 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 81554.432588 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 92934.096386 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92258.992806 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 92885.159800 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70825.841476 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113205.014749 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 70878.687614 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 92934.096386 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73868.315338 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92258.992806 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93763.317550 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 74822.293728 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 92934.096386 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73868.315338 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92258.992806 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93763.317550 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 74822.293728 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209766.859890 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197824 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.460961 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83235.960729 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 7073.226545 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total 70747.572816 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 856503 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 407142 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 413 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_requests 856478 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 407046 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 512 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7198 # Transaction distribution -system.membus.trans_dist::ReadResp 292654 # Transaction distribution +system.membus.trans_dist::ReadResp 292655 # Transaction distribution system.membus.trans_dist::WriteReq 14123 # Transaction distribution system.membus.trans_dist::WriteResp 14123 # Transaction distribution -system.membus.trans_dist::WritebackDirty 121489 # Transaction distribution -system.membus.trans_dist::CleanEvict 262335 # Transaction distribution -system.membus.trans_dist::UpgradeReq 11693 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 9938 # Transaction distribution +system.membus.trans_dist::WritebackDirty 121475 # Transaction distribution +system.membus.trans_dist::CleanEvict 262336 # Transaction distribution +system.membus.trans_dist::UpgradeReq 11690 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 9942 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 123969 # Transaction distribution -system.membus.trans_dist::ReadExResp 123101 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285456 # Transaction distribution +system.membus.trans_dist::ReadExReq 123955 # Transaction distribution +system.membus.trans_dist::ReadExResp 123087 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285457 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 148 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42642 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1181120 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1223762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1181082 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1223724 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83443 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83443 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1307205 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1307167 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82394 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31237440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31319834 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31235712 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31318106 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33978074 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 22774 # Total snoops (count) +system.membus.pkt_size::total 33976346 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 22923 # Total snoops (count) system.membus.snoopTraffic 27264 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 493929 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001371 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.036997 # Request fanout histogram +system.membus.snoop_fanout::samples 493917 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001373 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.037025 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 493252 99.86% 99.86% # Request fanout histogram -system.membus.snoop_fanout::1 677 0.14% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 493239 99.86% 99.86% # Request fanout histogram +system.membus.snoop_fanout::1 678 0.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 493929 # Request fanout histogram -system.membus.reqLayer0.occupancy 40493000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 493917 # Request fanout histogram +system.membus.reqLayer0.occupancy 40493500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1323047597 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1322925099 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2182313750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2182236750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 915117 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1074598 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 4789247 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2394847 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 361788 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 989 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 928 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 4789722 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2388089 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 374620 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 991 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 930 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 61 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 7198 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2106871 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2107102 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14123 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 14123 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 872840 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1018539 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 815364 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 17050 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11844 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28894 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297037 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297037 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1019728 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1079947 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 872860 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1018728 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 815346 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 17080 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11845 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28925 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297046 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297046 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1019917 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1079990 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 246 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2077258 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3616236 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 980715 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 523549 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7197758 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 88615616 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119196292 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41832064 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17309590 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 266953562 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 403246 # Total snoops (count) -system.toL2Bus.snoopTraffic 7576960 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2790110 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.141029 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.348296 # Request fanout histogram +system.toL2Bus.trans_dist::InvalidateResp 4 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2077759 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3616208 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 980781 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 523727 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7198475 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 88636992 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119193988 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41834880 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17315286 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 266981146 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 403271 # Total snoops (count) +system.toL2Bus.snoopTraffic 7578112 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 2790369 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.143087 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.350419 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2396861 85.91% 85.91% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 393013 14.09% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 235 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2391353 85.70% 85.70% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 398767 14.29% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 248 0.01% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2790110 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4223757496 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2790369 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4224217497 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 302383 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 304383 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1039141633 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1039374668 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1817975093 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1817986111 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 491872018 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 491891046 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 276251327 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 276353266 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1753,28 +1755,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index c56df0bbe..0bead1a4b 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.926421 # Number of seconds simulated -sim_ticks 1926421414000 # Number of ticks simulated -final_tick 1926421414000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.926422 # Number of seconds simulated +sim_ticks 1926421638000 # Number of ticks simulated +final_tick 1926421638000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 834051 # Simulator instruction rate (inst/s) -host_op_rate 834051 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28592100047 # Simulator tick rate (ticks/s) -host_mem_usage 333408 # Number of bytes of host memory used -host_seconds 67.38 # Real time elapsed on the host +host_inst_rate 1739419 # Simulator instruction rate (inst/s) +host_op_rate 1739418 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59628989604 # Simulator tick rate (ticks/s) +host_mem_usage 334072 # Number of bytes of host memory used +host_seconds 32.31 # Real time elapsed on the host sim_insts 56195014 # Number of instructions simulated sim_ops 56195014 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 844672 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24856896 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory @@ -29,18 +29,18 @@ system.physmem.num_reads::total 401602 # Nu system.physmem.num_writes::writebacks 115765 # Number of write requests responded to by this memory system.physmem.num_writes::total 115765 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 438467 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12903146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12903144 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13342111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13342109 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 438467 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 438467 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3845971 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3845971 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3845971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 3845970 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3845970 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3845970 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 438467 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12903146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12903144 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 498 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17188081 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17188079 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 401602 # Number of read requests accepted system.physmem.writeReqs 115765 # Number of write requests accepted system.physmem.readBursts 401602 # Number of DRAM read bursts, including those serviced by the write queue @@ -87,7 +87,7 @@ system.physmem.perBankWrBursts::14 7864 # Pe system.physmem.perBankWrBursts::15 7687 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 65 # Number of times write queue was full causing retry -system.physmem.totGap 1926409540500 # Total gap between requests +system.physmem.totGap 1926409764500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -150,68 +150,68 @@ system.physmem.wrQLenPdf::12 1 # Wh system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 1555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6885 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5581 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 330 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 339 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 238 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63474 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 521.529319 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 315.079750 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.298836 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14953 23.56% 23.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11433 18.01% 41.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4319 6.80% 48.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3083 4.86% 53.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3219 5.07% 58.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1509 2.38% 60.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1583 2.49% 63.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 998 1.57% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22377 35.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63474 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 63476 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 521.512887 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 315.060266 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.295929 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14957 23.56% 23.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11430 18.01% 41.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4320 6.81% 48.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3081 4.85% 53.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3222 5.08% 58.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1508 2.38% 60.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1584 2.50% 63.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 999 1.57% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22375 35.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63476 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5049 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 79.519311 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 2969.676150 # Reads before turning the bus around for writes @@ -222,29 +222,29 @@ system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% system.physmem.rdPerTurnAround::total 5049 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 5049 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 22.925332 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.952060 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.989890 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4540 89.92% 89.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 33 0.65% 90.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 164 3.25% 93.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.953728 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.991500 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4538 89.88% 89.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 34 0.67% 90.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 165 3.27% 93.82% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-47 7 0.14% 93.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-55 1 0.02% 93.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::56-63 14 0.28% 94.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 7 0.14% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 4 0.08% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 36 0.71% 95.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 8 0.16% 94.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 5 0.10% 94.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 34 0.67% 95.19% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::88-95 2 0.04% 95.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 139 2.75% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 18 0.36% 98.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 141 2.79% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 16 0.32% 98.34% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-119 13 0.26% 98.59% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::120-127 3 0.06% 98.65% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-135 6 0.12% 98.77% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::136-143 6 0.12% 98.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::152-159 3 0.06% 98.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-167 2 0.04% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 13 0.26% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.08% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 12 0.24% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 12 0.24% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 4 0.08% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 13 0.26% 99.56% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::192-199 10 0.20% 99.76% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::200-207 1 0.02% 99.78% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::208-215 1 0.02% 99.80% # Writes before turning the bus around for reads @@ -252,12 +252,12 @@ system.physmem.wrPerTurnAround::216-223 6 0.12% 99.92% # Wr system.physmem.wrPerTurnAround::224-231 2 0.04% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5049 # Writes before turning the bus around for reads -system.physmem.totQLat 6110965000 # Total ticks spent queuing -system.physmem.totMemAccLat 13638958750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 6110922250 # Total ticks spent queuing +system.physmem.totMemAccLat 13638916000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2007465000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15220.60 # Average queueing delay per DRAM burst +system.physmem.avgQLat 15220.50 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33970.60 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 33970.50 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.34 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.34 # Average system read bandwidth in MiByte/s @@ -268,52 +268,52 @@ system.physmem.busUtilRead 0.10 # Da system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing -system.physmem.readRowHits 360227 # Number of row buffer hits during reads +system.physmem.readRowHits 360225 # Number of row buffer hits during reads system.physmem.writeRowHits 93542 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.72 # Row buffer hit rate for reads system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes -system.physmem.avgGap 3723487.47 # Average gap between requests +system.physmem.avgGap 3723487.90 # Average gap between requests system.physmem.pageHitRate 87.73 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 220840200 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 117379350 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 1432076940 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 299763720 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 5519467200.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5038358250 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 366301440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 13030830420 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 6357713760 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 449603447400 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 481990669050 # Total energy per rank (pJ) -system.physmem_0.averagePower 250.200016 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1914256960750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 613825000 # Time in different power states +system.physmem_0.actBackEnergy 5038088640 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 365587680 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 13029981120 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 6359365440 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 449603503800 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 481990544460 # Total energy per rank (pJ) +system.physmem_0.averagePower 250.199922 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1914259413500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 611958500 # Time in different power states system.physmem_0.memoryStateTime::REF 2347892000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1869275563500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 16556600250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9050884750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 28576648500 # Time in different power states -system.physmem_1.actEnergy 232364160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 123504480 # Energy for precharge commands per rank (pJ) +system.physmem_0.memoryStateTime::SREF 1869275787500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 16560859500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9050522500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 28574618000 # Time in different power states +system.physmem_1.actEnergy 232378440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 123512070 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1434583080 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 304451280 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 5706932400.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5157840510 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 361297920 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 13647845730 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 6595007040 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 449082638955 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 482651277075 # Total energy per rank (pJ) -system.physmem_1.averagePower 250.542936 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1914153639500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 598128250 # Time in different power states +system.physmem_1.actBackEnergy 5156813940 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 361085280 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 13650484260 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 6593796000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 449082763260 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 482651694330 # Total energy per rank (pJ) +system.physmem_1.averagePower 250.543123 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1914156494000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 598122250 # Time in different power states system.physmem_1.memoryStateTime::REF 2427510000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1867054823500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 17174624250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9236704750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 29929623250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.physmem_1.memoryStateTime::SREF 1867055047500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 17171481750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9234080250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 29935396250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -349,16 +349,16 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.numPwrStateTransitions 12758 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 6379 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 281128919.188117 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 439406492.836173 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 281128919.971939 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 439406494.656653 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 6378 99.98% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 6379 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 133100038499 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1793321375501 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 3852842828 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 133100257499 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1793321380501 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 3852843276 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed @@ -374,11 +374,11 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.40% # nu system.cpu.kern.ipl_good::22 1934 1.30% 50.69% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73544 49.31% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149153 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1859428695000 96.52% 96.52% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1859428733000 96.52% 96.52% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 94503000 0.00% 96.53% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 772442000 0.04% 96.57% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 66125040000 3.43% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1926420680000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 772464500 0.04% 96.57% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 66125203500 3.43% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1926420904000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -411,9 +411,9 @@ system.cpu.kern.mode_switch_good::kernel 0.323061 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.391786 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 47043056000 2.44% 2.44% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5370301500 0.28% 2.72% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1874007320500 97.28% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 47043334000 2.44% 2.44% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5370278500 0.28% 2.72% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1874007289500 97.28% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.committedInsts 56195014 # Number of instructions committed system.cpu.committedOps 56195014 # Number of ops (including micro ops) committed @@ -430,8 +430,8 @@ system.cpu.num_fp_register_writes 166520 # nu system.cpu.num_mem_refs 15476659 # number of memory refs system.cpu.num_load_insts 9103400 # Number of load instructions system.cpu.num_store_insts 6373259 # Number of store instructions -system.cpu.num_idle_cycles 3586642751.000138 # Number of idle cycles -system.cpu.num_busy_cycles 266200076.999862 # Number of busy cycles +system.cpu.num_idle_cycles 3586642761.000138 # Number of idle cycles +system.cpu.num_busy_cycles 266200514.999862 # Number of busy cycles system.cpu.not_idle_fraction 0.069092 # Percentage of non-idle cycles system.cpu.idle_fraction 0.930908 # Percentage of idle cycles system.cpu.Branches 8424278 # Number of branches fetched @@ -474,12 +474,12 @@ system.cpu.op_class::FloatMemWrite 138108 0.25% 98.30% # Cl system.cpu.op_class::IprAccess 953511 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 56206855 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1390811 # number of replacements +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1390804 # number of replacements system.cpu.dcache.tags.tagsinuse 511.976541 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14051752 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1391323 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.099561 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 14051759 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1391316 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.099617 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 121311500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.976541 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999954 # Average percentage of cache occupancy @@ -489,41 +489,41 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63163628 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63163628 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7815905 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7815905 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5853570 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5853570 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183002 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183002 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 63163621 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63163621 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 7815914 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7815914 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5853567 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5853567 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183003 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183003 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199258 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199258 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13669475 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13669475 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13669475 # number of overall hits -system.cpu.dcache.overall_hits::total 13669475 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069743 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069743 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304319 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304319 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17279 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17279 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1374062 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1374062 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1374062 # number of overall misses -system.cpu.dcache.overall_misses::total 1374062 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33050586500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33050586500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13442150000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13442150000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232520000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 232520000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46492736500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46492736500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46492736500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46492736500 # number of overall miss cycles +system.cpu.dcache.demand_hits::cpu.data 13669481 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13669481 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13669481 # number of overall hits +system.cpu.dcache.overall_hits::total 13669481 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069734 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069734 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304322 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304322 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17278 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17278 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1374056 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1374056 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1374056 # number of overall misses +system.cpu.dcache.overall_misses::total 1374056 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33050329500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33050329500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13442227500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13442227500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232507000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 232507000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 46492557000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46492557000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46492557000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46492557000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 8885648 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 8885648 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6157889 # number of WriteReq accesses(hits+misses) @@ -536,96 +536,96 @@ system.cpu.dcache.demand_accesses::cpu.data 15043537 # system.cpu.dcache.demand_accesses::total 15043537 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 15043537 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15043537 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120390 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120390 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049419 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049419 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086274 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086274 # miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120389 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120389 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049420 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049420 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086269 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086269 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.091339 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.091339 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.091339 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.091339 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30895.819370 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30895.819370 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44171.247934 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44171.247934 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13456.797268 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13456.797268 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33835.981564 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33835.981564 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33835.981564 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33835.981564 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30895.839059 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30895.839059 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44171.067159 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44171.067159 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13456.823706 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13456.823706 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33835.998678 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33835.998678 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33835.998678 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33835.998678 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 835205 # number of writebacks -system.cpu.dcache.writebacks::total 835205 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069743 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069743 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304319 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304319 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17279 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17279 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1374062 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1374062 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1374062 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1374062 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 835203 # number of writebacks +system.cpu.dcache.writebacks::total 835203 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069734 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069734 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304322 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304322 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17278 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17278 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1374056 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1374056 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1374056 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1374056 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9652 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9652 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16582 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16582 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31980843500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 31980843500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13137831000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13137831000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215241000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215241000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45118674500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45118674500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45118674500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45118674500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31980595500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 31980595500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13137905500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13137905500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215229000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215229000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45118501000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45118501000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45118501000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45118501000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1533908500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1533908500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1533908500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 1533908500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120390 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120390 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049419 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049419 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086274 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086274 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120389 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120389 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049420 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049420 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086269 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086269 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091339 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.091339 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091339 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.091339 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29895.819370 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29895.819370 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43171.247934 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43171.247934 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12456.797268 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12456.797268 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32835.981564 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 32835.981564 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32835.981564 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32835.981564 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29895.839059 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29895.839059 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43171.067159 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43171.067159 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12456.823706 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12456.823706 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32835.998678 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 32835.998678 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32835.998678 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32835.998678 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221343.217893 # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221343.217893 # average ReadReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92504.432517 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92504.432517 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 928683 # number of replacements -system.cpu.icache.tags.tagsinuse 507.830404 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55277502 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 929194 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.489732 # Average number of references to valid blocks. +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 928685 # number of replacements +system.cpu.icache.tags.tagsinuse 507.830405 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55277500 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 929196 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.489602 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 44439092500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 507.830404 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 507.830405 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.991856 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.991856 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -634,27 +634,27 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 1 system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57136210 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57136210 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 55277502 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55277502 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55277502 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55277502 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55277502 # number of overall hits -system.cpu.icache.overall_hits::total 55277502 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929354 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929354 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929354 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929354 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929354 # number of overall misses -system.cpu.icache.overall_misses::total 929354 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13309679000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13309679000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13309679000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13309679000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13309679000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13309679000 # number of overall miss cycles +system.cpu.icache.tags.tag_accesses 57136212 # Number of tag accesses +system.cpu.icache.tags.data_accesses 57136212 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 55277500 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55277500 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55277500 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55277500 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55277500 # number of overall hits +system.cpu.icache.overall_hits::total 55277500 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929356 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929356 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929356 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929356 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929356 # number of overall misses +system.cpu.icache.overall_misses::total 929356 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13310087000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13310087000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13310087000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13310087000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13310087000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13310087000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 56206856 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 56206856 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 56206856 # number of demand (read+write) accesses @@ -667,54 +667,54 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.016535 system.cpu.icache.demand_miss_rate::total 0.016535 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.016535 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.016535 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14321.430800 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14321.430800 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14321.430800 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14321.430800 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14321.430800 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14321.430800 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14321.838994 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14321.838994 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14321.838994 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14321.838994 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14321.838994 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14321.838994 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 928683 # number of writebacks -system.cpu.icache.writebacks::total 928683 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929354 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929354 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929354 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929354 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929354 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929354 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12380325000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12380325000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12380325000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12380325000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12380325000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12380325000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 928685 # number of writebacks +system.cpu.icache.writebacks::total 928685 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929356 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 929356 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 929356 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 929356 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 929356 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 929356 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12380731000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12380731000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12380731000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12380731000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12380731000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12380731000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016535 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016535 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016535 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.016535 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016535 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.016535 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13321.430800 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13321.430800 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13321.430800 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13321.430800 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13321.430800 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13321.430800 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13321.838994 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13321.838994 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13321.838994 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13321.838994 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13321.838994 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13321.838994 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 336397 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65387.710851 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4236321 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 65387.710870 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4236311 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 401919 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.540236 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.540211 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 7724199000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 234.658578 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4730.574413 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 60422.477860 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 234.658565 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4730.574877 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 60422.477428 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.003581 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072183 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.921974 # Average percentage of cache occupancy @@ -725,27 +725,27 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 384 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4685 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59935 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 37511490 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 37511490 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 835205 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 835205 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 928450 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 928450 # number of WritebackClean hits +system.cpu.l2cache.tags.tag_accesses 37511410 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 37511410 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 835203 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 835203 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 928452 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 928452 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 12 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 12 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187485 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187485 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916136 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 916136 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 815048 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 815048 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 916136 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1002533 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1918669 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 916136 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1002533 # number of overall hits -system.cpu.l2cache.overall_hits::total 1918669 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187488 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187488 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916138 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 916138 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 815038 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 815038 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 916138 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1002526 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1918664 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 916138 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1002526 # number of overall hits +system.cpu.l2cache.overall_hits::total 1918664 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 116817 # number of ReadExReq misses @@ -762,64 +762,64 @@ system.cpu.l2cache.overall_misses::cpu.data 388791 # system.cpu.l2cache.overall_misses::total 401989 # number of overall misses system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 246500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 246500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10709040500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10709040500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1353538000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1353538000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21993492000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 21993492000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1353538000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 32702532500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34056070500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1353538000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 32702532500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34056070500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 835205 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 835205 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 928450 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 928450 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10708900500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10708900500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1353922000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1353922000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21993208500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 21993208500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1353922000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 32702109000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34056031000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1353922000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 32702109000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34056031000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 835203 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 835203 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 928452 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 928452 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304302 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304302 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929334 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 929334 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1087022 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1087022 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 929334 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1391324 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2320658 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 929334 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1391324 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2320658 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304305 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304305 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929336 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 929336 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1087012 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1087012 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 929336 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1391317 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2320653 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 929336 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1391317 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2320653 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.294118 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.294118 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383885 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383885 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383881 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383881 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014202 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014202 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250201 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250201 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250203 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250203 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014202 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279440 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.279441 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.173222 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014202 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279440 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.279441 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.173222 # miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49300 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49300 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91673.647671 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91673.647671 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 102556.296409 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 102556.296409 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80866.156324 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80866.156324 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 102556.296409 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84113.398973 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84718.911463 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 102556.296409 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84113.398973 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84718.911463 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91672.449215 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91672.449215 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 102585.391726 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 102585.391726 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80865.113945 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80865.113945 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 102585.391726 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84112.309699 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84718.813201 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 102585.391726 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84112.309699 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84718.813201 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -850,101 +850,102 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16582 system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16582 # number of overall MSHR uncacheable misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 196500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 196500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9540870500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9540870500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1221558000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1221558000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19273752000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19273752000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1221558000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28814622500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30036180500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1221558000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28814622500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30036180500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9540730500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9540730500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1221942000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1221942000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19273468500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19273468500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1221942000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28814199000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30036141000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1221942000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28814199000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30036141000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447252500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447252500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447252500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447252500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.294118 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.294118 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383885 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383885 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383881 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383881 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014202 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250201 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250201 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250203 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250203 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279440 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279441 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.173222 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279440 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279441 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.173222 # mshr miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 39300 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 39300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81673.647671 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81673.647671 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 92556.296409 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 92556.296409 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70866.156324 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70866.156324 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 92556.296409 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74113.398973 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74718.911463 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 92556.296409 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74113.398973 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74718.911463 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81672.449215 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81672.449215 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 92585.391726 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 92585.391726 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70865.113945 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70865.113945 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 92585.391726 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74112.309699 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74718.813201 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 92585.391726 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74112.309699 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74718.813201 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208838.744589 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208838.744589 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87278.524907 # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87278.524907 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4640189 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319660 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1516 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 4640179 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319543 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1996 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 884 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 884 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2023463 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2023455 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9652 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9652 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 909458 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 928683 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 817750 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 909456 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 928685 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 817745 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304302 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304302 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 929354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1087182 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304305 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304305 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 929356 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1087173 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 219 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787371 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4206814 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6994185 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118913088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142552484 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 261465572 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 336953 # Total snoops (count) +system.cpu.toL2Bus.trans_dist::InvalidateResp 1 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787377 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4206794 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6994171 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118913344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142551908 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 261465252 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 336955 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4763520 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2674053 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000958 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.030932 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2674049 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001078 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.032812 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2671492 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2561 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2671167 99.89% 99.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2882 0.11% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2674053 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4097099500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2674049 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4097094500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 293883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1394031000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1394034000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2098750500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2098740000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -958,7 +959,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51204 # Transaction distribution @@ -989,7 +990,7 @@ system.iobus.pkt_size_system.bridge.master::total 44580 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2706188 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5344500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5344000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 757500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1007,28 +1008,28 @@ system.iobus.reqLayer25.occupancy 6041500 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216215769 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216206774 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23512000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.340614 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.342515 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 1760392723000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.340614 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.083788 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.083788 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::tsunami.ide 1.342515 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.083907 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.083907 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1039,12 +1040,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21848883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21848883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4937126886 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4937126886 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4958975769 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4958975769 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4958975769 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4958975769 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4937049891 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4937049891 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4958898774 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4958898774 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4958898774 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4958898774 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1063,12 +1064,12 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126294.121387 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 126294.121387 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118818.032489 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118818.032489 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 118849.029814 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118849.029814 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 118849.029814 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118849.029814 # average overall miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118816.179510 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118816.179510 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 118847.184518 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118847.184518 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 118847.184518 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118847.184518 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 700 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -1087,12 +1088,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13198883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 13198883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2857073994 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2857073994 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2870272877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2870272877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2870272877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2870272877 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2857005811 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2857005811 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2870204694 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2870204694 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2870204694 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2870204694 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1103,19 +1104,19 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76294.121387 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 76294.121387 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68759.000626 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68759.000626 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68790.242708 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68790.242708 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68790.242708 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68790.242708 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68757.359718 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68757.359718 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68788.608604 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68788.608604 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68788.608604 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68788.608604 # average overall mshr miss latency system.membus.snoop_filter.tot_requests 821141 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 378246 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 407 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 378172 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 503 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution system.membus.trans_dist::ReadResp 292275 # Transaction distribution system.membus.trans_dist::WriteReq 9652 # Transaction distribution @@ -1128,6 +1129,7 @@ system.membus.trans_dist::ReadExReq 116686 # Tr system.membus.trans_dist::ReadExResp 116686 # Transaction distribution system.membus.trans_dist::ReadSharedReq 285345 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 124 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33164 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139253 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172417 # Packet count per connected master and slave (bytes) @@ -1140,32 +1142,32 @@ system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30498340 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 33156068 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 431 # Total snoops (count) +system.membus.snoops 555 # Total snoops (count) system.membus.snoopTraffic 27456 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 460301 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001416 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.037609 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001419 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.037638 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 459649 99.86% 99.86% # Request fanout histogram -system.membus.snoop_fanout::1 652 0.14% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 459648 99.86% 99.86% # Request fanout histogram +system.membus.snoop_fanout::1 653 0.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 460301 # Request fanout histogram -system.membus.reqLayer0.occupancy 30124000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 30123500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1287045337 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1287046834 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2142987750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2142988500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 887117 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1022522 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1197,28 +1199,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- |