diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 11:07:18 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 11:07:18 +0100 |
| commit | 62b6ff22ec1f90014b1d0fc778014bdb38cc09ce (patch) | |
| tree | 8dc7be3b13f98b2f6d082dc7424335d9ddfe764d /tests/quick/fs/10.linux-boot/ref/alpha | |
| parent | 71a02f624e9c406ad37a1ed7030f98a36da6e59f (diff) | |
| download | gem5-62b6ff22ec1f90014b1d0fc778014bdb38cc09ce.tar.xz | |
stats: update for snoop filter tweak
--HG--
extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha')
4 files changed, 1534 insertions, 1509 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 90f1f17e3..8d5fa3758 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.869358 # Number of seconds simulated -sim_ticks 1869357988000 # Number of ticks simulated -final_tick 1869357988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1869357999000 # Number of ticks simulated +final_tick 1869357999000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1670594 # Simulator instruction rate (inst/s) -host_op_rate 1670593 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48045239456 # Simulator tick rate (ticks/s) -host_mem_usage 332628 # Number of bytes of host memory used -host_seconds 38.91 # Real time elapsed on the host +host_inst_rate 1770526 # Simulator instruction rate (inst/s) +host_op_rate 1770526 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50919239991 # Simulator tick rate (ticks/s) +host_mem_usage 331076 # Number of bytes of host memory used +host_seconds 36.71 # Real time elapsed on the host sim_insts 64999904 # Number of instructions simulated sim_ops 64999904 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -49,7 +49,7 @@ system.physmem.bw_total::cpu0.data 35592763 # To system.physmem.bw_total::cpu1.inst 56764 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 409946 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40657621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40657620 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses @@ -83,7 +83,7 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3738722771 # number of cpu cycles simulated +system.cpu0.numCycles 3738722793 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed @@ -101,12 +101,12 @@ system.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # nu system.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1853222721000 99.14% 99.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1853222732000 99.14% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::31 15975327000 0.85% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1869357780500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1869357791500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -172,7 +172,7 @@ system.cpu0.kern.mode_switch_good::kernel 0.177764 # f system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.301957 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1868349152500 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1868349163500 99.95% 99.95% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::user 1008627000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 2744 # number of times the context was actually changed @@ -191,7 +191,7 @@ system.cpu0.num_fp_register_writes 98967 # nu system.cpu0.num_mem_refs 12536107 # number of memory refs system.cpu0.num_load_insts 7783754 # Number of load instructions system.cpu0.num_store_insts 4752353 # Number of store instructions -system.cpu0.num_idle_cycles 3689239788.666409 # Number of idle cycles +system.cpu0.num_idle_cycles 3689239810.666409 # Number of idle cycles system.cpu0.num_busy_cycles 49482982.333591 # Number of busy cycles system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles @@ -231,13 +231,13 @@ system.cpu0.op_class::MemWrite 4758292 9.62% 98.63% # Cl system.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 49485886 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1781371 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.187328 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10705763 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1781883 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 6.008118 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1781367 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.187330 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10705767 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1781879 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 6.008134 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187328 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187330 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -245,32 +245,32 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 446 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51822042 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51822042 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6068881 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6068881 # number of ReadReq hits +system.cpu0.dcache.tags.tag_accesses 51822038 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51822038 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6068885 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6068885 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 4360085 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 4360085 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127592 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 127592 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132849 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 132849 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10428966 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10428966 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10428966 # number of overall hits -system.cpu0.dcache.overall_hits::total 10428966 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1560069 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1560069 # number of ReadReq misses +system.cpu0.dcache.demand_hits::cpu0.data 10428970 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10428970 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10428970 # number of overall hits +system.cpu0.dcache.overall_hits::total 10428970 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1560065 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1560065 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 236538 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 236538 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12626 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 12626 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6921 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 6921 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1796607 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1796607 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1796607 # number of overall misses -system.cpu0.dcache.overall_misses::total 1796607 # number of overall misses +system.cpu0.dcache.demand_misses::cpu0.data 1796603 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1796603 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1796603 # number of overall misses +system.cpu0.dcache.overall_misses::total 1796603 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628950 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 7628950 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596623 # number of WriteReq accesses(hits+misses) @@ -301,8 +301,8 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 633127 # number of writebacks -system.cpu0.dcache.writebacks::total 633127 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 633126 # number of writebacks +system.cpu0.dcache.writebacks::total 633126 # number of writebacks system.cpu0.icache.tags.replacements 618292 # number of replacements system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks. @@ -383,7 +383,7 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3738296587 # number of cpu cycles simulated +system.cpu1.numCycles 3738296609 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -399,11 +399,11 @@ system.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # nu system.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1856123490500 99.30% 99.30% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::0 1856123501500 99.30% 99.30% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::31 12870743500 0.69% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1869146928500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1869146939500 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl @@ -457,7 +457,7 @@ system.cpu1.kern.mode_switch_good::idle 0.177356 # fr system.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches system.cpu1.kern.mode_ticks::kernel 5986368000 0.32% 0.32% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1862102404500 99.66% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1862102413500 99.66% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2507 # number of times the context was actually changed system.cpu1.committedInsts 15522159 # Number of instructions committed system.cpu1.committedOps 15522159 # Number of ops (including micro ops) committed @@ -474,8 +474,8 @@ system.cpu1.num_fp_register_writes 104129 # nu system.cpu1.num_mem_refs 4961786 # number of memory refs system.cpu1.num_load_insts 2849090 # Number of load instructions system.cpu1.num_store_insts 2112696 # Number of store instructions -system.cpu1.num_idle_cycles 3722773649.474793 # Number of idle cycles -system.cpu1.num_busy_cycles 15522937.525207 # Number of busy cycles +system.cpu1.num_idle_cycles 3722773671.474783 # Number of idle cycles +system.cpu1.num_busy_cycles 15522937.525217 # Number of busy cycles system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles system.cpu1.Branches 2214163 # Number of branches fetched @@ -515,12 +515,12 @@ system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Cl system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 15525875 # Class of executed instruction system.cpu1.dcache.tags.replacements 201757 # number of replacements -system.cpu1.dcache.tags.tagsinuse 497.601960 # Cycle average of tags in use +system.cpu1.dcache.tags.tagsinuse 497.601962 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 4718401 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 202065 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 23.350907 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601960 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601962 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971879 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.971879 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id @@ -590,7 +590,7 @@ system.cpu1.icache.tags.tagsinuse 453.133719 # Cy system.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 381159 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 39.733253 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1859777157500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.warmup_cycle 1859777195500 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133719 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy @@ -679,7 +679,7 @@ system.iocache.tags.tagsinuse 0.434096 # Cy system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1685787163517 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 1685787164517 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::tsunami.ide 0.434096 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy @@ -721,16 +721,16 @@ system.iocache.avg_blocked_cycles::no_targets nan system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks system.l2c.tags.replacements 999922 # number of replacements -system.l2c.tags.tagsinuse 65337.856722 # Cycle average of tags in use -system.l2c.tags.total_refs 4259784 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 65337.856710 # Cycle average of tags in use +system.l2c.tags.total_refs 4259780 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 1064972 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.999902 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 3.999899 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55997.404251 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4860.296117 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4190.275222 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 175.171528 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 114.709605 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 55997.404382 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4860.296070 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4190.275138 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 175.171519 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 114.709600 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.854453 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.074162 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.063939 # Average percentage of cache occupancy @@ -744,37 +744,37 @@ system.l2c.tags.age_task_id_blocks_1024::2 6047 # system.l2c.tags.age_task_id_blocks_1024::3 5933 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 49031 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 46377222 # Number of tag accesses -system.l2c.tags.data_accesses 46377222 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 777663 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 777663 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 721478 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 721478 # number of WritebackClean hits +system.l2c.tags.tag_accesses 46377199 # Number of tag accesses +system.l2c.tags.data_accesses 46377199 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 777662 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 777662 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 721480 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 721480 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 130 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 604 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 734 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 44 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 111475 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 111476 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 56605 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 168080 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 168081 # number of ReadExReq hits system.l2c.ReadCleanReq_hits::cpu0.inst 607070 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::cpu1.inst 379530 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::total 986600 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 626719 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 129011 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 755730 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 626716 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 129010 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 755726 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.inst 607070 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 738194 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 738192 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 379530 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits -system.l2c.demand_hits::total 1910410 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 185615 # number of demand (read+write) hits +system.l2c.demand_hits::total 1910407 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 607070 # number of overall hits -system.l2c.overall_hits::cpu0.data 738194 # number of overall hits +system.l2c.overall_hits::cpu0.data 738192 # number of overall hits system.l2c.overall_hits::cpu1.inst 379530 # number of overall hits -system.l2c.overall_hits::cpu1.data 185616 # number of overall hits -system.l2c.overall_hits::total 1910410 # number of overall hits +system.l2c.overall_hits::cpu1.data 185615 # number of overall hits +system.l2c.overall_hits::total 1910407 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 2989 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 2147 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 5136 # number of UpgradeReq misses @@ -800,57 +800,57 @@ system.l2c.overall_misses::cpu0.data 1040486 # nu system.l2c.overall_misses::cpu1.inst 1658 # number of overall misses system.l2c.overall_misses::cpu1.data 12101 # number of overall misses system.l2c.overall_misses::total 1066093 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 777663 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 777663 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 721478 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 721478 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 777662 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 777662 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 721480 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 721480 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 3119 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 2751 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 5870 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 1209 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 1123 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2332 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 225346 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 225347 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 67671 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 293017 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 293018 # number of ReadExReq accesses(hits+misses) system.l2c.ReadCleanReq_accesses::cpu0.inst 618918 # number of ReadCleanReq accesses(hits+misses) system.l2c.ReadCleanReq_accesses::cpu1.inst 381188 # number of ReadCleanReq accesses(hits+misses) system.l2c.ReadCleanReq_accesses::total 1000106 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 1553334 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 130046 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1683380 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 1553331 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 130045 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1683376 # number of ReadSharedReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 618918 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1778680 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1778678 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 381188 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 197717 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2976503 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 197716 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2976500 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 618918 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1778680 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1778678 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 381188 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 197717 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2976503 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 197716 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2976500 # number of overall (read+write) accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.958320 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.780443 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.874957 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.963606 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975067 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.969125 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.505316 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.505314 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.163526 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.426381 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.426380 # miss rate for ReadExReq accesses system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019143 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004350 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::total 0.013505 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596533 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596534 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007959 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.551064 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.551065 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.019143 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.584976 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.584977 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.004350 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.061204 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.358170 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.019143 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.584976 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.584977 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.004350 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.061204 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.358170 # miss rate for overall accesses @@ -862,6 +862,12 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.writebacks::writebacks 80923 # number of writebacks system.l2c.writebacks::total 80923 # number of writebacks +system.membus.snoop_filter.tot_requests 2182334 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1076327 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 430 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.trans_dist::ReadReq 7449 # Transaction distribution system.membus.trans_dist::ReadResp 948784 # Transaction distribution system.membus.trans_dist::WriteReq 14588 # Transaction distribution @@ -871,17 +877,17 @@ system.membus.trans_dist::CleanEvict 918012 # Tr system.membus.trans_dist::UpgradeReq 19594 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 14154 # Transaction distribution system.membus.trans_dist::UpgradeResp 8111 # Transaction distribution -system.membus.trans_dist::ReadExReq 125245 # Transaction distribution +system.membus.trans_dist::ReadExReq 125244 # Transaction distribution system.membus.trans_dist::ReadExResp 124222 # Transaction distribution system.membus.trans_dist::ReadSharedReq 941335 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3172394 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3216468 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3172393 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3216467 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3341629 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3341628 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73363264 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::total 73449426 # Cumulative packet size per connected master and slave (bytes) @@ -889,61 +895,61 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 76118162 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2204372 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 2204371 # Request fanout histogram +system.membus.snoop_fanout::mean 0.000517 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.022725 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2204372 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2203232 99.95% 99.95% # Request fanout histogram +system.membus.snoop_fanout::1 1139 0.05% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2204372 # Request fanout histogram -system.toL2Bus.snoop_filter.tot_requests 6035855 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 3018704 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 374458 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_fanout::total 2204371 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 6035847 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 3018700 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 374456 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 1611 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 1521 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2732156 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2732152 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 777663 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 777662 # Transaction distribution system.toL2Bus.trans_dist::WritebackClean 998939 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1205465 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1205462 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 19613 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 14226 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 33839 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 295242 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 295242 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1000127 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1724580 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1724576 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856170 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450139 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450127 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143023 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684385 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 9133717 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 9133705 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 79182784 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155766779 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155766459 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 48757440 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23358423 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 307065426 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1083516 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 7141244 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.105534 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.307488 # Request fanout histogram +system.toL2Bus.pkt_size::total 307065106 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1000943 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7058663 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.106768 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.309067 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 6388144 89.45% 89.45% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 752560 10.54% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 6305567 89.33% 89.33% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 752556 10.66% 99.99% # Request fanout histogram system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7141244 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 7058663 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 84bdf9ee5..1cd81f116 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu sim_ticks 1829331993500 # Number of ticks simulated final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1840131 # Simulator instruction rate (inst/s) -host_op_rate 1840130 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56067507873 # Simulator tick rate (ticks/s) -host_mem_usage 330836 # Number of bytes of host memory used -host_seconds 32.63 # Real time elapsed on the host +host_inst_rate 1838030 # Simulator instruction rate (inst/s) +host_op_rate 1838029 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56003449171 # Simulator tick rate (ticks/s) +host_mem_usage 325188 # Number of bytes of host memory used +host_seconds 32.66 # Real time elapsed on the host sim_insts 60038469 # Number of instructions simulated sim_ops 60038469 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index e58364a4b..d99331f2d 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.982593 # Number of seconds simulated -sim_ticks 1982592736000 # Number of ticks simulated -final_tick 1982592736000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.963613 # Number of seconds simulated +sim_ticks 1963612574000 # Number of ticks simulated +final_tick 1963612574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1178528 # Simulator instruction rate (inst/s) -host_op_rate 1178528 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38301918928 # Simulator tick rate (ticks/s) -host_mem_usage 332884 # Number of bytes of host memory used -host_seconds 51.76 # Real time elapsed on the host -sim_insts 61003209 # Number of instructions simulated -sim_ops 61003209 # Number of ops (including micro ops) simulated +host_inst_rate 993881 # Simulator instruction rate (inst/s) +host_op_rate 993880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32036346352 # Simulator tick rate (ticks/s) +host_mem_usage 331076 # Number of bytes of host memory used +host_seconds 61.29 # Real time elapsed on the host +sim_insts 60918165 # Number of instructions simulated +sim_ops 60918165 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 800192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24686016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 59328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 523328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 830784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24731648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 28416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 436224 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26069824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 800192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 59328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 859520 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7739392 # Number of bytes written to this memory -system.physmem.bytes_written::total 7739392 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12503 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 385719 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 927 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8177 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26028032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 830784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 28416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 859200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7709248 # Number of bytes written to this memory +system.physmem.bytes_written::total 7709248 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12981 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386432 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 444 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6816 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 407341 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120928 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120928 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 403609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12451380 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 29924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 263961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13149359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 403609 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 29924 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 433533 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3903672 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3903672 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3903672 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 403609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12451380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 29924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 263961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17053031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 407341 # Number of read requests accepted -system.physmem.writeReqs 120928 # Number of write requests accepted -system.physmem.readBursts 407341 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120928 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26061824 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue -system.physmem.bytesWritten 7737600 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26069824 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7739392 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 406688 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120457 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120457 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 423090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12594973 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 222154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13255177 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 423090 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14471 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 437561 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3926053 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3926053 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3926053 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 423090 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12594973 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 222154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17181230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 406688 # Number of read requests accepted +system.physmem.writeReqs 120457 # Number of write requests accepted +system.physmem.readBursts 406688 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120457 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26019904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8128 # Total number of bytes read from write queue +system.physmem.bytesWritten 7707200 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26028032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7709248 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 127 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25226 # Per bank write bursts -system.physmem.perBankRdBursts::1 25379 # Per bank write bursts -system.physmem.perBankRdBursts::2 25423 # Per bank write bursts -system.physmem.perBankRdBursts::3 24855 # Per bank write bursts -system.physmem.perBankRdBursts::4 25157 # Per bank write bursts -system.physmem.perBankRdBursts::5 25423 # Per bank write bursts -system.physmem.perBankRdBursts::6 25497 # Per bank write bursts -system.physmem.perBankRdBursts::7 25338 # Per bank write bursts -system.physmem.perBankRdBursts::8 25239 # Per bank write bursts -system.physmem.perBankRdBursts::9 25589 # Per bank write bursts -system.physmem.perBankRdBursts::10 25733 # Per bank write bursts -system.physmem.perBankRdBursts::11 25917 # Per bank write bursts -system.physmem.perBankRdBursts::12 25947 # Per bank write bursts -system.physmem.perBankRdBursts::13 25572 # Per bank write bursts -system.physmem.perBankRdBursts::14 25277 # Per bank write bursts -system.physmem.perBankRdBursts::15 25644 # Per bank write bursts -system.physmem.perBankWrBursts::0 7850 # Per bank write bursts -system.physmem.perBankWrBursts::1 7778 # Per bank write bursts -system.physmem.perBankWrBursts::2 7471 # Per bank write bursts -system.physmem.perBankWrBursts::3 6886 # Per bank write bursts -system.physmem.perBankWrBursts::4 7104 # Per bank write bursts -system.physmem.perBankWrBursts::5 7345 # Per bank write bursts -system.physmem.perBankWrBursts::6 7431 # Per bank write bursts -system.physmem.perBankWrBursts::7 7144 # Per bank write bursts -system.physmem.perBankWrBursts::8 7161 # Per bank write bursts -system.physmem.perBankWrBursts::9 7315 # Per bank write bursts -system.physmem.perBankWrBursts::10 7729 # Per bank write bursts -system.physmem.perBankWrBursts::11 8150 # Per bank write bursts -system.physmem.perBankWrBursts::12 8256 # Per bank write bursts -system.physmem.perBankWrBursts::13 7924 # Per bank write bursts -system.physmem.perBankWrBursts::14 7541 # Per bank write bursts -system.physmem.perBankWrBursts::15 7815 # Per bank write bursts +system.physmem.perBankRdBursts::0 25130 # Per bank write bursts +system.physmem.perBankRdBursts::1 25381 # Per bank write bursts +system.physmem.perBankRdBursts::2 25483 # Per bank write bursts +system.physmem.perBankRdBursts::3 24909 # Per bank write bursts +system.physmem.perBankRdBursts::4 25165 # Per bank write bursts +system.physmem.perBankRdBursts::5 25252 # Per bank write bursts +system.physmem.perBankRdBursts::6 25797 # Per bank write bursts +system.physmem.perBankRdBursts::7 25541 # Per bank write bursts +system.physmem.perBankRdBursts::8 25672 # Per bank write bursts +system.physmem.perBankRdBursts::9 25333 # Per bank write bursts +system.physmem.perBankRdBursts::10 25279 # Per bank write bursts +system.physmem.perBankRdBursts::11 25593 # Per bank write bursts +system.physmem.perBankRdBursts::12 25647 # Per bank write bursts +system.physmem.perBankRdBursts::13 25645 # Per bank write bursts +system.physmem.perBankRdBursts::14 25712 # Per bank write bursts +system.physmem.perBankRdBursts::15 25022 # Per bank write bursts +system.physmem.perBankWrBursts::0 7825 # Per bank write bursts +system.physmem.perBankWrBursts::1 7603 # Per bank write bursts +system.physmem.perBankWrBursts::2 7492 # Per bank write bursts +system.physmem.perBankWrBursts::3 6933 # Per bank write bursts +system.physmem.perBankWrBursts::4 7149 # Per bank write bursts +system.physmem.perBankWrBursts::5 7135 # Per bank write bursts +system.physmem.perBankWrBursts::6 7628 # Per bank write bursts +system.physmem.perBankWrBursts::7 7255 # Per bank write bursts +system.physmem.perBankWrBursts::8 7538 # Per bank write bursts +system.physmem.perBankWrBursts::9 7229 # Per bank write bursts +system.physmem.perBankWrBursts::10 7235 # Per bank write bursts +system.physmem.perBankWrBursts::11 7425 # Per bank write bursts +system.physmem.perBankWrBursts::12 7840 # Per bank write bursts +system.physmem.perBankWrBursts::13 8302 # Per bank write bursts +system.physmem.perBankWrBursts::14 8309 # Per bank write bursts +system.physmem.perBankWrBursts::15 7527 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 1982585344500 # Total gap between requests +system.physmem.numWrRetry 17 # Number of times write queue was full causing retry +system.physmem.totGap 1963565980500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 407341 # Read request sizes (log2) +system.physmem.readPktSize::6 406688 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120928 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407136 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120457 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 406481 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -158,176 +158,179 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 25 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67562 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 500.272698 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 302.933598 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 404.928891 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16219 24.01% 24.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12429 18.40% 42.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5206 7.71% 50.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3267 4.84% 54.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2499 3.70% 58.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4251 6.29% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1505 2.23% 67.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2122 3.14% 70.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20064 29.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67562 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5401 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.393816 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2870.561720 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5398 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 55 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 507.991867 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 305.024910 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.812380 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15899 23.95% 23.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12177 18.34% 42.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5415 8.16% 50.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3379 5.09% 55.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2311 3.48% 59.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2006 3.02% 62.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1513 2.28% 64.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1280 1.93% 66.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22413 33.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66393 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5392 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.397255 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2872.179140 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5389 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5401 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5401 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.384744 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.196926 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.269218 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4796 88.80% 88.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 29 0.54% 89.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 16 0.30% 89.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 48 0.89% 90.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 211 3.91% 94.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 14 0.26% 94.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 16 0.30% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 27 0.50% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 197 3.65% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 3 0.06% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 2 0.04% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 4 0.07% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 6 0.11% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 3 0.06% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 3 0.06% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 4 0.07% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 5 0.09% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.04% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 9 0.17% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 3 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5401 # Writes before turning the bus around for reads -system.physmem.totQLat 2785960750 # Total ticks spent queuing -system.physmem.totMemAccLat 10421260750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2036080000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6841.48 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5392 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5392 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.334013 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.995867 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.838616 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4788 88.80% 88.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 33 0.61% 89.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 252 4.67% 94.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 18 0.33% 94.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 6 0.11% 94.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 13 0.24% 94.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 10 0.19% 94.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 1 0.02% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 18 0.33% 95.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 18 0.33% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 190 3.52% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 3 0.06% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 1 0.02% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 7 0.13% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 1 0.02% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 1 0.02% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.04% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 1 0.02% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 6 0.11% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 2 0.04% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 2 0.04% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 3 0.06% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 13 0.24% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5392 # Writes before turning the bus around for reads +system.physmem.totQLat 2148968000 # Total ticks spent queuing +system.physmem.totMemAccLat 9771986750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2032805000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5285.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25591.48 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.15 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.90 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.15 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.90 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 24035.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.25 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing -system.physmem.readRowHits 363789 # Number of row buffer hits during reads -system.physmem.writeRowHits 96765 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.02 # Row buffer hit rate for writes -system.physmem.avgGap 3752984.45 # Average gap between requests -system.physmem.pageHitRate 87.20 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 243704160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132973500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1577924400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 382378320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 129493107120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 72905362650 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1125601770750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1330337220900 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.009839 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1872255893500 # Time in different power states -system.physmem_0.memoryStateTime::REF 66203020000 # Time in different power states +system.physmem.avgWrQLen 24.84 # Average write queue length when enqueuing +system.physmem.readRowHits 364299 # Number of row buffer hits during reads +system.physmem.writeRowHits 96294 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.94 # Row buffer hit rate for writes +system.physmem.avgGap 3724906.77 # Average gap between requests +system.physmem.pageHitRate 87.40 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 248179680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135415500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1580732400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 382449600 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 128253237840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 66024340605 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1120248020250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1316872375875 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.639531 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1863393486000 # Time in different power states +system.physmem_0.memoryStateTime::REF 65569140000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 44130839000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34644235250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 267064560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 145719750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1598360400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 401053680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 129493107120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 73884851505 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1124742561750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1330532718765 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.108451 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1870830292750 # Time in different power states -system.physmem_1.memoryStateTime::REF 66203020000 # Time in different power states +system.physmem_1.actEnergy 253751400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 138455625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1590443400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 397904400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 128253237840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 66573650745 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1119766169250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1316973612660 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.691088 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1862592163500 # Time in different power states +system.physmem_1.memoryStateTime::REF 65569140000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 45556426000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 35445557750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7416468 # DTB read hits -system.cpu0.dtb.read_misses 7442 # DTB read misses +system.cpu0.dtb.read_hits 7494168 # DTB read hits +system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 490672 # DTB read accesses -system.cpu0.dtb.write_hits 5004426 # DTB write hits -system.cpu0.dtb.write_misses 812 # DTB write misses +system.cpu0.dtb.read_accesses 490673 # DTB read accesses +system.cpu0.dtb.write_hits 5065702 # DTB write hits +system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations -system.cpu0.dtb.write_accesses 187451 # DTB write accesses -system.cpu0.dtb.data_hits 12420894 # DTB hits -system.cpu0.dtb.data_misses 8254 # DTB misses +system.cpu0.dtb.write_accesses 187452 # DTB write accesses +system.cpu0.dtb.data_hits 12559870 # DTB hits +system.cpu0.dtb.data_misses 8256 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations -system.cpu0.dtb.data_accesses 678123 # DTB accesses -system.cpu0.itb.fetch_hits 3482357 # ITB hits +system.cpu0.dtb.data_accesses 678125 # DTB accesses +system.cpu0.itb.fetch_hits 3501177 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3486228 # ITB accesses +system.cpu0.itb.fetch_accesses 3505048 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -340,36 +343,36 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3964851876 # number of cpu cycles simulated +system.cpu0.numCycles 3925790590 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6803 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 162795 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 55926 40.12% 40.12% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 133 0.10% 40.21% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1977 1.42% 41.63% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 435 0.31% 41.94% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 80935 58.06% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 139406 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 55417 49.07% 49.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 133 0.12% 49.18% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1977 1.75% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 435 0.39% 51.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 54983 48.68% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 112945 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1904797058500 96.08% 96.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 94101500 0.00% 96.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 790644500 0.04% 96.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 326474000 0.02% 96.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 76417629500 3.85% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1982425908000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990899 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6796 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 164911 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56822 40.19% 40.19% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1974 1.40% 41.68% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 422 0.30% 41.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82045 58.03% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141394 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56288 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1974 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 422 0.37% 51.29% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55866 48.71% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114681 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1901241129000 96.86% 96.86% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 93739000 0.00% 96.86% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 789776000 0.04% 96.90% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 316619500 0.02% 96.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 60454001500 3.08% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1962895265000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990602 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.679348 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810188 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.680919 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811074 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -401,352 +404,352 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 524 0.36% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3024 2.05% 2.41% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 132536 89.80% 92.24% # number of callpals executed -system.cpu0.kern.callpal::rdps 6593 4.47% 96.71% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.72% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.72% # number of callpals executed -system.cpu0.kern.callpal::rti 4325 2.93% 99.65% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::wripir 504 0.34% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3063 2.05% 2.39% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134533 89.85% 92.28% # number of callpals executed +system.cpu0.kern.callpal::rdps 6700 4.47% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed +system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 147596 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6863 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches +system.cpu0.kern.callpal::total 149727 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6886 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1283 -system.cpu0.kern.mode_good::user 1283 +system.cpu0.kern.mode_good::kernel 1282 +system.cpu0.kern.mode_good::user 1282 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186944 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186175 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.315001 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1977682468000 99.80% 99.80% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3900182500 0.20% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.313908 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1959142459500 99.82% 99.82% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3540793500 0.18% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3025 # number of times the context was actually changed -system.cpu0.committedInsts 47316464 # Number of instructions committed -system.cpu0.committedOps 47316464 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 43886764 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 206939 # Number of float alu accesses -system.cpu0.num_func_calls 1185664 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5565449 # number of instructions that are conditional controls -system.cpu0.num_int_insts 43886764 # number of integer instructions -system.cpu0.num_fp_insts 206939 # number of float instructions -system.cpu0.num_int_register_reads 60334858 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32718698 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 100516 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 102286 # number of times the floating registers were written -system.cpu0.num_mem_refs 12460790 # number of memory refs -system.cpu0.num_load_insts 7443408 # Number of load instructions -system.cpu0.num_store_insts 5017382 # Number of store instructions -system.cpu0.num_idle_cycles 3699967048.966084 # Number of idle cycles -system.cpu0.num_busy_cycles 264884827.033916 # Number of busy cycles -system.cpu0.not_idle_fraction 0.066808 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.933192 # Percentage of idle cycles -system.cpu0.Branches 7133745 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2703031 5.71% 5.71% # Class of executed instruction -system.cpu0.op_class::IntAlu 31175440 65.88% 71.59% # Class of executed instruction -system.cpu0.op_class::IntMult 51698 0.11% 71.70% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::FloatAdd 25566 0.05% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1656 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::MemRead 7616501 16.09% 87.85% # Class of executed instruction -system.cpu0.op_class::MemWrite 5023484 10.61% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 727686 1.54% 100.00% # Class of executed instruction +system.cpu0.kern.swap_context 3064 # number of times the context was actually changed +system.cpu0.committedInsts 47755591 # Number of instructions committed +system.cpu0.committedOps 47755591 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44289668 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 210363 # Number of float alu accesses +system.cpu0.num_func_calls 1202061 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5613734 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44289668 # number of integer instructions +system.cpu0.num_fp_insts 210363 # number of float instructions +system.cpu0.num_int_register_reads 60881629 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33006420 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102169 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 104020 # number of times the floating registers were written +system.cpu0.num_mem_refs 12600044 # number of memory refs +system.cpu0.num_load_insts 7521304 # Number of load instructions +system.cpu0.num_store_insts 5078740 # Number of store instructions +system.cpu0.num_idle_cycles 3699854946.150013 # Number of idle cycles +system.cpu0.num_busy_cycles 225935643.849987 # Number of busy cycles +system.cpu0.not_idle_fraction 0.057552 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.942448 # Percentage of idle cycles +system.cpu0.Branches 7206590 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2726655 5.71% 5.71% # Class of executed instruction +system.cpu0.op_class::IntAlu 31439878 65.82% 71.53% # Class of executed instruction +system.cpu0.op_class::IntMult 52896 0.11% 71.64% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.64% # Class of executed instruction +system.cpu0.op_class::FloatAdd 25705 0.05% 71.70% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1656 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::MemRead 7696642 16.11% 87.81% # Class of executed instruction +system.cpu0.op_class::MemWrite 5084839 10.65% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 735920 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47325062 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1172723 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.333527 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11236927 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1173142 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.578488 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 144706500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.333527 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986980 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986980 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 371 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.818359 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 50908342 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 50908342 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6342787 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6342787 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4601077 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4601077 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138129 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 138129 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145434 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 145434 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10943864 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10943864 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10943864 # number of overall hits -system.cpu0.dcache.overall_hits::total 10943864 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 934179 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 934179 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 249076 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 249076 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13578 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13578 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5739 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5739 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1183255 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1183255 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1183255 # number of overall misses -system.cpu0.dcache.overall_misses::total 1183255 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42885164500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 42885164500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 16793601000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 16793601000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 151515500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 151515500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 94785500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 94785500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 59678765500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 59678765500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 59678765500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 59678765500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7276966 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7276966 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4850153 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4850153 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151707 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 151707 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151173 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 151173 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12127119 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12127119 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12127119 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12127119 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128375 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.128375 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051354 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051354 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089501 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089501 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037963 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037963 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097571 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097571 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097571 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097571 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45906.795700 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 45906.795700 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67423.601632 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 67423.601632 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11158.896745 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11158.896745 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16516.030667 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16516.030667 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50436.098305 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50436.098305 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50436.098305 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50436.098305 # average overall miss latency +system.cpu0.op_class::total 47764191 # Class of executed instruction +system.cpu0.dcache.tags.replacements 1179864 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.229406 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11369687 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1180280 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.633042 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 114940500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.229406 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986776 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986776 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 369 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 51471495 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51471495 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6411173 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6411173 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4657733 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4657733 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 143918 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 143918 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147952 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 147952 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11068906 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11068906 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11068906 # number of overall hits +system.cpu0.dcache.overall_hits::total 11068906 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 937797 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 937797 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 251494 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 251494 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13653 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13653 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5444 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5444 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1189291 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1189291 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1189291 # number of overall misses +system.cpu0.dcache.overall_misses::total 1189291 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 29158420500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 29158420500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10960256500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10960256500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150265500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 150265500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 47401000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 47401000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 40118677000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 40118677000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 40118677000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 40118677000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7348970 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7348970 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4909227 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4909227 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157571 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157571 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153396 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153396 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12258197 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12258197 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12258197 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12258197 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127609 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127609 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051229 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051229 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086647 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086647 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035490 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035490 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097020 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097020 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097020 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097020 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31092.465107 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 31092.465107 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43580.588404 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43580.588404 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11006.042628 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11006.042628 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8707.016899 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8707.016899 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33733.272176 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33733.272176 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33733.272176 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33733.272176 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 672790 # number of writebacks -system.cpu0.dcache.writebacks::total 672790 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 934179 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 934179 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249076 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 249076 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13578 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13578 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5739 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5739 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1183255 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1183255 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1183255 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1183255 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7083 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7083 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10783 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10783 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17866 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17866 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41950985500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41950985500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 16544525000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 16544525000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 137937500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137937500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 89046500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 89046500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58495510500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 58495510500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58495510500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 58495510500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1566902000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1566902000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1566902000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1566902000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128375 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128375 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051354 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051354 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089501 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089501 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037963 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037963 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097571 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097571 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097571 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097571 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44906.795700 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44906.795700 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66423.601632 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66423.601632 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10158.896745 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10158.896745 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15516.030667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15516.030667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49436.098305 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49436.098305 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49436.098305 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49436.098305 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221220.104476 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221220.104476 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87703.011306 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87703.011306 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 686545 # number of replacements -system.cpu0.icache.tags.tagsinuse 506.490868 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 46637883 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 687057 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.880661 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 58998281500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.490868 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989240 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.989240 # Average percentage of cache occupancy +system.cpu0.dcache.writebacks::writebacks 678308 # number of writebacks +system.cpu0.dcache.writebacks::total 678308 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 937797 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 937797 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251494 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251494 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13653 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13653 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5444 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5444 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1189291 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1189291 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1189291 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1189291 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10837 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10837 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17947 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17947 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28220623500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28220623500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10708762500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10708762500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136612500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136612500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 41957000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 41957000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38929386000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 38929386000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38929386000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 38929386000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1578468500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1578468500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1578468500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1578468500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127609 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127609 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051229 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051229 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086647 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086647 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035490 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035490 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097020 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097020 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097020 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097020 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30092.465107 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30092.465107 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42580.588404 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42580.588404 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10006.042628 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10006.042628 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7707.016899 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7707.016899 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32733.272176 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32733.272176 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32733.272176 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32733.272176 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222006.821378 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222006.821378 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87951.663231 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87951.663231 # average overall mshr uncacheable latency +system.cpu0.icache.tags.replacements 698162 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.148952 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47065399 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 698674 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.363891 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 42439448500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.148952 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992478 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992478 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 417 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 351 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48012241 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48012241 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 46637883 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 46637883 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 46637883 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 46637883 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 46637883 # number of overall hits -system.cpu0.icache.overall_hits::total 46637883 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 687179 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 687179 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 687179 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 687179 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 687179 # number of overall misses -system.cpu0.icache.overall_misses::total 687179 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10623000500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10623000500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10623000500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10623000500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10623000500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10623000500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47325062 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47325062 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47325062 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47325062 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47325062 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47325062 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014520 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014520 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014520 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014520 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014520 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014520 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15458.854971 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15458.854971 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15458.854971 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15458.854971 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15458.854971 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15458.854971 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48462983 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48462983 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 47065399 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47065399 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47065399 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47065399 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47065399 # number of overall hits +system.cpu0.icache.overall_hits::total 47065399 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 698792 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 698792 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 698792 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 698792 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 698792 # number of overall misses +system.cpu0.icache.overall_misses::total 698792 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10197257500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10197257500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10197257500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10197257500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10197257500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10197257500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47764191 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47764191 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47764191 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47764191 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47764191 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47764191 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014630 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014630 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014630 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014630 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014630 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014630 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14592.693534 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14592.693534 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14592.693534 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14592.693534 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14592.693534 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14592.693534 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 686545 # number of writebacks -system.cpu0.icache.writebacks::total 686545 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687179 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 687179 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 687179 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 687179 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 687179 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 687179 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9935821500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9935821500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9935821500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9935821500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9935821500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9935821500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014520 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014520 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014520 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14458.854971 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 14458.854971 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 14458.854971 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 698162 # number of writebacks +system.cpu0.icache.writebacks::total 698162 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 698792 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 698792 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 698792 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 698792 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 698792 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 698792 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9498465500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9498465500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9498465500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9498465500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9498465500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9498465500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014630 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014630 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014630 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13592.693534 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13592.693534 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13592.693534 # average overall mshr miss latency system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2511191 # DTB read hits -system.cpu1.dtb.read_misses 2993 # DTB read misses +system.cpu1.dtb.read_hits 2421538 # DTB read hits +system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 239364 # DTB read accesses -system.cpu1.dtb.write_hits 1830032 # DTB write hits -system.cpu1.dtb.write_misses 342 # DTB write misses +system.cpu1.dtb.read_accesses 239363 # DTB read accesses +system.cpu1.dtb.write_hits 1759460 # DTB write hits +system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations -system.cpu1.dtb.write_accesses 105248 # DTB write accesses -system.cpu1.dtb.data_hits 4341223 # DTB hits -system.cpu1.dtb.data_misses 3335 # DTB misses +system.cpu1.dtb.write_accesses 105247 # DTB write accesses +system.cpu1.dtb.data_hits 4180998 # DTB hits +system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations -system.cpu1.dtb.data_accesses 344612 # DTB accesses -system.cpu1.itb.fetch_hits 1990291 # ITB hits +system.cpu1.dtb.data_accesses 344610 # DTB accesses +system.cpu1.itb.fetch_hits 1965348 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1991507 # ITB accesses +system.cpu1.itb.fetch_accesses 1966564 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -759,32 +762,32 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3965185472 # number of cpu cycles simulated +system.cpu1.numCycles 3927225148 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2869 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 81049 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27547 38.53% 38.53% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1971 2.76% 41.28% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 524 0.73% 42.01% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 41462 57.99% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 71504 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26679 48.22% 48.22% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1971 3.56% 51.78% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 524 0.95% 52.73% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 26155 47.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 55329 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1912239584500 96.45% 96.45% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 731206500 0.04% 96.49% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 374509500 0.02% 96.51% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 69246698500 3.49% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1982591999000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968490 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78631 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26567 38.35% 38.35% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1968 2.84% 41.19% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 504 0.73% 41.91% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40242 58.09% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69281 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25724 48.16% 48.16% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1968 3.68% 51.84% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 504 0.94% 52.79% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25220 47.21% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53416 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1910368546000 97.29% 97.29% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 730956000 0.04% 97.33% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 356511000 0.02% 97.34% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 52155834000 2.66% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1963611847000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968269 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.630819 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.773789 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.626708 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.771005 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -800,334 +803,342 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 435 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wripir 422 0.59% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2066 2.79% 3.39% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2001 2.80% 3.39% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed -system.cpu1.kern.callpal::swpipl 65182 88.12% 91.52% # number of callpals executed -system.cpu1.kern.callpal::rdps 2261 3.06% 94.57% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.57% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.58% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.58% # number of callpals executed -system.cpu1.kern.callpal::rti 3826 5.17% 99.76% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed +system.cpu1.kern.callpal::swpipl 63030 88.06% 91.46% # number of callpals executed +system.cpu1.kern.callpal::rdps 2146 3.00% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed +system.cpu1.kern.callpal::rti 3778 5.28% 99.75% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 73972 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2115 # number of protection mode switches +system.cpu1.kern.callpal::total 71579 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2069 # number of protection mode switches system.cpu1.kern.mode_switch::user 464 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2921 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 912 +system.cpu1.kern.mode_switch::idle 2878 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 892 system.cpu1.kern.mode_good::user 464 -system.cpu1.kern.mode_good::idle 448 -system.cpu1.kern.mode_switch_good::kernel 0.431206 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 428 +system.cpu1.kern.mode_switch_good::kernel 0.431126 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.153372 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.331636 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 19469811000 0.98% 0.98% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1729387000 0.09% 1.07% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1961392799000 98.93% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2067 # number of times the context was actually changed -system.cpu1.committedInsts 13686745 # Number of instructions committed -system.cpu1.committedOps 13686745 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12624358 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 178612 # Number of float alu accesses -system.cpu1.num_func_calls 430170 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1359717 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12624358 # number of integer instructions -system.cpu1.num_fp_insts 178612 # number of float instructions -system.cpu1.num_int_register_reads 17383561 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9260404 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 93246 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 95234 # number of times the floating registers were written -system.cpu1.num_mem_refs 4365379 # number of memory refs -system.cpu1.num_load_insts 2525846 # Number of load instructions -system.cpu1.num_store_insts 1839533 # Number of store instructions -system.cpu1.num_idle_cycles 3912234287.998026 # Number of idle cycles -system.cpu1.num_busy_cycles 52951184.001973 # Number of busy cycles -system.cpu1.not_idle_fraction 0.013354 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.986646 # Percentage of idle cycles -system.cpu1.Branches 1950147 # Number of branches fetched -system.cpu1.op_class::No_OpClass 733822 5.36% 5.36% # Class of executed instruction -system.cpu1.op_class::IntAlu 8101444 59.18% 64.54% # Class of executed instruction -system.cpu1.op_class::IntMult 23186 0.17% 64.71% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.71% # Class of executed instruction -system.cpu1.op_class::FloatAdd 14372 0.10% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1986 0.01% 64.83% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::MemRead 2600523 19.00% 83.82% # Class of executed instruction -system.cpu1.op_class::MemWrite 1840557 13.44% 97.27% # Class of executed instruction -system.cpu1.op_class::IprAccess 374219 2.73% 100.00% # Class of executed instruction +system.cpu1.kern.mode_switch_good::idle 0.148714 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.329699 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17834392500 0.91% 0.91% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1709021000 0.09% 1.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1944068431500 99.00% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2002 # number of times the context was actually changed +system.cpu1.committedInsts 13162574 # Number of instructions committed +system.cpu1.committedOps 13162574 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12139381 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 173446 # Number of float alu accesses +system.cpu1.num_func_calls 411749 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1304648 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12139381 # number of integer instructions +system.cpu1.num_fp_insts 173446 # number of float instructions +system.cpu1.num_int_register_reads 16710166 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8908141 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 90735 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 92616 # number of times the floating registers were written +system.cpu1.num_mem_refs 4204594 # number of memory refs +system.cpu1.num_load_insts 2435865 # Number of load instructions +system.cpu1.num_store_insts 1768729 # Number of store instructions +system.cpu1.num_idle_cycles 3877736087.998025 # Number of idle cycles +system.cpu1.num_busy_cycles 49489060.001975 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012602 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987398 # Percentage of idle cycles +system.cpu1.Branches 1871255 # Number of branches fetched +system.cpu1.op_class::No_OpClass 705493 5.36% 5.36% # Class of executed instruction +system.cpu1.op_class::IntAlu 7781042 59.10% 64.46% # Class of executed instruction +system.cpu1.op_class::IntMult 21322 0.16% 64.62% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.62% # Class of executed instruction +system.cpu1.op_class::FloatAdd 14181 0.11% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1986 0.02% 64.74% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::MemRead 2507774 19.05% 83.79% # Class of executed instruction +system.cpu1.op_class::MemWrite 1769717 13.44% 97.23% # Class of executed instruction +system.cpu1.op_class::IprAccess 364421 2.77% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13690109 # Class of executed instruction -system.cpu1.dcache.tags.replacements 173692 # number of replacements -system.cpu1.dcache.tags.tagsinuse 481.984896 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4164965 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 174204 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.908550 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 90321767000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.984896 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.941377 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.941377 # Average percentage of cache occupancy +system.cpu1.op_class::total 13165936 # Class of executed instruction +system.cpu1.dcache.tags.replacements 166516 # number of replacements +system.cpu1.dcache.tags.tagsinuse 486.373615 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4012325 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 167028 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.021871 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 70707818000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.373615 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949948 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.949948 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 17608650 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 17608650 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2339562 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2339562 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1707213 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1707213 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50427 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 50427 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 53080 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 53080 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4046775 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4046775 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 4046775 # number of overall hits -system.cpu1.dcache.overall_hits::total 4046775 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 123491 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 123491 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 65586 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 65586 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9255 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9255 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6109 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 6109 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 189077 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 189077 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 189077 # number of overall misses -system.cpu1.dcache.overall_misses::total 189077 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1555586500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1555586500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1871475500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1871475500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84845000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 84845000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 96965500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 96965500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 3427062000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 3427062000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 3427062000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 3427062000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2463053 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2463053 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1772799 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1772799 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59682 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 59682 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59189 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 59189 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4235852 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4235852 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4235852 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4235852 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050137 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.050137 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036996 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.036996 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155072 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155072 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103212 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103212 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044637 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044637 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044637 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044637 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12596.760088 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12596.760088 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28534.679657 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 28534.679657 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9167.477039 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9167.477039 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15872.565068 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15872.565068 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18125.218826 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18125.218826 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18125.218826 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18125.218826 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 16958396 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16958396 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2257201 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2257201 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1642023 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1642023 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48215 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 48215 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50821 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50821 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3899224 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3899224 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3899224 # number of overall hits +system.cpu1.dcache.overall_hits::total 3899224 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 118432 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 118432 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 62660 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 62660 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8936 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8936 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5856 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5856 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 181092 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 181092 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 181092 # number of overall misses +system.cpu1.dcache.overall_misses::total 181092 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1454494000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1454494000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1265962000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1265962000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 82083000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 82083000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49296000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 49296000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2720456000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2720456000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2720456000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2720456000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2375633 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2375633 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1704683 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1704683 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57151 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 57151 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56677 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 56677 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4080316 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4080316 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4080316 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4080316 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049853 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049853 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036758 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.036758 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156358 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156358 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103322 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103322 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044382 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044382 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044382 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044382 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12281.258444 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12281.258444 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20203.670603 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20203.670603 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.653536 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.653536 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8418.032787 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8418.032787 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15022.507897 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15022.507897 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15022.507897 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15022.507897 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 119726 # number of writebacks -system.cpu1.dcache.writebacks::total 119726 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123491 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 123491 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65586 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 65586 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9255 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9255 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6109 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 6109 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 189077 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 189077 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 189077 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 189077 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 118 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3348 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3348 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3466 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3466 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1432095500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1432095500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1805889500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1805889500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 75590000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 75590000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 90856500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 90856500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3237985000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3237985000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3237985000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3237985000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 25051000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 25051000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 25051000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 25051000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050137 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050137 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036996 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036996 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155072 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155072 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103212 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103212 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044637 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044637 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044637 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044637 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11596.760088 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11596.760088 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27534.679657 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27534.679657 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8167.477039 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8167.477039 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14872.565068 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14872.565068 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17125.218826 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17125.218826 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17125.218826 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17125.218826 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 212296.610169 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212296.610169 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 7227.639931 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 7227.639931 # average overall mshr uncacheable latency -system.cpu1.icache.tags.replacements 331529 # number of replacements -system.cpu1.icache.tags.tagsinuse 442.932822 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 13358029 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 332041 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.230059 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1975288394500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.932822 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865103 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.865103 # Average percentage of cache occupancy +system.cpu1.dcache.writebacks::writebacks 114398 # number of writebacks +system.cpu1.dcache.writebacks::total 114398 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118432 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 118432 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62660 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 62660 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8936 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8936 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5856 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5856 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 181092 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 181092 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 181092 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 181092 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3221 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3221 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3310 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3310 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1336062000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1336062000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1203302000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1203302000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73147000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 73147000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43441000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43441000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2539364000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2539364000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2539364000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2539364000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 20174000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 20174000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 20174000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 20174000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049853 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049853 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036758 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036758 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156358 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156358 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103322 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103322 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044382 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044382 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044382 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044382 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11281.258444 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11281.258444 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19203.670603 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19203.670603 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8185.653536 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8185.653536 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7418.203552 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7418.203552 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14022.507897 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14022.507897 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14022.507897 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14022.507897 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 226674.157303 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 226674.157303 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 6094.864048 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 6094.864048 # average overall mshr uncacheable latency +system.cpu1.icache.tags.replacements 316153 # number of replacements +system.cpu1.icache.tags.tagsinuse 445.936315 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12849230 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 316665 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.576729 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1962762014000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.936315 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870969 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.870969 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 403 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 14022191 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 14022191 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 13358029 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13358029 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13358029 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13358029 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13358029 # number of overall hits -system.cpu1.icache.overall_hits::total 13358029 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 332081 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 332081 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 332081 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 332081 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 332081 # number of overall misses -system.cpu1.icache.overall_misses::total 332081 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4540351000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4540351000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4540351000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4540351000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4540351000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4540351000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13690110 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13690110 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13690110 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13690110 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13690110 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13690110 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024257 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024257 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024257 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024257 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024257 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024257 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13672.420283 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13672.420283 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13672.420283 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13672.420283 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13672.420283 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13672.420283 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13482644 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13482644 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 12849230 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12849230 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12849230 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12849230 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12849230 # number of overall hits +system.cpu1.icache.overall_hits::total 12849230 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 316707 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 316707 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 316707 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 316707 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 316707 # number of overall misses +system.cpu1.icache.overall_misses::total 316707 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4252859000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4252859000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4252859000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4252859000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4252859000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4252859000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13165937 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13165937 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13165937 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13165937 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13165937 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13165937 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024055 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024055 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024055 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024055 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024055 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024055 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13428.370702 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13428.370702 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13428.370702 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13428.370702 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13428.370702 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13428.370702 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 331529 # number of writebacks -system.cpu1.icache.writebacks::total 331529 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 332081 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 332081 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 332081 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 332081 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 332081 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 332081 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4208270000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4208270000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4208270000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4208270000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4208270000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4208270000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024257 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024257 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024257 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12672.420283 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12672.420283 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12672.420283 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 316153 # number of writebacks +system.cpu1.icache.writebacks::total 316153 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316707 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 316707 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 316707 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 316707 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 316707 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 316707 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3936152000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3936152000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3936152000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3936152000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3936152000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3936152000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024055 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024055 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024055 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12428.370702 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12428.370702 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12428.370702 # average overall mshr miss latency system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1140,98 +1151,98 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7376 # Transaction distribution -system.iobus.trans_dist::ReadResp 7376 # Transaction distribution -system.iobus.trans_dist::WriteReq 55683 # Transaction distribution -system.iobus.trans_dist::WriteResp 55683 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14050 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7373 # Transaction distribution +system.iobus.trans_dist::ReadResp 7373 # Transaction distribution +system.iobus.trans_dist::WriteReq 55610 # Transaction distribution +system.iobus.trans_dist::WriteResp 55610 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1014 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 188 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18150 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42664 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126118 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56200 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42514 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 125966 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2749 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 171 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9075 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 82454 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2744078 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 15116500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 81882 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2743498 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 14957500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 758000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 764000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 183000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 175000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15844000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15839500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2460000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2459000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6055500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6056000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 83000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215674412 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216128057 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28533000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28456000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41948000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.566860 # Cycle average of tags in use +system.iocache.tags.replacements 41694 # number of replacements +system.iocache.tags.tagsinuse 0.569299 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1775103309000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.566860 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035429 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035429 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1756488432000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.569299 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035581 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035581 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375543 # Number of tag accesses -system.iocache.tags.data_accesses 375543 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.tags.tag_accesses 375534 # Number of tag accesses +system.iocache.tags.data_accesses 375534 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses -system.iocache.demand_misses::total 41727 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses -system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21956883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21956883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245146529 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5245146529 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5267103412 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5267103412 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5267103412 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5267103412 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21854883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21854883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858321174 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4858321174 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4880176057 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4880176057 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4880176057 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4880176057 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1240,38 +1251,38 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125467.902857 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125467.902857 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.904144 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126230.904144 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126227.704172 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126227.704172 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126227.704172 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126227.704172 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125602.775862 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125602.775862 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116921.476078 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 116921.476078 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 116957.677635 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 116957.677635 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 116957.677635 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 116957.677635 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 1 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 1 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13206883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13206883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165739741 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3165739741 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3178946624 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3178946624 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3178946624 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3178946624 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13154883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13154883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778324656 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2778324656 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2791479539 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2791479539 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2791479539 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2791479539 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1280,206 +1291,206 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75467.902857 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76187.421568 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76187.421568 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76184.403959 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76184.403959 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76184.403959 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76184.403959 # average overall mshr miss latency -system.l2c.tags.replacements 342136 # number of replacements -system.l2c.tags.tagsinuse 65163.366749 # Cycle average of tags in use -system.l2c.tags.total_refs 3685387 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407142 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.051847 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 12928623000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54851.977847 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4799.733629 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5353.675533 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 118.645951 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 39.333789 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.836975 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073238 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.081691 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.001810 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000600 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994314 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65006 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 517 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5377 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6298 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52712 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.991913 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 35906899 # Number of tag accesses -system.l2c.tags.data_accesses 35906899 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 792516 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 792516 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 746948 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 746948 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 183 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 548 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 731 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 41 # number of SCUpgradeReq hits +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75602.775862 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75602.775862 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66863.800924 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66863.800924 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66900.242990 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 66900.242990 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66900.242990 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 66900.242990 # average overall mshr miss latency +system.l2c.tags.replacements 341504 # number of replacements +system.l2c.tags.tagsinuse 65213.029486 # Cycle average of tags in use +system.l2c.tags.total_refs 3680110 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 406507 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.053005 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 9200946000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 55179.216512 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4842.215722 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5040.815485 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 110.867276 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 39.914491 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.841968 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073886 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.076917 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.001692 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000609 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995072 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1114 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5002 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6095 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52608 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 35882279 # Number of tag accesses +system.l2c.tags.data_accesses 35882279 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 792706 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 792706 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 747201 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 747201 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 175 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 534 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 709 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 33 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 65 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 124124 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 48553 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172677 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 674650 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 331142 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1005792 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 659425 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 113738 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 773163 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 674650 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 783549 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 331142 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 162291 # number of demand (read+write) hits -system.l2c.demand_hits::total 1951632 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 674650 # number of overall hits -system.l2c.overall_hits::cpu0.data 783549 # number of overall hits -system.l2c.overall_hits::cpu1.inst 331142 # number of overall hits -system.l2c.overall_hits::cpu1.data 162291 # number of overall hits -system.l2c.overall_hits::total 1951632 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 2972 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1812 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4784 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 926 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 930 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1856 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114970 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7877 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122847 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 12503 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 938 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 13441 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 271537 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 338 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 271875 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 12503 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 386507 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 938 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8215 # number of demand (read+write) misses -system.l2c.demand_misses::total 408163 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 12503 # number of overall misses -system.l2c.overall_misses::cpu0.data 386507 # number of overall misses -system.l2c.overall_misses::cpu1.inst 938 # number of overall misses -system.l2c.overall_misses::cpu1.data 8215 # number of overall misses -system.l2c.overall_misses::total 408163 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 3623500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 35439500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 39063000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3369500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 943000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 4312500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 14618383500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1037446500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 15655830000 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1639795500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 123119500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1762915000 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 33668278500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 42563000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 33710841500 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1639795500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 48286662000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 123119500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1080009500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 51129586500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1639795500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 48286662000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 123119500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1080009500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 51129586500 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 792516 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 792516 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 746948 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 746948 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3155 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2360 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5515 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 967 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 954 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1921 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 239094 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 56430 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 295524 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 687153 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 332080 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1019233 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 930962 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 114076 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1045038 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 687153 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1170056 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 332080 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 170506 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2359795 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 687153 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1170056 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 332080 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 170506 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2359795 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941997 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.767797 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.867452 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.957601 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.974843 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.966163 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.480857 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.139589 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.415692 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.018195 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.002825 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013187 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.291674 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.002963 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.260158 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018195 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.330332 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.002825 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.048180 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.172965 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.018195 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.330332 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.002825 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.048180 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.172965 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1219.212651 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 19558.222958 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 8165.342809 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3638.768898 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1013.978495 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 2323.545259 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 127149.547708 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131705.789006 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 127441.695768 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 131152.163481 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131257.462687 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 131159.511941 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 123991.494713 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 125926.035503 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 123993.899770 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 131152.163481 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 124930.886116 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 131257.462687 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 131467.985393 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 125267.568349 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 131152.163481 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 124930.886116 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 131257.462687 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 131467.985393 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 125267.568349 # average overall miss latency +system.l2c.SCUpgradeReq_hits::total 57 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 126431 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 47312 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 173743 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 685790 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 316251 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1002041 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 663459 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 109055 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 772514 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 685790 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 789890 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 316251 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 156367 # number of demand (read+write) hits +system.l2c.demand_hits::total 1948298 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 685790 # number of overall hits +system.l2c.overall_hits::cpu0.data 789890 # number of overall hits +system.l2c.overall_hits::cpu1.inst 316251 # number of overall hits +system.l2c.overall_hits::cpu1.data 156367 # number of overall hits +system.l2c.overall_hits::total 1948298 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 2941 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1732 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4673 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 898 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 897 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1795 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 115557 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 6591 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 122148 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 12981 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 455 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 13436 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 271641 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 237 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 271878 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 12981 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 387198 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 455 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 6828 # number of demand (read+write) misses +system.l2c.demand_misses::total 407462 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 12981 # number of overall misses +system.l2c.overall_misses::cpu0.data 387198 # number of overall misses +system.l2c.overall_misses::cpu1.inst 455 # number of overall misses +system.l2c.overall_misses::cpu1.data 6828 # number of overall misses +system.l2c.overall_misses::total 407462 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 1599000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 12643000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 14242000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1259500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 178000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1437500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 8901595500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 544185500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9445781000 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1065078500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 37559000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1102637500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 19890941000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 19543500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 19910484500 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1065078500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 28792536500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 37559000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 563729000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 30458903000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1065078500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 28792536500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 37559000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 563729000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 30458903000 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 792706 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 792706 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 747201 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 747201 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3116 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 2266 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5382 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 931 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 921 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1852 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 241988 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 53903 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295891 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 698771 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 316706 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1015477 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 935100 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 109292 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1044392 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 698771 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1177088 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 316706 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 163195 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2355760 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 698771 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1177088 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 316706 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 163195 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2355760 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.943838 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.764342 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.868265 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.964554 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.973941 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.969222 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.477532 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.122275 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.412814 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.018577 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.001437 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013231 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.290494 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.002169 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.260322 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018577 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.328946 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.001437 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.041840 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.172964 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018577 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.328946 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.001437 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.041840 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.172964 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 543.692622 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7299.653580 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 3047.720950 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1402.561247 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 198.439242 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 800.835655 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 77032.075080 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82564.937035 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 77330.623506 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82049.033202 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82547.252747 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 82065.905031 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 73225.105930 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82462.025316 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 73233.157887 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 82049.033202 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 74361.273819 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 82547.252747 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 82561.364968 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 74752.745041 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 82049.033202 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 74361.273819 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 82547.252747 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 82561.364968 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 74752.745041 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 79408 # number of writebacks -system.l2c.writebacks::total 79408 # number of writebacks +system.l2c.writebacks::writebacks 78937 # number of writebacks +system.l2c.writebacks::total 78937 # number of writebacks system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits @@ -1488,230 +1499,238 @@ system.l2c.overall_mshr_hits::cpu1.inst 11 # nu system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2972 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1812 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 4784 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 926 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 930 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1856 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 114970 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 7877 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 122847 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 12503 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 927 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 13430 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 271537 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 338 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 271875 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 12503 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 386507 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 927 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 8215 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 408152 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 12503 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 386507 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 927 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 8215 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 408152 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7083 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 7201 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10783 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3348 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 14131 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17866 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3466 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 21332 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 204338000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 124770000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 329108000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 63412000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 64097500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 127509500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 13468683500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 958676001 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 14427359501 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1514765500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 112494001 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 1627259501 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 30952908500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 39183000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 30992091500 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1514765500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 44421592000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 112494001 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 997859001 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 47046710502 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1514765500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 44421592000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 112494001 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 997859001 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 47046710502 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1478327000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 23575500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1501902500 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1478327000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 23575500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1501902500 # number of overall MSHR uncacheable cycles +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2941 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1732 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4673 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 898 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 897 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1795 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 115557 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 6591 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 122148 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 12981 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 444 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 13425 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 271641 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 237 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 271878 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 12981 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 387198 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 444 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 6828 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 407451 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 12981 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 387198 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 444 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 6828 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 407451 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 7199 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10837 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3221 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 14058 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17947 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3310 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 21257 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 58492500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 34311000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 92803500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 17536000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 17907500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 35443500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7746025500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 478275500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8224301000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 935268500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 32302501 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 967571001 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17174531000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 17173500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 17191704500 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 935268500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 24920556500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 32302501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 495449000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 26383576501 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 935268500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 24920556500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 32302501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 495449000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 26383576501 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1489559500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 19061000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1508620500 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1489559500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 19061000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1508620500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941997 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.767797 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.867452 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.957601 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.974843 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.966163 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.480857 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.139589 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.415692 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018195 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002791 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013177 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.291674 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002963 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260158 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018195 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.330332 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002791 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.048180 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.172961 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018195 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.330332 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002791 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.048180 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.172961 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68754.374159 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68857.615894 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68793.478261 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68479.481641 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68922.043011 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68701.239224 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117149.547708 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121705.725657 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 117441.691706 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121152.163481 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121352.751888 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121166.009010 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113991.494713 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 115926.035503 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113993.899770 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121152.163481 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114930.886116 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121352.751888 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121467.924650 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 115267.622116 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121152.163481 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114930.886116 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121352.751888 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121467.924650 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 115267.622116 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208714.810109 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199792.372881 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208568.601583 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82745.270346 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 6801.933064 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 70406.080068 # average overall mshr uncacheable latency -system.membus.trans_dist::ReadReq 7201 # Transaction distribution -system.membus.trans_dist::ReadResp 292681 # Transaction distribution -system.membus.trans_dist::WriteReq 14131 # Transaction distribution -system.membus.trans_dist::WriteResp 14131 # Transaction distribution -system.membus.trans_dist::WritebackDirty 120928 # Transaction distribution -system.membus.trans_dist::CleanEvict 262098 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16893 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11783 # Transaction distribution +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.943838 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764342 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.868265 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.964554 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.973941 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969222 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477532 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122275 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.412814 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018577 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.001402 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013220 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.290494 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002169 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260322 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018577 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.328946 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001402 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.041840 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.172959 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018577 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.328946 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001402 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.041840 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.172959 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19888.643319 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19810.046189 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19859.512091 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19527.839644 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19963.768116 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 19745.682451 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 67032.075080 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72564.937035 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 67330.623506 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72072.327821 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63225.105930 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72462.025316 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63233.157887 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64361.273819 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72561.364968 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 64752.759230 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64361.273819 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72561.364968 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 64752.759230 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209502.039381 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214168.539326 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.730518 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82997.687636 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 5758.610272 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 70970.527356 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 859272 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 411340 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadReq 7199 # Transaction distribution +system.membus.trans_dist::ReadResp 292676 # Transaction distribution +system.membus.trans_dist::WriteReq 14058 # Transaction distribution +system.membus.trans_dist::WriteResp 14058 # Transaction distribution +system.membus.trans_dist::WritebackDirty 120457 # Transaction distribution +system.membus.trans_dist::CleanEvict 261938 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16120 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11242 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 123156 # Transaction distribution -system.membus.trans_dist::ReadExResp 122284 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285480 # Transaction distribution +system.membus.trans_dist::ReadExReq 122469 # Transaction distribution +system.membus.trans_dist::ReadExResp 121633 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285477 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42664 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1185794 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1228458 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83437 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83437 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1311895 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82454 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31150976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31233430 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42514 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1182508 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1225022 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83435 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83435 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1308457 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81882 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31079040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31160922 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33891670 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 22771 # Total snoops (count) -system.membus.snoop_fanout::samples 883231 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size::total 33819162 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 21640 # Total snoops (count) +system.membus.snoop_fanout::samples 498117 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001313 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.036211 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 883231 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 497463 99.87% 99.87% # Request fanout histogram +system.membus.snoop_fanout::1 654 0.13% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 883231 # Request fanout histogram -system.membus.reqLayer0.occupancy 40519500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 498117 # Request fanout histogram +system.membus.reqLayer0.occupancy 40353000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1327558723 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1324238537 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2178214500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2174676250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 898617 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 893117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4790762 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2395545 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 361654 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1242 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1182 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 4780466 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2390280 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 355276 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 975 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 915 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 7201 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2107124 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14131 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14131 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 913453 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1018074 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 816802 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 17061 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11848 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28909 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297601 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297601 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1019260 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1080678 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2060877 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3585353 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 995690 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 558897 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7200817 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 87916672 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118008584 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 42470976 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 18601102 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 266997334 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 484769 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2873172 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.136988 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.344078 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2101675 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14058 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14058 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 871643 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1014315 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 816241 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16314 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11299 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 27613 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297840 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297840 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1015499 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1078979 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 227 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2095725 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3605435 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 949566 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 535407 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7186133 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 89403712 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118812032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40502976 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17791322 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 266510042 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 398828 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2782920 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.138526 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.345713 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2479819 86.31% 86.31% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 393117 13.68% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 234 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2397661 86.16% 86.16% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 385012 13.83% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 245 0.01% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2873172 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4223704496 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2782920 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4214914494 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 297883 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 296383 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1031139756 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1048435504 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1802215285 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1811762602 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 499214310 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 476230655 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 293827886 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 281513896 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index b4533a137..2fb77dfab 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.941276 # Nu sim_ticks 1941275996000 # Number of ticks simulated final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1048317 # Simulator instruction rate (inst/s) -host_op_rate 1048317 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36222399744 # Simulator tick rate (ticks/s) -host_mem_usage 330588 # Number of bytes of host memory used -host_seconds 53.59 # Real time elapsed on the host +host_inst_rate 855166 # Simulator instruction rate (inst/s) +host_op_rate 855166 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29548473540 # Simulator tick rate (ticks/s) +host_mem_usage 325188 # Number of bytes of host memory used +host_seconds 65.70 # Real time elapsed on the host sim_insts 56182685 # Number of instructions simulated sim_ops 56182685 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts |