diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:15:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:15:59 -0400 |
| commit | b387d8e2136b6eccf590e5223096dce6830a66ec (patch) | |
| tree | e1ec53e315c313a54a612b54b74164375dcc0a1d /tests/quick/fs/10.linux-boot/ref/alpha | |
| parent | 6f6adbf0f6a4ca96cf44a24ea575860af56eb7b2 (diff) | |
| download | gem5-b387d8e2136b6eccf590e5223096dce6830a66ec.tar.xz | |
stats: Update the stats to reflect the 1GHz default system clock
This patch updates the stats to reflect the change in the default
system clock from 1 THz to 1GHz. The changes are due to the DMA
devices now injecting requests at a lower pace.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt | 1572 | ||||
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt | 22 |
2 files changed, 797 insertions, 797 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index e568ced30..ab95e5b1c 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.950813 # Number of seconds simulated -sim_ticks 1950813247500 # Number of ticks simulated -final_tick 1950813247500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.950814 # Number of seconds simulated +sim_ticks 1950813955500 # Number of ticks simulated +final_tick 1950813955500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1287440 # Simulator instruction rate (inst/s) -host_op_rate 1287440 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41184614921 # Simulator tick rate (ticks/s) +host_inst_rate 770652 # Simulator instruction rate (inst/s) +host_op_rate 770652 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24652738853 # Simulator tick rate (ticks/s) host_mem_usage 325660 # Number of bytes of host memory used -host_seconds 47.37 # Real time elapsed on the host -sim_insts 60982794 # Number of instructions simulated -sim_ops 60982794 # Number of ops (including micro ops) simulated +host_seconds 79.13 # Real time elapsed on the host +sim_insts 60983017 # Number of instructions simulated +sim_ops 60983017 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 827264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24727680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24727744 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 38464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 439808 # Number of bytes read from this memory -system.physmem.bytes_read::total 28684096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 439872 # Number of bytes read from this memory +system.physmem.bytes_read::total 28684224 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 827264 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 38464 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 865728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7706368 # Number of bytes written to this memory -system.physmem.bytes_written::total 7706368 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7706496 # Number of bytes written to this memory +system.physmem.bytes_written::total 7706496 # Number of bytes written to this memory system.physmem.num_reads::cpu0.inst 12926 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386370 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386371 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 601 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6872 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448189 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120412 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120412 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 6873 # Number of read requests responded to by this memory +system.physmem.num_reads::total 448191 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120414 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120414 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.inst 424061 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12675575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1358859 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12675603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1358858 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 19717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 225449 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14703661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 225481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14703721 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 424061 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 19717 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 443778 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3950336 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3950336 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3950336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 3950400 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3950400 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3950400 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 424061 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12675575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1358859 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12675603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1358858 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 19717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 225449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18653997 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 448189 # Total number of read requests seen -system.physmem.writeReqs 120412 # Total number of write requests seen -system.physmem.cpureqs 599134 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28684096 # Total number of bytes read from memory -system.physmem.bytesWritten 7706368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28684096 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7706368 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.data 225481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18654121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 448191 # Total number of read requests seen +system.physmem.writeReqs 120414 # Total number of write requests seen +system.physmem.cpureqs 599152 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28684224 # Total number of bytes read from memory +system.physmem.bytesWritten 7706496 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28684224 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7706496 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 7172 # Reqs where no action is needed +system.physmem.neitherReadNorWrite 7175 # Reqs where no action is needed system.physmem.perBankRdReqs::0 28371 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 27660 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 28102 # Track reads on a per bank basis @@ -72,7 +72,7 @@ system.physmem.perBankRdReqs::11 28196 # Tr system.physmem.perBankRdReqs::12 28402 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 28329 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 27819 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27647 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27649 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 7817 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 7535 # Track writes on a per bank basis @@ -88,17 +88,17 @@ system.physmem.perBankWrReqs::11 7772 # Tr system.physmem.perBankWrReqs::12 8034 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 7948 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 7345 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7159 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 522 # Number of times wr buffer was full causing retry -system.physmem.totGap 1950759532000 # Total gap between requests +system.physmem.numWrRetry 530 # Number of times wr buffer was full causing retry +system.physmem.totGap 1950760240000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 448189 # Categorize read packet sizes +system.physmem.readPktSize::6 448191 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -107,7 +107,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 120934 # categorize write packet sizes +system.physmem.writePktSize::6 120944 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -116,29 +116,29 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 7172 # categorize neither packet sizes +system.physmem.neitherpktsize::6 7175 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 409832 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7493 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2815 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1774 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1998 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1671 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1601 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1562 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1645 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1753 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 874 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 409750 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7530 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5264 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2844 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1780 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1657 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1586 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1655 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1735 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 881 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 259 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 108 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -152,13 +152,13 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5228 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 5230 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 5231 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 5235 # What write queue length does an incoming req see @@ -175,24 +175,24 @@ system.physmem.wrQLenPdf::19 5235 # Wh system.physmem.wrQLenPdf::20 5235 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5235 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2865774804 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10947900804 # Sum of mem lat for all requests -system.physmem.totBusLat 1792528000 # Total cycles spent in databus access -system.physmem.totBankLat 6289598000 # Total cycles spent in bank access -system.physmem.avgQLat 6394.93 # Average queueing delay per request -system.physmem.avgBankLat 14035.15 # Average bank access latency per request +system.physmem.totQLat 2917085023 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10998617023 # Sum of mem lat for all requests +system.physmem.totBusLat 1792536000 # Total cycles spent in databus access +system.physmem.totBankLat 6288996000 # Total cycles spent in bank access +system.physmem.avgQLat 6509.40 # Average queueing delay per request +system.physmem.avgBankLat 14033.74 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24430.08 # Average memory access latency +system.physmem.avgMemAccLat 24543.14 # Average memory access latency system.physmem.avgRdBW 14.70 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 14.70 # Average consumed read bandwidth in MB/s @@ -200,177 +200,177 @@ system.physmem.avgConsumedWrBW 3.95 # Av system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.12 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.50 # Average write queue length over time -system.physmem.readRowHits 428033 # Number of row buffer hits during reads -system.physmem.writeRowHits 76777 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.51 # Row buffer hit rate for reads +system.physmem.avgWrQLen 10.51 # Average write queue length over time +system.physmem.readRowHits 428061 # Number of row buffer hits during reads +system.physmem.writeRowHits 76773 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads system.physmem.writeRowHitRate 63.76 # Row buffer hit rate for writes -system.physmem.avgGap 3430805.67 # Average gap between requests -system.l2c.replacements 341333 # number of replacements -system.l2c.tagsinuse 65247.038846 # Cycle average of tags in use -system.l2c.total_refs 2438074 # Total number of references to valid blocks. -system.l2c.sampled_refs 406309 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.000541 # Average number of references to valid blocks. +system.physmem.avgGap 3430782.78 # Average gap between requests +system.l2c.replacements 341335 # number of replacements +system.l2c.tagsinuse 65247.035905 # Cycle average of tags in use +system.l2c.total_refs 2438054 # Total number of references to valid blocks. +system.l2c.sampled_refs 406311 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.000463 # Average number of references to valid blocks. system.l2c.warmup_cycle 6891280002 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55545.297156 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4807.218464 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4686.690338 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 164.376104 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 43.456784 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.847554 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 55545.332470 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4807.217204 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4686.652945 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 164.376424 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 43.456861 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.847555 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.073352 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.071513 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.inst 0.002508 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.000663 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.995591 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 674220 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 658221 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 328583 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 113537 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1774561 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 791464 # number of Writeback hits -system.l2c.Writeback_hits::total 791464 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 176 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 567 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 743 # number of UpgradeReq hits +system.l2c.ReadReq_hits::cpu0.inst 674205 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 658217 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 328581 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 113535 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1774538 # 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average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42021.112177 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 31476.753335 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41952.024958 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51693.865477 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 32168.460790 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42021.112177 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 31476.753335 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41952.024958 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51693.865477 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 32168.460790 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -503,12 +503,12 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41696 # number of replacements -system.iocache.tagsinuse 0.562945 # Cycle average of tags in use +system.iocache.tagsinuse 0.562950 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1745713328000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.562945 # Average occupied blocks per requestor +system.iocache.occ_blocks::tsunami.ide 0.562950 # Average occupied blocks per requestor system.iocache.occ_percent::tsunami.ide 0.035184 # Average percentage of cache occupancy system.iocache.occ_percent::total 0.035184 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses @@ -521,12 +521,12 @@ system.iocache.overall_misses::tsunami.ide 41728 # system.iocache.overall_misses::total 41728 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21268998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21268998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 9455401806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9455401806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9476670804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9476670804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9476670804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9476670804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 9497531806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9497531806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9518800804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9518800804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9518800804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9518800804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -545,17 +545,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 227555.877118 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 227555.877118 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 227105.799559 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 227105.799559 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 227105.799559 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 227105.799559 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 186741 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228569.787399 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 228569.787399 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 228115.433378 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 228115.433378 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 228115.433378 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 228115.433378 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 188605 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23044 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 22594 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.103671 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.347570 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -571,12 +571,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41728 system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12116000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7292629022 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7292629022 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7304745022 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7304745022 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7304745022 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7304745022 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7334778982 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7334778982 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 7346894982 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7346894982 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 7346894982 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7346894982 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -587,12 +587,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68840.909091 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 68840.909091 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 175506.089286 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 175506.089286 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 175056.197805 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 175056.197805 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 175056.197805 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 175056.197805 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176520.479929 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 176520.479929 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176066.309960 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 176066.309960 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176066.309960 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 176066.309960 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -610,15 +610,15 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7424678 # DTB read hits +system.cpu0.dtb.read_hits 7424685 # DTB read hits system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 5011102 # DTB write hits +system.cpu0.dtb.write_hits 5011105 # DTB write hits system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 12435780 # DTB hits +system.cpu0.dtb.data_hits 12435790 # DTB hits system.cpu0.dtb.data_misses 8256 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678125 # DTB accesses @@ -638,28 +638,28 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3900399022 # number of cpu cycles simulated +system.cpu0.numCycles 3900399041 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47350752 # Number of instructions committed -system.cpu0.committedOps 47350752 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 43919757 # Number of integer alu accesses +system.cpu0.committedInsts 47350784 # Number of instructions committed +system.cpu0.committedOps 47350784 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 43919786 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 206365 # Number of float alu accesses system.cpu0.num_func_calls 1188579 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5567605 # number of instructions that are conditional controls -system.cpu0.num_int_insts 43919757 # number of integer instructions +system.cpu0.num_conditional_control_insts 5567614 # number of instructions that are conditional controls +system.cpu0.num_int_insts 43919786 # number of integer instructions system.cpu0.num_fp_insts 206365 # number of float instructions -system.cpu0.num_int_register_reads 60378447 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32741783 # number of times the integer registers were written +system.cpu0.num_int_register_reads 60378491 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32741801 # number of times the integer registers were written system.cpu0.num_fp_register_reads 100221 # number of times the floating registers were read system.cpu0.num_fp_register_writes 101982 # number of times the floating registers were written -system.cpu0.num_mem_refs 12475681 # number of memory refs -system.cpu0.num_load_insts 7451619 # Number of load instructions -system.cpu0.num_store_insts 5024062 # Number of store instructions -system.cpu0.num_idle_cycles 3698907701.219057 # Number of idle cycles -system.cpu0.num_busy_cycles 201491320.780943 # Number of busy cycles -system.cpu0.not_idle_fraction 0.051659 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.948341 # Percentage of idle cycles +system.cpu0.num_mem_refs 12475691 # number of memory refs +system.cpu0.num_load_insts 7451626 # Number of load instructions +system.cpu0.num_store_insts 5024065 # Number of store instructions +system.cpu0.num_idle_cycles 3698902228.116945 # Number of idle cycles +system.cpu0.num_busy_cycles 201496812.883055 # Number of busy cycles +system.cpu0.not_idle_fraction 0.051661 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.948339 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed system.cpu0.kern.inst.hwrei 162790 # number of hwrei instructions executed @@ -675,12 +675,12 @@ system.cpu0.kern.ipl_good::22 1971 1.74% 50.93% # nu system.cpu0.kern.ipl_good::30 443 0.39% 51.32% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 55007 48.68% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 113002 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1898626830000 97.36% 97.36% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 93050500 0.00% 97.36% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 759970000 0.04% 97.40% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 326793000 0.02% 97.42% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 50392837500 2.58% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1950199481000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1898623862000 97.36% 97.36% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 92984000 0.00% 97.36% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 759861500 0.04% 97.40% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 328899000 0.02% 97.42% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 50393884000 2.58% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1950199490500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.991187 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -745,8 +745,8 @@ system.cpu0.kern.mode_switch_good::kernel 0.186890 # f system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.314924 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1946498286500 99.83% 99.83% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3408187000 0.17% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1946502716500 99.83% 99.83% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3403122000 0.17% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3025 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA @@ -780,51 +780,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 686559 # number of replacements -system.cpu0.icache.tagsinuse 509.179293 # Cycle average of tags in use -system.cpu0.icache.total_refs 46672188 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 687071 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 67.929207 # Average number of references to valid blocks. +system.cpu0.icache.replacements 686544 # number of replacements +system.cpu0.icache.tagsinuse 509.179305 # Cycle average of tags in use +system.cpu0.icache.total_refs 46672235 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 687056 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 67.930758 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 32409447000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.179293 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 509.179305 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.994491 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.994491 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 46672188 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 46672188 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 46672188 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 46672188 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 46672188 # number of overall hits -system.cpu0.icache.overall_hits::total 46672188 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 687164 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 687164 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 687164 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 687164 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 687164 # number of overall misses -system.cpu0.icache.overall_misses::total 687164 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9577778500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9577778500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9577778500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9577778500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9577778500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9577778500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47359352 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47359352 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47359352 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47359352 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47359352 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47359352 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014510 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014510 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014510 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014510 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014510 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014510 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13938.126124 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13938.126124 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13938.126124 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13938.126124 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13938.126124 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13938.126124 # average overall miss latency +system.cpu0.icache.ReadReq_hits::cpu0.inst 46672235 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 46672235 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 46672235 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 46672235 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 46672235 # number of overall hits +system.cpu0.icache.overall_hits::total 46672235 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 687149 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 687149 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 687149 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 687149 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 687149 # number of overall misses +system.cpu0.icache.overall_misses::total 687149 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9571696500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9571696500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9571696500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9571696500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9571696500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9571696500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47359384 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47359384 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47359384 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47359384 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47359384 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47359384 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014509 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014509 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014509 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014509 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014509 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014509 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13929.579320 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13929.579320 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13929.579320 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13929.579320 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13929.579320 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13929.579320 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -833,112 +833,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687164 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 687164 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 687164 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 687164 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 687164 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 687164 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8203450500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8203450500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8203450500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8203450500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8203450500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8203450500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014510 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014510 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014510 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014510 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014510 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014510 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11938.126124 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11938.126124 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11938.126124 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11938.126124 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11938.126124 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11938.126124 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687149 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 687149 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 687149 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 687149 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 687149 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 687149 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8197398500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8197398500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8197398500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8197398500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8197398500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8197398500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014509 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014509 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014509 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11929.579320 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11929.579320 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11929.579320 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1171741 # number of replacements -system.cpu0.dcache.tagsinuse 505.264481 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11253752 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1172158 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.600883 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1171731 # number of replacements +system.cpu0.dcache.tagsinuse 505.264467 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11253773 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1172148 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.600983 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 93429000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.264481 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu0.data 505.264467 # Average occupied blocks per requestor system.cpu0.dcache.occ_percent::cpu0.data 0.986845 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.986845 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6351991 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6351991 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4607363 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4607363 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138394 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 138394 # number of LoadLockedReq hits +system.cpu0.dcache.ReadReq_hits::cpu0.data 6351999 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6351999 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4607371 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4607371 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138396 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 138396 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145569 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 145569 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10959354 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10959354 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10959354 # number of overall hits -system.cpu0.dcache.overall_hits::total 10959354 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 933040 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 933040 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 249280 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 249280 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13436 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13436 # number of LoadLockedReq misses +system.cpu0.dcache.demand_hits::cpu0.data 10959370 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10959370 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10959370 # number of overall hits +system.cpu0.dcache.overall_hits::total 10959370 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 933038 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 933038 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 249274 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 249274 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13435 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13435 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5731 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 5731 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1182320 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1182320 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1182320 # number of overall misses -system.cpu0.dcache.overall_misses::total 1182320 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 20820883000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 20820883000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7761604000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7761604000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 144502500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 144502500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43447000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 43447000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 28582487000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 28582487000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 28582487000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 28582487000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7285031 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7285031 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4856643 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4856643 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151830 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 151830 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 1182312 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1182312 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1182312 # number of overall misses +system.cpu0.dcache.overall_misses::total 1182312 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 20824713000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 20824713000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7766651000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7766651000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 144248500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 144248500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43490500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 43490500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 28591364000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 28591364000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 28591364000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 28591364000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7285037 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7285037 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4856645 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4856645 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151831 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 151831 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151300 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 151300 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12141674 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12141674 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12141674 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12141674 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 12141682 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12141682 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12141682 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12141682 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128076 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.128076 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051328 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051328 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088494 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088494 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051326 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051326 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088487 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088487 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037878 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037878 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097377 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097377 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097377 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097377 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22315.102246 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 22315.102246 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31136.087933 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 31136.087933 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10754.874963 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10754.874963 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7581.050427 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7581.050427 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24174.916266 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 24174.916266 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24174.916266 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 24174.916266 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097376 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097376 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097376 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097376 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22319.254950 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 22319.254950 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31157.084172 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 31157.084172 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10736.769632 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10736.769632 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7588.640726 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7588.640726 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24182.588014 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 24182.588014 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24182.588014 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 24182.588014 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -947,62 +947,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 672349 # number of writebacks -system.cpu0.dcache.writebacks::total 672349 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 933040 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 933040 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249280 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 249280 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13436 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13436 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 672345 # number of writebacks +system.cpu0.dcache.writebacks::total 672345 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 933038 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 933038 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249274 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 249274 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13435 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13435 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5731 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 5731 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1182320 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1182320 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1182320 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1182320 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18954803000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18954803000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7263044000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7263044000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117630500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117630500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31985000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31985000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26217847000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 26217847000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26217847000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 26217847000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465453500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465453500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2285524000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2285524000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3750977500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3750977500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1182312 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1182312 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1182312 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1182312 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18958637000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18958637000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7268103000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7268103000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117378500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117378500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32028500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32028500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26226740000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 26226740000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26226740000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 26226740000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465462500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465462500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2285670500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2285670500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3751133000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3751133000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128076 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128076 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051328 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051328 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088494 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088494 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051326 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051326 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088487 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088487 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037878 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037878 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097377 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097377 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097377 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097377 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20315.102246 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20315.102246 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29136.087933 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29136.087933 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8754.874963 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8754.874963 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5581.050427 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5581.050427 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22174.916266 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22174.916266 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22174.916266 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22174.916266 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097376 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097376 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097376 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097376 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20319.254950 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20319.254950 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29157.084172 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29157.084172 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8736.769632 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8736.769632 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5588.640726 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5588.640726 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22182.588014 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22182.588014 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22182.588014 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22182.588014 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1014,15 +1014,15 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2500235 # DTB read hits +system.cpu1.dtb.read_hits 2500361 # DTB read hits system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 1820988 # DTB write hits +system.cpu1.dtb.write_hits 1820984 # DTB write hits system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 4321223 # DTB hits +system.cpu1.dtb.data_hits 4321345 # DTB hits system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344610 # DTB accesses @@ -1042,26 +1042,26 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3901626495 # number of cpu cycles simulated +system.cpu1.numCycles 3901627911 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13632042 # Number of instructions committed -system.cpu1.committedOps 13632042 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12571491 # Number of integer alu accesses +system.cpu1.committedInsts 13632233 # Number of instructions committed +system.cpu1.committedOps 13632233 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12571690 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 180459 # Number of float alu accesses -system.cpu1.num_func_calls 426717 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1355011 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12571491 # number of integer instructions +system.cpu1.num_func_calls 426713 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1355142 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12571690 # number of integer instructions system.cpu1.num_fp_insts 180459 # number of float instructions -system.cpu1.num_int_register_reads 17311598 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9221787 # number of times the integer registers were written +system.cpu1.num_int_register_reads 17311762 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9221860 # number of times the integer registers were written system.cpu1.num_fp_register_reads 94168 # number of times the floating registers were read system.cpu1.num_fp_register_writes 96184 # number of times the floating registers were written -system.cpu1.num_mem_refs 4345531 # number of memory refs -system.cpu1.num_load_insts 2514982 # Number of load instructions -system.cpu1.num_store_insts 1830549 # Number of store instructions -system.cpu1.num_idle_cycles 3850258507.998026 # Number of idle cycles -system.cpu1.num_busy_cycles 51367987.001974 # Number of busy cycles +system.cpu1.num_mem_refs 4345653 # number of memory refs +system.cpu1.num_load_insts 2515108 # Number of load instructions +system.cpu1.num_store_insts 1830545 # Number of store instructions +system.cpu1.num_idle_cycles 3850258537.998026 # Number of idle cycles +system.cpu1.num_busy_cycles 51369373.001974 # Number of busy cycles system.cpu1.not_idle_fraction 0.013166 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.986834 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -1077,11 +1077,11 @@ system.cpu1.kern.ipl_good::22 1966 3.56% 51.78% # nu system.cpu1.kern.ipl_good::30 525 0.95% 52.73% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 26090 47.27% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 55196 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1907138262500 97.76% 97.76% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 705201000 0.04% 97.80% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 364168000 0.02% 97.82% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 42604858000 2.18% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1950812489500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::0 1907137344500 97.76% 97.76% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 705261000 0.04% 97.80% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 364072500 0.02% 97.82% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 42606519500 2.18% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1950813197500 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.967853 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl @@ -1118,65 +1118,65 @@ system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # nu system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.callpal::total 73828 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2126 # number of protection mode switches +system.cpu1.kern.mode_switch::kernel 2125 # number of protection mode switches system.cpu1.kern.mode_switch::user 465 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2924 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2925 # number of protection mode switches system.cpu1.kern.mode_good::kernel 915 system.cpu1.kern.mode_good::user 465 system.cpu1.kern.mode_good::idle 450 -system.cpu1.kern.mode_switch_good::kernel 0.430386 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.430588 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.153899 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::idle 0.153846 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::total 0.331822 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 18665784500 0.96% 0.96% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1711228500 0.09% 1.04% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1930435473000 98.96% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::kernel 18664257000 0.96% 0.96% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1710579000 0.09% 1.04% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1930438358000 98.96% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2086 # number of times the context was actually changed -system.cpu1.icache.replacements 328648 # number of replacements -system.cpu1.icache.tagsinuse 446.257828 # Cycle average of tags in use -system.cpu1.icache.total_refs 13306209 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 329160 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 40.424745 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1948917036000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 446.257828 # Average occupied blocks per requestor +system.cpu1.icache.replacements 328646 # number of replacements +system.cpu1.icache.tagsinuse 446.257851 # Cycle average of tags in use +system.cpu1.icache.total_refs 13306402 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 329158 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 40.425577 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1948915489000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 446.257851 # Average occupied blocks per requestor system.cpu1.icache.occ_percent::cpu1.inst 0.871597 # Average percentage of cache occupancy system.cpu1.icache.occ_percent::total 0.871597 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 13306209 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13306209 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13306209 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13306209 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13306209 # number of overall hits -system.cpu1.icache.overall_hits::total 13306209 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 329196 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 329196 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 329196 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 329196 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 329196 # number of overall misses -system.cpu1.icache.overall_misses::total 329196 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4347354500 # 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average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13203.569931 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13203.569931 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1185,112 +1185,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 329196 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 329196 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 329196 # 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average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14149.643598 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14149.643598 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14149.643598 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14149.643598 # average overall miss latency +system.cpu1.dcache.demand_hits::cpu1.data 4028441 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 4028441 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 4028441 # number of overall hits +system.cpu1.dcache.overall_hits::total 4028441 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 123241 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 123241 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 64769 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 64769 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9346 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9346 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6142 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 6142 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 188010 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 188010 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 188010 # number of overall misses +system.cpu1.dcache.overall_misses::total 188010 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1494406500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1494406500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1166606000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1166606000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 85391000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 85391000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44592000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 44592000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2661012500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2661012500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2661012500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2661012500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2452457 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2452457 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1763994 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1763994 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59566 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 59566 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59069 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 59069 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4216451 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4216451 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4216451 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4216451 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050252 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.050252 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036717 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.036717 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156902 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156902 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103980 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103980 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044590 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044590 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044590 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044590 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12125.887489 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12125.887489 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18011.795766 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18011.795766 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9136.635994 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9136.635994 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7260.175838 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7260.175838 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14153.568959 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14153.568959 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14153.568959 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14153.568959 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1299,62 +1299,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 119115 # number of writebacks -system.cpu1.dcache.writebacks::total 119115 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123236 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 123236 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 64754 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 64754 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9347 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9347 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6143 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 6143 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 187990 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 187990 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 187990 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 187990 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1247220000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1247220000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1036791500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1036791500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66696000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 66696000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32229500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32229500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2284011500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2284011500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2284011500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2284011500 # number of overall MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 119125 # number of writebacks +system.cpu1.dcache.writebacks::total 119125 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123241 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 123241 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 64769 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 64769 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9346 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9346 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6142 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 6142 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 188010 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 188010 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 188010 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 188010 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1247924500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1247924500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1037068000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1037068000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66699000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 66699000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32308000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32308000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2284992500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2284992500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2284992500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2284992500 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19381000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19381000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723171500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723171500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742552500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742552500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050253 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050253 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036709 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036709 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156916 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156916 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103995 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103995 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044586 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044586 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044586 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044586 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10120.581648 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10120.581648 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16011.234827 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16011.234827 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7135.551514 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7135.551514 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5246.540778 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5246.540778 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12149.643598 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12149.643598 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12149.643598 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12149.643598 # average overall mshr miss latency +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723292500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723292500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742673500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742673500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050252 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050252 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036717 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036717 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156902 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156902 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103980 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103980 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044590 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044590 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044590 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044590 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10125.887489 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10125.887489 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16011.795766 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16011.795766 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7136.635994 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7136.635994 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5260.175838 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5260.175838 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12153.568959 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12153.568959 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12153.568959 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12153.568959 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 997f2e448..dfbac48e1 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.910582 # Nu sim_ticks 1910582068000 # Number of ticks simulated final_tick 1910582068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1092208 # Simulator instruction rate (inst/s) -host_op_rate 1092208 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37180157619 # Simulator tick rate (ticks/s) -host_mem_usage 321564 # Number of bytes of host memory used -host_seconds 51.39 # Real time elapsed on the host +host_inst_rate 942466 # Simulator instruction rate (inst/s) +host_op_rate 942466 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32082735017 # Simulator tick rate (ticks/s) +host_mem_usage 321492 # Number of bytes of host memory used +host_seconds 59.55 # Real time elapsed on the host sim_insts 56125446 # Number of instructions simulated sim_ops 56125446 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory @@ -815,12 +815,12 @@ system.cpu.l2cache.demand_mshr_miss_latency::total 12860525290 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 561273079 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12299252211 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 12860525290 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331550000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331550000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1891670000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1891670000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3223220000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3223220000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334146000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895221500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895221500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229367500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229367500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250366 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141600 # mshr miss rate for ReadReq accesses |