diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
| commit | 3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0 (patch) | |
| tree | 63ce098bc690eb5b58b3297b747794d623cface4 /tests/quick/fs/10.linux-boot/ref/alpha | |
| parent | af2b14a362281f36347728e13dcd6b2c4d3c4991 (diff) | |
| download | gem5-3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0.tar.xz | |
Stats: Update stats for RAS and LRU fixes.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha')
8 files changed, 1677 insertions, 1681 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index 06d87b670..86d337feb 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:39:49 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:04 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 97861500 Exiting @ tick 1870335522500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index b45122ce6..046013e55 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,167 +4,167 @@ sim_seconds 1.870336 # Nu sim_ticks 1870335522500 # Number of ticks simulated final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2870976 # Simulator instruction rate (inst/s) -host_op_rate 2870973 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 85025108641 # Simulator tick rate (ticks/s) -host_mem_usage 298608 # Number of bytes of host memory used -host_seconds 22.00 # Real time elapsed on the host +host_inst_rate 4061827 # Simulator instruction rate (inst/s) +host_op_rate 4061823 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 120292600618 # Simulator tick rate (ticks/s) +host_mem_usage 301032 # Number of bytes of host memory used +host_seconds 15.55 # Real time elapsed on the host sim_insts 63154034 # Number of instructions simulated sim_ops 63154034 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 855168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 67882688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 139840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 770176 # Number of bytes read from this memory -system.physmem.bytes_read::total 72297472 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 855168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 139840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 995008 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10452352 # Number of bytes written to this memory -system.physmem.bytes_written::total 10452352 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13362 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1060667 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 668672 # Number of bytes read from this memory +system.physmem.bytes_read::total 70883520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 761216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 872192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7861504 # Number of bytes written to this memory +system.physmem.bytes_written::total 7861504 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11894 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1042079 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2185 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 12034 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1129648 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 163318 # Number of write requests responded to by this memory -system.physmem.num_writes::total 163318 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 457227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 36294391 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10448 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1107555 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122836 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122836 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 406994 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35658338 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 74767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 411785 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 38654814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 457227 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 74767 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 531994 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5588490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5588490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5588490 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 457227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 36294391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 357514 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37898826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 406994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 466329 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4203259 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4203259 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4203259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 406994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35658338 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 74767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 411785 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 44243304 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 1051788 # number of replacements -system.l2c.tagsinuse 34117.721410 # Cycle average of tags in use -system.l2c.total_refs 2341203 # Total number of references to valid blocks. -system.l2c.sampled_refs 1087985 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.151871 # Average number of references to valid blocks. -system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 23831.931773 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3683.485712 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 6336.188239 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 152.381317 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 113.734368 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.363646 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056206 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.096683 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.002325 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.001735 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.520595 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 871618 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 748887 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 101445 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 35685 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1757635 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 811846 # number of Writeback hits -system.l2c.Writeback_hits::total 811846 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 134 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 39 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 173 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 15 # number of SCUpgradeReq hits +system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42102084 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 1000626 # number of replacements +system.l2c.tagsinuse 65381.922680 # Cycle average of tags in use +system.l2c.total_refs 2464692 # Total number of references to valid blocks. +system.l2c.sampled_refs 1065768 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.312597 # Average number of references to valid blocks. +system.l2c.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 56158.702580 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4894.236968 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4134.601551 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 174.423287 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 19.958294 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.997649 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 873086 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 763047 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 101896 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 36724 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1774753 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 816766 # number of Writeback hits +system.l2c.Writeback_hits::total 816766 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 133 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 36 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 169 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 24 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 164417 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 14126 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 178543 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 871618 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 913304 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 101445 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 49811 # number of demand (read+write) hits -system.l2c.demand_hits::total 1936178 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 871618 # number of overall hits -system.l2c.overall_hits::cpu0.data 913304 # number of overall hits -system.l2c.overall_hits::cpu1.inst 101445 # number of overall hits -system.l2c.overall_hits::cpu1.data 49811 # number of overall hits -system.l2c.overall_hits::total 1936178 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13362 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 943555 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2185 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 2326 # number of ReadReq misses -system.l2c.ReadReq_misses::total 961428 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2441 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 567 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3008 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 166157 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 14260 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 180417 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 873086 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 929204 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 101896 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 50984 # number of demand (read+write) hits +system.l2c.demand_hits::total 1955170 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 873086 # number of overall hits +system.l2c.overall_hits::cpu0.data 929204 # number of overall hits +system.l2c.overall_hits::cpu1.inst 101896 # number of overall hits +system.l2c.overall_hits::cpu1.data 50984 # number of overall hits +system.l2c.overall_hits::total 1955170 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 11894 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 908 # number of ReadReq misses +system.l2c.ReadReq_misses::total 941297 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 570 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3012 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 65 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 101 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 166 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 117481 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 9826 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 127307 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13362 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 1061036 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2185 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 12152 # number of demand (read+write) misses -system.l2c.demand_misses::total 1088735 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13362 # number of overall misses -system.l2c.overall_misses::cpu0.data 1061036 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2185 # number of overall misses -system.l2c.overall_misses::cpu1.data 12152 # number of overall misses -system.l2c.overall_misses::total 1088735 # number of overall misses +system.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 165 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 115706 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9662 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 125368 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 11894 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 1042467 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1734 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10570 # number of demand (read+write) misses +system.l2c.demand_misses::total 1066665 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11894 # number of overall misses +system.l2c.overall_misses::cpu0.data 1042467 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1734 # number of overall misses +system.l2c.overall_misses::cpu1.data 10570 # number of overall misses +system.l2c.overall_misses::total 1066665 # number of overall misses system.l2c.ReadReq_accesses::cpu0.inst 884980 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1692442 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1689808 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 103630 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 38011 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2719063 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 811846 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 811846 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 37632 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2716050 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 816766 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 816766 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 2575 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 606 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 3181 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 80 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 110 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 190 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 281898 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 23952 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 305850 # number of ReadExReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 281863 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 23922 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 305785 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 884980 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1974340 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1971671 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 103630 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 61963 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3024913 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 61554 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3021835 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 884980 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1974340 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1971671 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 103630 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 61963 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3024913 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015099 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.557511 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.021085 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.061193 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.353588 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947961 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.935644 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.945615 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.812500 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.918182 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.873684 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.416750 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.410237 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.416240 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015099 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.537413 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.021085 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.196117 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.359923 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015099 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.537413 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.021085 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.196117 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.359923 # miss rate for overall accesses +system.l2c.overall_accesses::cpu1.data 61554 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3021835 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.548442 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.016733 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024128 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.346568 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.948350 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.940594 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.946872 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.410504 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.403896 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.409987 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.528723 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.016733 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.171719 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.352986 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.528723 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.016733 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.171719 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.352986 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -173,8 +173,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 121798 # number of writebacks -system.l2c.writebacks::total 121798 # number of writebacks +system.l2c.writebacks::writebacks 81316 # number of writebacks +system.l2c.writebacks::total 81316 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41695 # number of replacements system.iocache.tagsinuse 0.435437 # Cycle average of tags in use @@ -451,39 +451,39 @@ system.cpu0.icache.cache_copies 0 # nu system.cpu0.icache.writebacks::writebacks 95 # number of writebacks system.cpu0.icache.writebacks::total 95 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1978962 # number of replacements -system.cpu0.dcache.tagsinuse 504.827058 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13123502 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1979474 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 6.629793 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1978686 # number of replacements +system.cpu0.dcache.tagsinuse 507.129778 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13123753 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1979198 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 6.630844 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 504.827058 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.985990 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.985990 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7298106 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7298106 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5462265 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5462265 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172138 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 172138 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186635 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 186635 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12760371 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12760371 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12760371 # number of overall hits -system.cpu0.dcache.overall_hits::total 12760371 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1683563 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1683563 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 285996 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 285996 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16159 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16159 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 703 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 703 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1969559 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1969559 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1969559 # number of overall misses -system.cpu0.dcache.overall_misses::total 1969559 # number of overall misses +system.cpu0.dcache.occ_blocks::cpu0.data 507.129778 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.990488 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7298337 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7298337 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5462263 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5462263 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186624 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 186624 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12760600 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12760600 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12760600 # number of overall hits +system.cpu0.dcache.overall_hits::total 12760600 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1683332 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1683332 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 285998 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 285998 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 714 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1969330 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1969330 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1969330 # number of overall misses +system.cpu0.dcache.overall_misses::total 1969330 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981669 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748261 # number of WriteReq accesses(hits+misses) @@ -496,18 +496,18 @@ system.cpu0.dcache.demand_accesses::cpu0.data 14729930 system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187444 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.187444 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049753 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049753 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085817 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085817 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003753 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003753 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133711 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.133711 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133711 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.133711 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187419 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.187419 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049754 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085785 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085785 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003811 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003811 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133696 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.133696 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133696 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.133696 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -516,8 +516,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 771740 # number of writebacks -system.cpu0.dcache.writebacks::total 771740 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 775641 # number of writebacks +system.cpu0.dcache.writebacks::total 775641 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses @@ -687,42 +687,42 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 15 # number of writebacks -system.cpu1.icache.writebacks::total 15 # number of writebacks +system.cpu1.icache.writebacks::writebacks 18 # number of writebacks +system.cpu1.icache.writebacks::total 18 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 62338 # number of replacements -system.cpu1.dcache.tagsinuse 391.951263 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 391.951263 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.765530 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.765530 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1109315 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1109315 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 707444 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 707444 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15129 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 15129 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15613 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 15613 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1816759 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1816759 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1816759 # number of overall hits -system.cpu1.dcache.overall_hits::total 1816759 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 41650 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 41650 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 25861 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 25861 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1289 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1289 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 732 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 732 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 67511 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 67511 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 67511 # number of overall misses -system.cpu1.dcache.overall_misses::total 67511 # number of overall misses +system.cpu1.dcache.replacements 62044 # number of replacements +system.cpu1.dcache.tagsinuse 421.562730 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1836054 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 62382 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 29.432432 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1851115552500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 421.562730 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.823365 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.823365 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1109521 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1109521 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 707457 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 707457 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1816978 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1816978 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1816978 # number of overall hits +system.cpu1.dcache.overall_hits::total 1816978 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 41444 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 41444 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 25848 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 25848 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 67292 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 67292 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 67292 # number of overall misses +system.cpu1.dcache.overall_misses::total 67292 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses) @@ -735,18 +735,18 @@ system.cpu1.dcache.demand_accesses::cpu1.data 1884270 system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036187 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036187 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035266 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.035266 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078511 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078511 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044784 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044784 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035829 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.035829 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035829 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035829 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036008 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036008 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035249 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.035249 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035713 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.035713 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035713 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035713 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -755,8 +755,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 39996 # number of writebacks -system.cpu1.dcache.writebacks::total 39996 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 41012 # number of writebacks +system.cpu1.dcache.writebacks::total 41012 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index 92dc7ad3d..d842316f6 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -1,12 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:07:23 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:03 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1829332258000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 4492aa0b0..e2a65cb45 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,109 +4,109 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332258000 # Number of ticks simulated final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2878195 # Simulator instruction rate (inst/s) -host_op_rate 2878193 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 87696777763 # Simulator tick rate (ticks/s) -host_mem_usage 296144 # Number of bytes of host memory used -host_seconds 20.86 # Real time elapsed on the host +host_inst_rate 4017982 # Simulator instruction rate (inst/s) +host_op_rate 4017978 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 122425314574 # Simulator tick rate (ticks/s) +host_mem_usage 297960 # Number of bytes of host memory used +host_seconds 14.94 # Real time elapsed on the host sim_insts 60038305 # Number of instructions simulated sim_ops 60038305 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 955904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 68042304 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652608 # Number of bytes read from this memory -system.physmem.bytes_read::total 71650816 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 955904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 955904 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10156864 # Number of bytes written to this memory -system.physmem.bytes_written::total 10156864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 14936 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1063161 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41447 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1119544 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 158701 # Number of write requests responded to by this memory -system.physmem.num_writes::total 158701 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 522543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 37195159 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1450042 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 39167743 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 522543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 522543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5552225 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5552225 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5552225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 522543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 37195159 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1450042 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 44719968 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 1045877 # number of replacements -system.l2c.tagsinuse 33807.015903 # Cycle average of tags in use -system.l2c.total_refs 2291835 # Total number of references to valid blocks. -system.l2c.sampled_refs 1077848 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.126306 # Average number of references to valid blocks. -system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 23613.410409 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3680.391656 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6513.213838 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.360312 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.056158 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.099384 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.515854 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 905267 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 794128 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1699395 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 825291 # number of Writeback hits -system.l2c.Writeback_hits::total 825291 # number of Writeback hits +system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory +system.physmem.bytes_read::total 70349696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7411392 # Number of bytes written to this memory +system.physmem.bytes_written::total 7411392 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1044366 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1099214 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115803 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115803 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36537607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1449867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 38456489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4051419 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4051419 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4051419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 992301 # number of replacements +system.l2c.tagsinuse 65424.374305 # Cycle average of tags in use +system.l2c.total_refs 2433195 # Total number of references to valid blocks. +system.l2c.sampled_refs 1057464 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.300972 # Average number of references to valid blocks. +system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 4247.922119 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.998297 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 811183 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1717980 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 833599 # number of Writeback hits +system.l2c.Writeback_hits::total 833599 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 185383 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 185383 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 905267 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 979511 # number of demand (read+write) hits -system.l2c.demand_hits::total 1884778 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 905267 # number of overall hits -system.l2c.overall_hits::cpu.data 979511 # number of overall hits -system.l2c.overall_hits::total 1884778 # number of overall hits -system.l2c.ReadReq_misses::cpu.inst 14936 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 944693 # number of ReadReq misses -system.l2c.ReadReq_misses::total 959629 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu.data 187125 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 187125 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 906797 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 998308 # number of demand (read+write) hits +system.l2c.demand_hits::total 1905105 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.inst 906797 # number of overall hits +system.l2c.overall_hits::cpu.data 998308 # number of overall hits +system.l2c.overall_hits::total 1905105 # number of overall hits +system.l2c.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 927640 # number of ReadReq misses +system.l2c.ReadReq_misses::total 941046 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 118859 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 118859 # number of ReadExReq misses -system.l2c.demand_misses::cpu.inst 14936 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 1063552 # number of demand (read+write) misses -system.l2c.demand_misses::total 1078488 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.inst 14936 # number of overall misses -system.l2c.overall_misses::cpu.data 1063552 # number of overall misses -system.l2c.overall_misses::total 1078488 # number of overall misses +system.l2c.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 117117 # number of ReadExReq misses +system.l2c.demand_misses::cpu.inst 13406 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 1044757 # number of demand (read+write) misses +system.l2c.demand_misses::total 1058163 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.inst 13406 # number of overall misses +system.l2c.overall_misses::cpu.data 1044757 # number of overall misses +system.l2c.overall_misses::total 1058163 # number of overall misses system.l2c.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1738821 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2659024 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 825291 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 825291 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1738823 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2659026 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 833599 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 833599 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu.data 304242 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 304242 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 2043063 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2963266 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 2043065 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2963268 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 2043063 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2963266 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.016231 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.543295 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.360895 # miss rate for ReadReq accesses +system.l2c.overall_accesses::cpu.data 2043065 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2963268 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.533487 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.353906 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.923077 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.923077 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.390673 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.390673 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.inst 0.016231 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.520567 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.363952 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.inst 0.016231 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.520567 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.363952 # miss rate for overall accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.384947 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.384947 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.511367 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.357093 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.511367 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.357093 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -115,8 +115,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 117189 # number of writebacks -system.l2c.writebacks::total 117189 # number of writebacks +system.l2c.writebacks::writebacks 74291 # number of writebacks +system.l2c.writebacks::total 74291 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41686 # number of replacements system.iocache.tagsinuse 1.225570 # Cycle average of tags in use @@ -388,37 +388,37 @@ system.cpu.icache.cache_copies 0 # nu system.cpu.icache.writebacks::writebacks 108 # number of writebacks system.cpu.icache.writebacks::total 108 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2042700 # number of replacements +system.cpu.dcache.replacements 2042702 # number of replacements system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2043212 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 14038431 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2043214 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 6.870759 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7807782 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807782 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 7807780 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807780 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 5848212 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655994 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655994 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655994 # number of overall hits -system.cpu.dcache.overall_hits::total 13655994 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721705 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721705 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 13655992 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655992 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655992 # number of overall hits +system.cpu.dcache.overall_hits::total 13655992 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721707 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721707 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026067 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026067 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026067 # number of overall misses -system.cpu.dcache.overall_misses::total 2026067 # number of overall misses +system.cpu.dcache.demand_misses::cpu.data 2026069 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026069 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026069 # number of overall misses +system.cpu.dcache.overall_misses::total 2026069 # number of overall misses system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses) @@ -431,16 +431,16 @@ system.cpu.dcache.demand_accesses::cpu.data 15682061 # system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180671 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.180671 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.129196 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.129196 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.129196 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.129196 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,8 +449,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 825183 # number of writebacks -system.cpu.dcache.writebacks::total 825183 # number of writebacks +system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks +system.cpu.dcache.writebacks::total 833491 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index b3456c80f..4abaeca9d 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:42:45 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:10 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 562628000 -Exiting @ tick 1958647095000 because m5_exit instruction encountered +Exiting @ tick 1957577582000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index e92359043..9611b47c5 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.958647 # Number of seconds simulated -sim_ticks 1958647095000 # Number of ticks simulated -final_tick 1958647095000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.957578 # Number of seconds simulated +sim_ticks 1957577582000 # Number of ticks simulated +final_tick 1957577582000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1245422 # Simulator instruction rate (inst/s) -host_op_rate 1245421 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41097010927 # Simulator tick rate (ticks/s) -host_mem_usage 295412 # Number of bytes of host memory used -host_seconds 47.66 # Real time elapsed on the host -sim_insts 59355643 # Number of instructions simulated -sim_ops 59355643 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 919744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 25960192 # Number of bytes read from this memory +host_inst_rate 1866861 # Simulator instruction rate (inst/s) +host_op_rate 1866860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61595044213 # Simulator tick rate (ticks/s) +host_mem_usage 296940 # Number of bytes of host memory used +host_seconds 31.78 # Real time elapsed on the host +sim_insts 59331415 # Number of instructions simulated +sim_ops 59331415 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 825984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24749824 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 51456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 468416 # Number of bytes read from this memory -system.physmem.bytes_read::total 30050624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 919744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 51456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 971200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10333120 # Number of bytes written to this memory -system.physmem.bytes_written::total 10333120 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14371 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 405628 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 37440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 398080 # Number of bytes read from this memory +system.physmem.bytes_read::total 28662144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 825984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 37440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 863424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7684736 # Number of bytes written to this memory +system.physmem.bytes_written::total 7684736 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12906 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386716 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 804 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 7319 # Number of read requests responded to by this memory -system.physmem.num_reads::total 469541 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 161455 # Number of write requests responded to by this memory -system.physmem.num_writes::total 161455 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 469581 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13254145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1353391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 26271 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 239153 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15342541 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 469581 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 26271 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 495852 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5275642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5275642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5275642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 469581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13254145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1353391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 26271 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 239153 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 20618183 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 393576 # number of replacements -system.l2c.tagsinuse 34487.800710 # Cycle average of tags in use -system.l2c.total_refs 2371449 # Total number of references to valid blocks. -system.l2c.sampled_refs 427769 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.543761 # Average number of references to valid blocks. -system.l2c.warmup_cycle 10882116000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 23419.887612 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3728.336055 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 7139.593108 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 100.838318 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 99.145617 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.357359 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056890 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.108942 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001539 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.001513 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.526242 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 901389 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 758006 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 86187 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 33004 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1778586 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 816294 # number of Writeback hits -system.l2c.Writeback_hits::total 816294 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 172 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 53 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 225 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 18 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 19 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 37 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 170288 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 12569 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 182857 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 901389 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 928294 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 86187 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 45573 # number of demand (read+write) hits -system.l2c.demand_hits::total 1961443 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 901389 # number of overall hits -system.l2c.overall_hits::cpu0.data 928294 # number of overall hits -system.l2c.overall_hits::cpu1.inst 86187 # number of overall hits -system.l2c.overall_hits::cpu1.data 45573 # number of overall hits -system.l2c.overall_hits::total 1961443 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 14371 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 288456 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 815 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1138 # number of ReadReq misses -system.l2c.ReadReq_misses::total 304780 # number of ReadReq misses +system.physmem.num_reads::cpu1.inst 585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6220 # Number of read requests responded to by this memory +system.physmem.num_reads::total 447846 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120074 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120074 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 421942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12643087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1354131 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 19126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 203353 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14641639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 421942 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 19126 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 441068 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3925635 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3925635 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3925635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 421942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12643087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1354131 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 19126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 203353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18567274 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 340832 # number of replacements +system.l2c.tagsinuse 65295.945000 # Cycle average of tags in use +system.l2c.total_refs 2492123 # Total number of references to valid blocks. +system.l2c.sampled_refs 405944 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.139081 # Average number of references to valid blocks. +system.l2c.warmup_cycle 7739998000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 55466.932424 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4795.907583 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4852.495880 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 163.850290 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 16.758824 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.846358 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.073180 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.074043 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.002500 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000256 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.996337 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 902441 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 771400 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 86210 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 33732 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1793783 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 821051 # number of Writeback hits +system.l2c.Writeback_hits::total 821051 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 166 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 54 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 220 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 14 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.578027 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40007.372976 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40013.135837 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40003.254300 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.578027 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40007.372976 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40013.135837 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -345,14 +345,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41694 # number of replacements -system.iocache.tagsinuse 0.563721 # Cycle average of tags in use +system.iocache.tagsinuse 0.563379 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1751545158000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.563721 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.035233 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.035233 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1750565168000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.563379 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.035211 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.035211 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -363,12 +363,12 @@ system.iocache.overall_misses::tsunami.ide 41726 # system.iocache.overall_misses::total 41726 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20052998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20052998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5721783806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5721783806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5741836804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5741836804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5741836804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5741836804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5719883806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5719883806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5739936804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5739936804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5739936804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5739936804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -387,17 +387,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.114943 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 115247.114943 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137701.766606 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 137701.766606 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 137608.129320 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 137608.129320 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64596068 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137656.040768 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137656.040768 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137562.594162 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137562.594162 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137562.594162 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137562.594162 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 64630068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6176.122765 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6179.373554 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -413,12 +413,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41726 system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11004998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11004998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3560928000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3560928000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3571932998 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3571932998 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3571932998 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3571932998 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3559028000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3559028000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3570032998 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3570032998 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3570032998 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3570032998 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -429,12 +429,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.114943 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 63247.114943 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85698.113208 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 85698.113208 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85604.491157 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 85604.491157 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85604.491157 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 85604.491157 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85652.387370 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85652.387370 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85558.955999 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85558.955999 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85558.955999 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85558.955999 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -452,22 +452,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8633623 # DTB read hits +system.cpu0.dtb.read_hits 8630502 # DTB read hits system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 6044743 # DTB write hits +system.cpu0.dtb.write_hits 6043026 # DTB write hits system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 14678366 # DTB hits +system.cpu0.dtb.data_hits 14673528 # DTB hits system.cpu0.dtb.data_misses 8256 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3853057 # ITB hits +system.cpu0.itb.fetch_hits 3852973 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3856928 # ITB accesses +system.cpu0.itb.fetch_accesses 3856844 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -480,55 +480,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3916023774 # number of cpu cycles simulated +system.cpu0.numCycles 3914070794 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 54072652 # Number of instructions committed -system.cpu0.committedOps 54072652 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 50043234 # Number of integer alu accesses +system.cpu0.committedInsts 54051547 # Number of instructions committed +system.cpu0.committedOps 54051547 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 50023130 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 293967 # Number of float alu accesses -system.cpu0.num_func_calls 1426863 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6237040 # number of instructions that are conditional controls -system.cpu0.num_int_insts 50043234 # number of integer instructions +system.cpu0.num_func_calls 1426247 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6235141 # number of instructions that are conditional controls +system.cpu0.num_int_insts 50023130 # number of integer instructions system.cpu0.num_fp_insts 293967 # number of float instructions -system.cpu0.num_int_register_reads 68528072 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37080372 # number of times the integer registers were written +system.cpu0.num_int_register_reads 68498295 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37064173 # number of times the integer registers were written system.cpu0.num_fp_register_reads 143353 # number of times the floating registers were read system.cpu0.num_fp_register_writes 146452 # number of times the floating registers were written -system.cpu0.num_mem_refs 14724357 # number of memory refs -system.cpu0.num_load_insts 8664914 # Number of load instructions -system.cpu0.num_store_insts 6059443 # Number of store instructions -system.cpu0.num_idle_cycles 3680034047.555842 # Number of idle cycles -system.cpu0.num_busy_cycles 235989726.444158 # Number of busy cycles -system.cpu0.not_idle_fraction 0.060263 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.939737 # Percentage of idle cycles +system.cpu0.num_mem_refs 14719518 # number of memory refs +system.cpu0.num_load_insts 8661793 # Number of load instructions +system.cpu0.num_store_insts 6057725 # Number of store instructions +system.cpu0.num_idle_cycles 3679914036.735006 # Number of idle cycles +system.cpu0.num_busy_cycles 234156757.264994 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059824 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940176 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6380 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 202972 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 72739 40.62% 40.62% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6362 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 202969 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 72743 40.62% 40.62% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 131 0.07% 40.70% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1975 1.10% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1974 1.10% 41.80% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 104211 58.20% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 179062 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71372 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 104206 58.20% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 179060 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 71376 49.27% 49.27% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1975 1.36% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1974 1.36% 50.73% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71366 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 144850 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1899667899000 97.02% 97.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 79058000 0.00% 97.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 565985500 0.03% 97.05% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 4729500 0.00% 97.05% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 57694185000 2.95% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1958011857000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981207 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 71370 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 144857 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1898820258500 97.03% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 78970000 0.00% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 565865000 0.03% 97.06% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 4687500 0.00% 97.06% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 57565586000 2.94% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1957035367000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981208 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684822 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808938 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684893 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808986 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -567,28 +567,28 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # nu system.cpu0.kern.callpal::swpctx 3894 2.07% 2.12% # number of callpals executed system.cpu0.kern.callpal::tbi 51 0.03% 2.15% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.15% # number of callpals executed -system.cpu0.kern.callpal::swpipl 172198 91.50% 93.64% # number of callpals executed -system.cpu0.kern.callpal::rdps 6678 3.55% 97.19% # number of callpals executed +system.cpu0.kern.callpal::swpipl 172198 91.50% 93.65% # number of callpals executed +system.cpu0.kern.callpal::rdps 6677 3.55% 97.19% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 97.20% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed -system.cpu0.kern.callpal::rti 4751 2.52% 99.73% # number of callpals executed +system.cpu0.kern.callpal::rti 4750 2.52% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 188203 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7302 # number of protection mode switches +system.cpu0.kern.callpal::total 188201 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7301 # number of protection mode switches system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1283 system.cpu0.kern.mode_good::user 1283 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.175705 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.175729 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.298893 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1954355762000 99.83% 99.83% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3390072000 0.17% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.298928 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1953310949000 99.83% 99.83% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3370111000 0.17% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3895 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA @@ -622,51 +622,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 915147 # number of replacements -system.cpu0.icache.tagsinuse 508.800486 # Cycle average of tags in use -system.cpu0.icache.total_refs 53165471 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 915659 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 58.062522 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 36696092000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 508.800486 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.993751 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.993751 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 53165471 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 53165471 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 53165471 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 53165471 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 53165471 # number of overall hits -system.cpu0.icache.overall_hits::total 53165471 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 915781 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 915781 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 915781 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 915781 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 915781 # number of overall misses -system.cpu0.icache.overall_misses::total 915781 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13429132500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13429132500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13429132500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13429132500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13429132500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13429132500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 54081252 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 54081252 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 54081252 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 54081252 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 54081252 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 54081252 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016933 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.016933 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016933 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.016933 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016933 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.016933 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14664.130944 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14664.130944 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14664.130944 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14664.130944 # average overall miss latency +system.cpu0.icache.replacements 914734 # number of replacements +system.cpu0.icache.tagsinuse 508.814250 # Cycle average of tags in use +system.cpu0.icache.total_refs 53144779 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 915246 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 58.066114 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 35914239000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 508.814250 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.993778 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.993778 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 53144779 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 53144779 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 53144779 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 53144779 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 53144779 # number of overall hits +system.cpu0.icache.overall_hits::total 53144779 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 915368 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 915368 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 915368 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 915368 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 915368 # number of overall misses +system.cpu0.icache.overall_misses::total 915368 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13361799000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13361799000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13361799000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13361799000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13361799000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13361799000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 54060147 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 54060147 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 54060147 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 54060147 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 54060147 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 54060147 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016932 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.016932 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016932 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.016932 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016932 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.016932 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14597.188235 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14597.188235 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14597.188235 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14597.188235 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14597.188235 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14597.188235 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -677,112 +677,112 @@ system.cpu0.icache.fast_writes 0 # nu system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 55 # number of writebacks system.cpu0.icache.writebacks::total 55 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915781 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 915781 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 915781 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 915781 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 915781 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 915781 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10681093500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10681093500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10681093500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10681093500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10681093500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10681093500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016933 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016933 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016933 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11663.370937 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11663.370937 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11663.370937 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915368 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 915368 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 915368 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 915368 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 915368 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 915368 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10614998000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10614998000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10614998000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10614998000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10614998000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10614998000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016932 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016932 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016932 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.016932 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016932 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.016932 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11596.426792 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11596.426792 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11596.426792 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11596.426792 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11596.426792 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11596.426792 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1338438 # number of replacements -system.cpu0.dcache.tagsinuse 503.524900 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13348404 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1338837 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.970149 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1337419 # number of replacements +system.cpu0.dcache.tagsinuse 506.341163 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13344261 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1337832 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.974542 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 83958000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 503.524900 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.983447 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.983447 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7421006 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7421006 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5560133 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5560133 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176505 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 176505 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191674 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 191674 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12981139 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12981139 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12981139 # number of overall hits -system.cpu0.dcache.overall_hits::total 12981139 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1036101 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1036101 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 291536 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 291536 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16544 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16544 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 410 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 410 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1327637 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1327637 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1327637 # number of overall misses -system.cpu0.dcache.overall_misses::total 1327637 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26570279500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 26570279500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9109954000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 9109954000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 234949000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 234949000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2973000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 2973000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 35680233500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 35680233500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 35680233500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 35680233500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8457107 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8457107 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5851669 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5851669 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193049 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 193049 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192084 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 192084 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14308776 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14308776 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14308776 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14308776 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122512 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.122512 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049821 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049821 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085698 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085698 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002134 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002134 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092785 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.092785 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092785 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092785 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25644.487844 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25644.487844 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31248.127161 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 31248.127161 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14201.462766 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14201.462766 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7251.219512 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7251.219512 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26874.991809 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 26874.991809 # average overall miss latency +system.cpu0.dcache.occ_blocks::cpu0.data 506.341163 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.988948 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.988948 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7419012 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7419012 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5558431 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5558431 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176349 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 176349 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191666 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 191666 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12977443 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12977443 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12977443 # number of overall hits +system.cpu0.dcache.overall_hits::total 12977443 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1034980 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1034980 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 291529 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 291529 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16694 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16694 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 411 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 411 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1326509 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1326509 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1326509 # number of overall misses +system.cpu0.dcache.overall_misses::total 1326509 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 25827814500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 25827814500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9022984000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 9022984000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 234039000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 234039000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2995000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 2995000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 34850798500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 34850798500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 34850798500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 34850798500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8453992 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8453992 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5849960 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5849960 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193043 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 193043 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192077 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 192077 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14303952 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14303952 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14303952 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14303952 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122425 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.122425 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049834 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049834 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086478 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086478 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002140 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002140 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092737 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092737 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092737 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092737 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24954.892365 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 24954.892365 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30950.553804 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30950.553804 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14019.348269 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14019.348269 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7287.104623 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7287.104623 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26272.568448 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26272.568448 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26272.568448 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 26272.568448 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -791,62 +791,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 786441 # number of writebacks -system.cpu0.dcache.writebacks::total 786441 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1036101 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1036101 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291536 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 291536 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16544 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16544 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 410 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 410 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1327637 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1327637 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1327637 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1327637 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23461938500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23461938500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8235346000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8235346000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 185317000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 185317000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1743000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1743000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31697284500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 31697284500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31697284500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 31697284500 # number of overall MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 790358 # number of writebacks +system.cpu0.dcache.writebacks::total 790358 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1034980 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1034980 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291529 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 291529 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16694 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16694 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 411 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 411 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326509 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1326509 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326509 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1326509 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 22722836500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 22722836500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8148397000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8148397000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183957000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183957000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1762000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1762000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30871233500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 30871233500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30871233500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 30871233500 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 884470000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 884470000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1242107000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1242107000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2126577000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2126577000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122512 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122512 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049821 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049821 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085698 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085698 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002134 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002134 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092785 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092785 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092785 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092785 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22644.451168 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22644.451168 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28248.127161 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28248.127161 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11201.462766 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11201.462766 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4251.219512 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4251.219512 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23874.963186 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23874.963186 # average overall mshr miss latency +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1241998500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1241998500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2126468500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2126468500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122425 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122425 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049834 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049834 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086478 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086478 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002140 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002140 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092737 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092737 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092737 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092737 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21954.855649 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21954.855649 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27950.553804 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27950.553804 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11019.348269 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11019.348269 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4287.104623 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4287.104623 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23272.539802 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23272.539802 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23272.539802 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23272.539802 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -858,22 +858,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1050117 # DTB read hits +system.cpu1.dtb.read_hits 1049963 # DTB read hits system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 651208 # DTB write hits +system.cpu1.dtb.write_hits 651106 # DTB write hits system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 1701325 # DTB hits +system.cpu1.dtb.data_hits 1701069 # DTB hits system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1493438 # ITB hits +system.cpu1.itb.fetch_hits 1493400 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1494654 # ITB accesses +system.cpu1.itb.fetch_accesses 1494616 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -886,51 +886,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3917294190 # number of cpu cycles simulated +system.cpu1.numCycles 3915155164 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5282991 # Number of instructions committed -system.cpu1.committedOps 5282991 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 4948310 # Number of integer alu accesses +system.cpu1.committedInsts 5279868 # Number of instructions committed +system.cpu1.committedOps 5279868 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 4945263 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses -system.cpu1.num_func_calls 158031 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 510974 # number of instructions that are conditional controls -system.cpu1.num_int_insts 4948310 # number of integer instructions +system.cpu1.num_func_calls 157997 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 510441 # number of instructions that are conditional controls +system.cpu1.num_int_insts 4945263 # number of integer instructions system.cpu1.num_fp_insts 34031 # number of float instructions -system.cpu1.num_int_register_reads 6886066 # number of times the integer registers were read -system.cpu1.num_int_register_writes 3732878 # number of times the integer registers were written +system.cpu1.num_int_register_reads 6880916 # number of times the integer registers were read +system.cpu1.num_int_register_writes 3730475 # number of times the integer registers were written system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written -system.cpu1.num_mem_refs 1710778 # number of memory refs -system.cpu1.num_load_insts 1056124 # Number of load instructions -system.cpu1.num_store_insts 654654 # Number of store instructions -system.cpu1.num_idle_cycles 3898237020.998010 # Number of idle cycles -system.cpu1.num_busy_cycles 19057169.001990 # Number of busy cycles -system.cpu1.not_idle_fraction 0.004865 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.995135 # Percentage of idle cycles +system.cpu1.num_mem_refs 1710522 # number of memory refs +system.cpu1.num_load_insts 1055970 # Number of load instructions +system.cpu1.num_store_insts 654552 # Number of store instructions +system.cpu1.num_idle_cycles 3896226886.998010 # Number of idle cycles +system.cpu1.num_busy_cycles 18928277.001990 # Number of busy cycles +system.cpu1.not_idle_fraction 0.004835 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.995165 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2318 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 36191 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 9289 32.15% 32.15% # number of times we switched to this ipl +system.cpu1.kern.inst.quiesce 2314 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 36187 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 9288 32.15% 32.15% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1969 6.81% 38.96% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 88 0.30% 39.26% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 17551 60.74% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 28897 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 9279 45.20% 45.20% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::30 88 0.30% 39.27% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 17548 60.73% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 28893 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 9278 45.20% 45.20% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1969 9.59% 54.80% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 88 0.43% 55.22% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 9191 44.78% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 20527 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1917878582000 97.92% 97.92% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 507844000 0.03% 97.94% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 54239000 0.00% 97.95% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 40205672000 2.05% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1958646337000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_good::30 88 0.43% 55.23% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 9190 44.77% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 20525 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1917614123000 97.96% 97.96% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 507941000 0.03% 97.98% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 53691000 0.00% 97.99% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 39401069000 2.01% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1957576824000 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.998923 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.523674 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.710351 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.523706 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.710380 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -952,7 +952,7 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # nu system.cpu1.kern.callpal::swpctx 337 1.14% 1.17% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.01% 1.18% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.02% 1.20% # number of callpals executed -system.cpu1.kern.callpal::swpipl 24309 82.25% 83.46% # number of callpals executed +system.cpu1.kern.callpal::swpipl 24305 82.25% 83.46% # number of callpals executed system.cpu1.kern.callpal::rdps 2170 7.34% 90.80% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 90.80% # number of callpals executed system.cpu1.kern.callpal::wrusp 4 0.01% 90.82% # number of callpals executed @@ -961,66 +961,66 @@ system.cpu1.kern.callpal::rti 2530 8.56% 99.39% # nu system.cpu1.kern.callpal::callsys 136 0.46% 99.85% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.15% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 29554 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 804 # number of protection mode switches -system.cpu1.kern.mode_switch::user 464 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2064 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 477 -system.cpu1.kern.mode_good::user 464 +system.cpu1.kern.callpal::total 29550 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 803 # number of protection mode switches +system.cpu1.kern.mode_switch::user 463 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2065 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 476 +system.cpu1.kern.mode_good::user 463 system.cpu1.kern.mode_good::idle 13 -system.cpu1.kern.mode_switch_good::kernel 0.593284 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.592777 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.006298 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.286315 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 3571416000 0.18% 0.18% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1745054000 0.09% 0.27% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1953329865000 99.73% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::idle 0.006295 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.285800 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 3531821000 0.18% 0.18% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1727088000 0.09% 0.27% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1952317913000 99.73% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 338 # number of times the context was actually changed -system.cpu1.icache.replacements 86457 # number of replacements -system.cpu1.icache.tagsinuse 419.807616 # Cycle average of tags in use -system.cpu1.icache.total_refs 5199349 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 86969 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 59.783935 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1942711132000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 419.807616 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.819937 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.819937 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 5199349 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5199349 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5199349 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5199349 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5199349 # number of overall hits -system.cpu1.icache.overall_hits::total 5199349 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 87005 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 87005 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 87005 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 87005 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 87005 # number of overall misses -system.cpu1.icache.overall_misses::total 87005 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1260607500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1260607500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1260607500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1260607500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1260607500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1260607500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5286354 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5286354 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5286354 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5286354 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5286354 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5286354 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016458 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.016458 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016458 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.016458 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016458 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.016458 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14488.908683 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14488.908683 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14488.908683 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14488.908683 # average overall miss latency +system.cpu1.icache.replacements 86261 # number of replacements +system.cpu1.icache.tagsinuse 419.419440 # Cycle average of tags in use +system.cpu1.icache.total_refs 5196422 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 86773 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 59.885241 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1941709468000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 419.419440 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.819179 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.819179 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 5196422 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5196422 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 5196422 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5196422 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 5196422 # number of overall hits +system.cpu1.icache.overall_hits::total 5196422 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 86809 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 86809 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 86809 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 86809 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 86809 # number of overall misses +system.cpu1.icache.overall_misses::total 86809 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1248608500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1248608500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1248608500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1248608500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1248608500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1248608500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 5283231 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5283231 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 5283231 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5283231 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 5283231 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5283231 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016431 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.016431 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016431 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.016431 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016431 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.016431 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14383.399187 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14383.399187 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14383.399187 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14383.399187 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14383.399187 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14383.399187 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1031,112 +1031,112 @@ system.cpu1.icache.fast_writes 0 # nu system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks::writebacks 14 # number of writebacks system.cpu1.icache.writebacks::total 14 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 87005 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 87005 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 87005 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 87005 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 87005 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 87005 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 999558500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 999558500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 999558500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 999558500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 999558500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 999558500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016458 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.016458 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.016458 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11488.517901 # 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number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 988145500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 988145500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 988145500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 988145500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 988145500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 988145500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016431 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016431 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016431 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.016431 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 12762 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 12026 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 12026 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 1677346 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1677346 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1677346 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1677346 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035572 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035572 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032036 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.032036 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.073970 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.073970 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.042159 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.042159 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034228 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.034228 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034228 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.034228 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13311.332739 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13311.332739 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26940.237092 # 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number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1145,62 +1145,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 29784 # number of writebacks -system.cpu1.dcache.writebacks::total 29784 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37113 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 37113 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20421 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 20421 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 982 # 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number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298050500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 298050500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 309464000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 309464000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035676 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035676 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032042 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032042 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.076923 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.076923 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.041975 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.041975 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.034296 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034296 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11368.577048 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11368.577048 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24265.853778 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24265.853778 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10318.737271 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10318.737271 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9704.950495 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9704.950495 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15946.310008 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15946.310008 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 30624 # number of writebacks +system.cpu1.dcache.writebacks::total 30624 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 36999 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 36999 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20414 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 20414 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 944 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 944 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 507 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 507 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 57413 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 57413 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 57413 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 57413 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 381507000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 381507000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 488716000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 488716000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8473000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8473000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4831000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4831000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 870223000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 870223000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 870223000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 870223000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 11412500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11412500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298066500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 298066500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 309479000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 309479000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035572 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035572 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032036 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032036 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.073970 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.073970 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.042159 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.042159 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034228 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.034228 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034228 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034228 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10311.278683 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10311.278683 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23940.237092 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23940.237092 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8975.635593 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8975.635593 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9528.599606 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9528.599606 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15157.246617 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15157.246617 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15157.246617 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15157.246617 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index 33fb3404f..c4cb3c061 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -1,12 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:23:20 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:05 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1915548867000 because m5_exit instruction encountered +Exiting @ tick 1915492819000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 42fcfede1..abedba373 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.915549 # Number of seconds simulated -sim_ticks 1915548867000 # Number of ticks simulated -final_tick 1915548867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.915493 # Number of seconds simulated +sim_ticks 1915492819000 # Number of ticks simulated +final_tick 1915492819000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1238015 # Simulator instruction rate (inst/s) -host_op_rate 1238014 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42244373047 # Simulator tick rate (ticks/s) -host_mem_usage 292960 # Number of bytes of host memory used -host_seconds 45.34 # Real time elapsed on the host -sim_insts 56137087 # Number of instructions simulated -sim_ops 56137087 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 943040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 26067904 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652416 # Number of bytes read from this memory -system.physmem.bytes_read::total 29663360 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 943040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 943040 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10122368 # Number of bytes written to this memory -system.physmem.bytes_written::total 10122368 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 14735 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 407311 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41444 # Number of read requests responded to by this memory -system.physmem.num_reads::total 463490 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 158162 # Number of write requests responded to by this memory -system.physmem.num_writes::total 158162 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 492308 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13608582 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1384677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15485567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 492308 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 492308 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5284317 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5284317 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5284317 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 492308 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13608582 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1384677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 20769884 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 389289 # number of replacements -system.l2c.tagsinuse 34352.038344 # Cycle average of tags in use -system.l2c.total_refs 2311163 # Total number of references to valid blocks. -system.l2c.sampled_refs 421794 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.479364 # Average number of references to valid blocks. -system.l2c.warmup_cycle 6937912000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 23110.665097 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3746.363547 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 7495.009700 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.352641 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.057165 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.114365 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.524171 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 913599 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 796862 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1710461 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 826671 # number of Writeback hits -system.l2c.Writeback_hits::total 826671 # number of Writeback hits +host_inst_rate 1853108 # Simulator instruction rate (inst/s) +host_op_rate 1853107 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63179819624 # Simulator tick rate (ticks/s) +host_mem_usage 294892 # Number of bytes of host memory used +host_seconds 30.32 # Real time elapsed on the host +sim_insts 56182681 # Number of instructions simulated +sim_ops 56182681 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24846208 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory +system.physmem.bytes_read::total 28349056 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7388480 # Number of bytes written to this memory +system.physmem.bytes_written::total 7388480 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388222 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory +system.physmem.num_reads::total 442954 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115445 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115445 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 444009 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12971183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1384684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14799876 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 444009 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 444009 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3857221 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3857221 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3857221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 444009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12971183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1384684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18657097 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 336041 # number of replacements +system.l2c.tagsinuse 65311.191779 # Cycle average of tags in use +system.l2c.total_refs 2447812 # Total number of references to valid blocks. +system.l2c.sampled_refs 401203 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.101181 # Average number of references to valid blocks. +system.l2c.warmup_cycle 5933228000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 55666.496606 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 4774.109125 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 4870.586047 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.849403 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.072847 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.074319 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.996570 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 915368 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 814896 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1730264 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835591 # number of Writeback hits +system.l2c.Writeback_hits::total 835591 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 6 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 6 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 185878 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 185878 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 913599 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 982740 # number of demand (read+write) hits -system.l2c.demand_hits::total 1896339 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 913599 # number of overall hits -system.l2c.overall_hits::cpu.data 982740 # number of overall hits -system.l2c.overall_hits::total 1896339 # number of overall hits -system.l2c.ReadReq_misses::cpu.inst 14735 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 289403 # number of ReadReq misses -system.l2c.ReadReq_misses::total 304138 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu.data 187658 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 187658 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 915368 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1002554 # number of demand (read+write) hits +system.l2c.demand_hits::total 1917922 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.inst 915368 # number of overall hits +system.l2c.overall_hits::cpu.data 1002554 # number of overall hits +system.l2c.overall_hits::total 1917922 # number of overall hits +system.l2c.ReadReq_misses::cpu.inst 13289 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 271916 # number of ReadReq misses +system.l2c.ReadReq_misses::total 285205 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 7 # 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Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1750545944000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.340325 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.083770 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.083770 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1750543570000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.340010 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.083751 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.083751 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -225,14 +225,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 19940998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 19940998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5722300806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5722300806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5742241804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5742241804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5742241804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5742241804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 19939998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 19939998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5720017806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5720017806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5739957804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5739957804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5739957804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5739957804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -249,19 +249,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115265.884393 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 115265.884393 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137714.208847 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 137714.208847 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 137621.133709 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 137621.133709 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64604060 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115260.104046 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 115260.104046 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137659.265643 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137659.265643 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137566.394344 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137566.394344 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137566.394344 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137566.394344 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 64633068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6166.863307 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6169.632302 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -275,14 +275,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10944998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 10944998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561447990 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3561447990 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3572392988 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3572392988 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3572392988 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3572392988 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10943998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 10943998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3559163998 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3559163998 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3570107996 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3570107996 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3570107996 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3570107996 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -291,14 +291,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63265.884393 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 63265.884393 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85710.627407 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 85710.627407 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 85617.567118 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 85617.567118 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63260.104046 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 63260.104046 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85655.660329 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85655.660329 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85562.803978 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85562.803978 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85562.803978 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85562.803978 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -316,22 +316,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9057511 # DTB read hits -system.cpu.dtb.read_misses 10312 # DTB read misses +system.cpu.dtb.read_hits 9064877 # DTB read hits +system.cpu.dtb.read_misses 10317 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728817 # DTB read accesses -system.cpu.dtb.write_hits 6352446 # DTB write hits +system.cpu.dtb.read_accesses 728824 # DTB read accesses +system.cpu.dtb.write_hits 6356219 # DTB write hits system.cpu.dtb.write_misses 1140 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291929 # DTB write accesses -system.cpu.dtb.data_hits 15409957 # DTB hits -system.cpu.dtb.data_misses 11452 # DTB misses +system.cpu.dtb.data_hits 15421096 # DTB hits +system.cpu.dtb.data_misses 11457 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020746 # DTB accesses -system.cpu.itb.fetch_hits 4973520 # ITB hits +system.cpu.dtb.data_accesses 1020753 # DTB accesses +system.cpu.itb.fetch_hits 4974034 # ITB hits system.cpu.itb.fetch_misses 4997 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4978517 # ITB accesses +system.cpu.itb.fetch_accesses 4979031 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -344,51 +344,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3831097734 # number of cpu cycles simulated +system.cpu.numCycles 3830985638 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56137087 # Number of instructions committed -system.cpu.committedOps 56137087 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52011214 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324192 # Number of float alu accesses -system.cpu.num_func_calls 1482242 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6464616 # number of instructions that are conditional controls -system.cpu.num_int_insts 52011214 # number of integer instructions -system.cpu.num_fp_insts 324192 # number of float instructions -system.cpu.num_int_register_reads 71259077 # number of times the integer registers were read -system.cpu.num_int_register_writes 38485860 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163510 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166384 # number of times the floating registers were written -system.cpu.num_mem_refs 15462519 # number of memory refs -system.cpu.num_load_insts 9094324 # Number of load instructions -system.cpu.num_store_insts 6368195 # Number of store instructions -system.cpu.num_idle_cycles 3587943187.998127 # Number of idle cycles -system.cpu.num_busy_cycles 243154546.001873 # Number of busy cycles -system.cpu.not_idle_fraction 0.063469 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.936531 # Percentage of idle cycles +system.cpu.committedInsts 56182681 # Number of instructions committed +system.cpu.committedOps 56182681 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52054721 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses +system.cpu.num_func_calls 1483282 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6468098 # number of instructions that are conditional controls +system.cpu.num_int_insts 52054721 # number of integer instructions +system.cpu.num_fp_insts 324259 # number of float instructions +system.cpu.num_int_register_reads 71321767 # number of times the integer registers were read +system.cpu.num_int_register_writes 38521612 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written +system.cpu.num_mem_refs 15473677 # number of memory refs +system.cpu.num_load_insts 9101706 # Number of load instructions +system.cpu.num_store_insts 6371971 # Number of store instructions +system.cpu.num_idle_cycles 3589415321.998127 # Number of idle cycles +system.cpu.num_busy_cycles 241570316.001874 # Number of busy cycles +system.cpu.not_idle_fraction 0.063057 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.936943 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211932 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74887 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211976 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74903 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1931 1.05% 42.02% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106197 57.98% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183146 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73520 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 106219 57.98% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183184 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73536 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1931 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73520 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149102 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857816228500 96.99% 96.99% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 79988500 0.00% 96.99% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 554693000 0.03% 97.02% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 57097199000 2.98% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1915548109000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981746 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73536 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149134 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1857766748000 96.99% 96.99% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 79985500 0.00% 96.99% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 554565500 0.03% 97.02% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 57090762000 2.98% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1915492061000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981750 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692298 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814116 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692306 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814121 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -424,33 +424,33 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4173 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175927 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::swpipl 175965 91.22% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192868 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2092 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1906 -system.cpu.kern.mode_good::user 1738 -system.cpu.kern.mode_good::idle 168 -system.cpu.kern.mode_switch_good::kernel 0.322887 # fraction of useful protection mode switches +system.cpu.kern.callpal::total 192907 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5900 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1740 +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.323559 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080306 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.391657 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 45253274000 2.36% 2.36% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5124228000 0.27% 2.63% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1865170605000 97.37% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4174 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392153 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 45078055000 2.35% 2.35% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5087693000 0.27% 2.62% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1865326311000 97.38% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -482,51 +482,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 927683 # number of replacements -system.cpu.icache.tagsinuse 508.721464 # Cycle average of tags in use -system.cpu.icache.total_refs 55220553 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 928194 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.492469 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 36307428000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 508.721464 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.993597 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.993597 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55220553 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55220553 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55220553 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55220553 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55220553 # number of overall hits -system.cpu.icache.overall_hits::total 55220553 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928354 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928354 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928354 # 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Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.993627 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.993627 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55265829 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55265829 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55265829 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55265829 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55265829 # number of overall hits +system.cpu.icache.overall_hits::total 55265829 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 928677 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 928677 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 928677 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 928677 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 928677 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14601.591834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14601.591834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14601.591834 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -537,104 +537,104 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 85 # number of writebacks system.cpu.icache.writebacks::total 85 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928354 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 928354 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 928354 # 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miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049461 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049461 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086449 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086449 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091356 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091356 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091356 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091356 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24679.631657 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24679.631657 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30092.869598 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30092.869598 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14157.703195 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14157.703195 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25879.289114 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25879.289114 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25879.289114 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25879.289114 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -643,54 +643,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31437471000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31437471000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 862763000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 862763000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1199607500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1199607500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2062370500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 2062370500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120441 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120441 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049462 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049462 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085908 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085908 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091383 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091383 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22368.647754 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22368.647754 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27323.439631 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27323.439631 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11300.331376 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11300.331376 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23466.555996 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23466.555996 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1199604500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1199604500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2062367500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 2062367500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120390 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120390 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049461 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049461 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086449 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086449 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091356 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091356 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091356 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091356 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21679.589583 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21679.589583 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27092.869598 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27092.869598 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11157.703195 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11157.703195 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22879.256364 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22879.256364 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22879.256364 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22879.256364 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |