diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
| commit | c4e91289ae8806eb051fb1f41ece8be308f0ff85 (patch) | |
| tree | 6f35a7725cfd4072c8516ee0bb2ae799d48ce896 /tests/quick/fs/10.linux-boot/ref/alpha | |
| parent | cc6523e2d686447f90acccac20c0fb2940dc3e3b (diff) | |
| download | gem5-c4e91289ae8806eb051fb1f41ece8be308f0ff85.tar.xz | |
stats: Bump stats for filter, crossbar and config changes
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha')
4 files changed, 3042 insertions, 2816 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 87d1939f2..973b187d4 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,188 +1,221 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.870335 # Number of seconds simulated -sim_ticks 1870335131500 # Number of ticks simulated -final_tick 1870335131500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.869358 # Number of seconds simulated +sim_ticks 1869357988000 # Number of ticks simulated +final_tick 1869357988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1824221 # Simulator instruction rate (inst/s) -host_op_rate 1824220 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54024573563 # Simulator tick rate (ticks/s) -host_mem_usage 318368 # Number of bytes of host memory used -host_seconds 34.62 # Real time elapsed on the host -sim_insts 63154606 # Number of instructions simulated -sim_ops 63154606 # Number of ops (including micro ops) simulated +host_inst_rate 2868261 # Simulator instruction rate (inst/s) +host_op_rate 2868259 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 82489350498 # Simulator tick rate (ticks/s) +host_mem_usage 370556 # Number of bytes of host memory used +host_seconds 22.66 # Real time elapsed on the host +sim_insts 64999904 # Number of instructions simulated +sim_ops 64999904 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 761088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 66705472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 765760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 66552064 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 674112 # Number of bytes read from this memory -system.physmem.bytes_read::total 68252608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 761088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 872064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5204096 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 106560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 771648 # Number of bytes read from this memory +system.physmem.bytes_read::total 68196992 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 765760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 106560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 872320 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5174080 # Number of bytes written to this memory system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7863424 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11892 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1042273 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7833408 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11965 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1039876 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10533 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1066447 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 81314 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1665 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 12057 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1065578 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 80845 # Number of write requests responded to by this memory system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122866 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 406926 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35664984 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 360423 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36492181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 406926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466261 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2782440 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1421846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4204286 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2782440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 406926 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35664984 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1422359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 360423 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40696467 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 40739369 # Throughput (bytes/s) -system.membus.data_through_bus 76196274 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.physmem.num_writes::total 122397 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 409638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35601562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 57004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 412788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36481505 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 409638 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 57004 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 466641 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2767838 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1422589 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4190427 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2767838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 409638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35601562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1423102 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 57004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 412788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40671931 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 948901 # Transaction distribution +system.membus.trans_dist::ReadResp 948901 # Transaction distribution +system.membus.trans_dist::WriteReq 14588 # Transaction distribution +system.membus.trans_dist::WriteResp 14588 # Transaction distribution +system.membus.trans_dist::Writeback 80845 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 19618 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 14179 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8160 # Transaction distribution +system.membus.trans_dist::ReadExReq 126515 # Transaction distribution +system.membus.trans_dist::ReadExResp 124290 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2256153 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 2300227 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2383689 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73370112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 73456274 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2670784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2670784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 76127058 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1224161 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 1224161 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 1224161 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 1000624 # number of replacements -system.l2c.tags.tagsinuse 65381.923240 # Cycle average of tags in use -system.l2c.tags.total_refs 2464778 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1065766 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.312682 # Average number of references to valid blocks. +system.l2c.tags.replacements 999765 # number of replacements +system.l2c.tags.tagsinuse 65320.982867 # Cycle average of tags in use +system.l2c.tags.total_refs 2387620 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1064815 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.242286 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 56158.686870 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4894.230886 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4134.623273 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 174.423683 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 19.958527 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.997649 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65142 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 769 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 3264 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6912 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6213 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 47984 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.993988 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 32109770 # Number of tag accesses -system.l2c.tags.data_accesses 32109770 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 873092 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 763091 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 101902 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 36740 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1774825 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 816663 # number of Writeback hits -system.l2c.Writeback_hits::total 816663 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 172 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 166232 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 14288 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 180520 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 873092 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 929323 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 101902 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 51028 # number of demand (read+write) hits -system.l2c.demand_hits::total 1955345 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 873092 # number of overall hits -system.l2c.overall_hits::cpu0.data 929323 # number of overall hits -system.l2c.overall_hits::cpu1.inst 101902 # number of overall hits -system.l2c.overall_hits::cpu1.data 51028 # number of overall hits -system.l2c.overall_hits::total 1955345 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11892 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 908 # number of ReadReq misses -system.l2c.ReadReq_misses::total 941295 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 570 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3012 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 65 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 165 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 115706 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 9662 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 125368 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 11892 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 1042467 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1734 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10570 # number of demand (read+write) misses -system.l2c.demand_misses::total 1066663 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11892 # number of overall misses -system.l2c.overall_misses::cpu0.data 1042467 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1734 # number of overall misses -system.l2c.overall_misses::cpu1.data 10570 # number of overall misses -system.l2c.overall_misses::total 1066663 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.inst 884984 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1689852 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 103636 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 37648 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2716120 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 816663 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 816663 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 281938 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 23950 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 305888 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 884984 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1971790 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 103636 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 61598 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3022008 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 884984 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1971790 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 103636 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 61598 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3022008 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.013438 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.548427 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.016732 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024118 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.346559 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.410395 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.403424 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.409849 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.013438 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.528691 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.016732 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.171596 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.352965 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.013438 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.528691 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.016732 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.171596 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.352965 # miss rate for overall accesses +system.l2c.tags.occ_blocks::writebacks 56016.884833 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4834.504330 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4176.028554 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 178.991920 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 114.573230 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.854750 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073769 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.063721 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002731 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.001748 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65050 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 768 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 3271 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 6128 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5934 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 48949 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 31465722 # Number of tag accesses +system.l2c.tags.data_accesses 31465722 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 606953 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 626726 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 379523 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 129013 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1742215 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 777631 # number of Writeback hits +system.l2c.Writeback_hits::total 777631 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 577 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 693 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 13 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 50 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 111430 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 168033 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 606953 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 738156 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 379523 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits +system.l2c.demand_hits::total 1910248 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 606953 # number of overall hits +system.l2c.overall_hits::cpu0.data 738156 # number of overall hits +system.l2c.overall_hits::cpu1.inst 379523 # number of overall hits +system.l2c.overall_hits::cpu1.data 185616 # number of overall hits +system.l2c.overall_hits::total 1910248 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 11965 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 926610 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1665 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1033 # number of ReadReq misses +system.l2c.ReadReq_misses::total 941273 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2175 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 5181 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 1175 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1110 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2285 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 113916 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 11068 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 124984 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 11965 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 1040526 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1665 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 12101 # number of demand (read+write) misses +system.l2c.demand_misses::total 1066257 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11965 # number of overall misses +system.l2c.overall_misses::cpu0.data 1040526 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1665 # number of overall misses +system.l2c.overall_misses::cpu1.data 12101 # number of overall misses +system.l2c.overall_misses::total 1066257 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.inst 618918 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1553336 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 381188 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 130046 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2683488 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 777631 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 777631 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 2752 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5874 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 1212 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1123 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2335 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 225346 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 67671 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 293017 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 618918 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1778682 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 381188 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 197717 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2976505 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 618918 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1778682 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 381188 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 197717 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2976505 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.019332 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.596529 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.004368 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.350765 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.962844 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.790334 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.882022 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.969472 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.988424 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.978587 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.505516 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.163556 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.426542 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.019332 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.584998 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004368 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.061204 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.358224 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.019332 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.584998 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004368 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.061204 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.358224 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -191,39 +224,39 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 81314 # number of writebacks -system.l2c.writebacks::total 81314 # number of writebacks +system.l2c.writebacks::writebacks 80845 # number of writebacks +system.l2c.writebacks::total 80845 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.435433 # Cycle average of tags in use +system.iocache.tags.replacements 41699 # number of replacements +system.iocache.tags.tagsinuse 0.434096 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.435433 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.027215 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1685787163517 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.434096 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375543 # Number of tag accesses -system.iocache.tags.data_accesses 375543 # Number of data accesses +system.iocache.tags.tag_accesses 375579 # Number of tag accesses +system.iocache.tags.data_accesses 375579 # Number of data accesses system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses -system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses -system.iocache.demand_misses::total 175 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 175 # number of overall misses -system.iocache.overall_misses::total 175 # number of overall misses -system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses +system.iocache.ReadReq_misses::total 179 # number of ReadReq misses +system.iocache.demand_misses::tsunami.ide 179 # number of demand (read+write) misses +system.iocache.demand_misses::total 179 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 179 # number of overall misses +system.iocache.overall_misses::total 179 # number of overall misses +system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 179 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 179 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 179 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 179 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses @@ -255,22 +288,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9154569 # DTB read hits -system.cpu0.dtb.read_misses 7079 # DTB read misses +system.cpu0.dtb.read_hits 7758808 # DTB read hits +system.cpu0.dtb.read_misses 7155 # DTB read misses system.cpu0.dtb.read_acv 152 # DTB read access violations -system.cpu0.dtb.read_accesses 508987 # DTB read accesses -system.cpu0.dtb.write_hits 5936918 # DTB write hits -system.cpu0.dtb.write_misses 726 # DTB write misses -system.cpu0.dtb.write_acv 99 # DTB write access violations -system.cpu0.dtb.write_accesses 189050 # DTB write accesses -system.cpu0.dtb.data_hits 15091487 # DTB hits -system.cpu0.dtb.data_misses 7805 # DTB misses -system.cpu0.dtb.data_acv 251 # DTB access violations -system.cpu0.dtb.data_accesses 698037 # DTB accesses -system.cpu0.itb.fetch_hits 3855534 # ITB hits -system.cpu0.itb.fetch_misses 3485 # ITB misses +system.cpu0.dtb.read_accesses 531148 # DTB read accesses +system.cpu0.dtb.write_hits 4740251 # DTB write hits +system.cpu0.dtb.write_misses 732 # DTB write misses +system.cpu0.dtb.write_acv 102 # DTB write access violations +system.cpu0.dtb.write_accesses 201714 # DTB write accesses +system.cpu0.dtb.data_hits 12499059 # DTB hits +system.cpu0.dtb.data_misses 7887 # DTB misses +system.cpu0.dtb.data_acv 254 # DTB access violations +system.cpu0.dtb.data_accesses 732862 # DTB accesses +system.cpu0.itb.fetch_hits 3525726 # ITB hits +system.cpu0.itb.fetch_misses 3572 # ITB misses system.cpu0.itb.fetch_acv 127 # ITB acv -system.cpu0.itb.fetch_accesses 3859019 # ITB accesses +system.cpu0.itb.fetch_accesses 3529298 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -283,154 +316,154 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3740670264 # number of cpu cycles simulated +system.cpu0.numCycles 3738722771 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 57222643 # Number of instructions committed -system.cpu0.committedOps 57222643 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 53250480 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses -system.cpu0.num_func_calls 1399593 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6808341 # number of instructions that are conditional controls -system.cpu0.num_int_insts 53250480 # number of integer instructions -system.cpu0.num_fp_insts 299810 # number of float instructions -system.cpu0.num_int_register_reads 73319539 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39827957 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written -system.cpu0.num_mem_refs 15135573 # number of memory refs -system.cpu0.num_load_insts 9184516 # Number of load instructions -system.cpu0.num_store_insts 5951057 # Number of store instructions -system.cpu0.num_idle_cycles 3683435851.584730 # Number of idle cycles -system.cpu0.num_busy_cycles 57234412.415270 # Number of busy cycles -system.cpu0.not_idle_fraction 0.015301 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.984699 # Percentage of idle cycles -system.cpu0.Branches 8650822 # Number of branches fetched -system.cpu0.op_class::No_OpClass 3102524 5.42% 5.42% # Class of executed instruction -system.cpu0.op_class::IntAlu 37811313 66.07% 71.49% # Class of executed instruction -system.cpu0.op_class::IntMult 59497 0.10% 71.59% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.59% # Class of executed instruction -system.cpu0.op_class::FloatAdd 30844 0.05% 71.65% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::FloatDiv 2221 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::MemRead 9401091 16.43% 88.08% # Class of executed instruction -system.cpu0.op_class::MemWrite 5957003 10.41% 98.49% # Class of executed instruction -system.cpu0.op_class::IprAccess 866206 1.51% 100.00% # Class of executed instruction +system.cpu0.committedInsts 49477745 # Number of instructions committed +system.cpu0.committedOps 49477745 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 46201705 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses +system.cpu0.num_func_calls 1124633 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6043603 # number of instructions that are conditional controls +system.cpu0.num_int_insts 46201705 # number of integer instructions +system.cpu0.num_fp_insts 197598 # number of float instructions +system.cpu0.num_int_register_reads 64003225 # number of times the integer registers were read +system.cpu0.num_int_register_writes 34834421 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written +system.cpu0.num_mem_refs 12536107 # number of memory refs +system.cpu0.num_load_insts 7783754 # Number of load instructions +system.cpu0.num_store_insts 4752353 # Number of store instructions +system.cpu0.num_idle_cycles 3689239788.666409 # Number of idle cycles +system.cpu0.num_busy_cycles 49482982.333591 # Number of busy cycles +system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles +system.cpu0.Branches 7530826 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2589816 5.23% 5.23% # Class of executed instruction +system.cpu0.op_class::IntAlu 33436017 67.57% 72.80% # Class of executed instruction +system.cpu0.op_class::IntMult 50540 0.10% 72.90% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction +system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatDiv 2233 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::MemRead 7945590 16.06% 89.02% # Class of executed instruction +system.cpu0.op_class::MemWrite 4758292 9.62% 98.63% # Class of executed instruction +system.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 57230699 # Class of executed instruction +system.cpu0.op_class::total 49485886 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 197118 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 101703 58.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 174866 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1852989089000 99.07% 99.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 17242731500 0.92% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1870334924000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 150435 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 51398 40.00% 40.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 243 0.19% 40.19% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1907 1.48% 41.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 514 0.40% 42.07% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 74446 57.93% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 128508 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 51050 48.97% 48.97% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 243 0.23% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1853222721000 99.14% 99.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 15975327000 0.85% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1869357780500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684631 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808762 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed -system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed -system.cpu0.kern.syscall::6 32 14.16% 26.11% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.44% 26.55% # number of syscalls executed -system.cpu0.kern.syscall::15 1 0.44% 26.99% # number of syscalls executed -system.cpu0.kern.syscall::17 9 3.98% 30.97% # number of syscalls executed -system.cpu0.kern.syscall::19 8 3.54% 34.51% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.65% 37.17% # number of syscalls executed -system.cpu0.kern.syscall::23 2 0.88% 38.05% # number of syscalls executed -system.cpu0.kern.syscall::24 4 1.77% 39.82% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.10% 42.92% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.88% 43.81% # number of syscalls executed -system.cpu0.kern.syscall::45 37 16.37% 60.18% # number of syscalls executed -system.cpu0.kern.syscall::47 4 1.77% 61.95% # number of syscalls executed -system.cpu0.kern.syscall::48 8 3.54% 65.49% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.42% 69.91% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.44% 70.35% # number of syscalls executed -system.cpu0.kern.syscall::59 4 1.77% 72.12% # number of syscalls executed -system.cpu0.kern.syscall::71 30 13.27% 85.40% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.33% 86.73% # number of syscalls executed -system.cpu0.kern.syscall::74 8 3.54% 90.27% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.44% 90.71% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.88% 91.59% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.98% 95.58% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.88% 96.46% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.88% 97.35% # number of syscalls executed -system.cpu0.kern.syscall::132 2 0.88% 98.23% # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.678828 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811234 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 6 2.63% 2.63% # number of syscalls executed +system.cpu0.kern.syscall::3 20 8.77% 11.40% # number of syscalls executed +system.cpu0.kern.syscall::4 2 0.88% 12.28% # number of syscalls executed +system.cpu0.kern.syscall::6 32 14.04% 26.32% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.44% 26.75% # number of syscalls executed +system.cpu0.kern.syscall::15 1 0.44% 27.19% # number of syscalls executed +system.cpu0.kern.syscall::17 9 3.95% 31.14% # number of syscalls executed +system.cpu0.kern.syscall::19 8 3.51% 34.65% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.63% 37.28% # number of syscalls executed +system.cpu0.kern.syscall::23 2 0.88% 38.16% # number of syscalls executed +system.cpu0.kern.syscall::24 4 1.75% 39.91% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.07% 42.98% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.88% 43.86% # number of syscalls executed +system.cpu0.kern.syscall::45 37 16.23% 60.09% # number of syscalls executed +system.cpu0.kern.syscall::47 4 1.75% 61.84% # number of syscalls executed +system.cpu0.kern.syscall::48 8 3.51% 65.35% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.39% 69.74% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.44% 70.18% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.19% 72.37% # number of syscalls executed +system.cpu0.kern.syscall::71 30 13.16% 85.53% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.32% 86.84% # number of syscalls executed +system.cpu0.kern.syscall::74 8 3.51% 90.35% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.44% 90.79% # number of syscalls executed +system.cpu0.kern.syscall::90 2 0.88% 91.67% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.95% 95.61% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.88% 96.49% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.88% 97.37% # number of syscalls executed +system.cpu0.kern.syscall::132 2 0.88% 98.25% # number of syscalls executed system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 226 # number of syscalls executed +system.cpu0.kern.syscall::total 228 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 110 0.06% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed -system.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal::swpipl 168033 91.68% 93.82% # number of callpals executed -system.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.00% 97.18% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed -system.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 183289 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1156 # number of protection mode switches +system.cpu0.kern.callpal::wripir 616 0.45% 0.45% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.46% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.46% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2743 2.02% 2.47% # number of callpals executed +system.cpu0.kern.callpal::tbi 39 0.03% 2.50% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed +system.cpu0.kern.callpal::swpipl 121668 89.51% 92.02% # number of callpals executed +system.cpu0.kern.callpal::rdps 6149 4.52% 96.54% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.54% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.54% # number of callpals executed +system.cpu0.kern.callpal::rdusp 7 0.01% 96.55% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.55% # number of callpals executed +system.cpu0.kern.callpal::rti 4175 3.07% 99.62% # number of callpals executed +system.cpu0.kern.callpal::callsys 369 0.27% 99.89% # number of callpals executed +system.cpu0.kern.callpal::imb 146 0.11% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 135929 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6593 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1173 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1155 -system.cpu0.kern.mode_good::user 1156 +system.cpu0.kern.mode_good::kernel 1172 +system.cpu0.kern.mode_good::user 1173 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.162883 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.177764 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.280223 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1869377924000 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 956999000 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.301957 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1868349152500 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1008627000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3763 # number of times the context was actually changed +system.cpu0.kern.swap_context 2744 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -462,51 +495,117 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 133353257 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 246745714 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 2669568 # Total snoop data (bytes) -system.iobus.throughput 1460501 # Throughput (bytes/s) -system.iobus.data_through_bus 2731626 # Total data (bytes) -system.cpu0.icache.tags.replacements 884408 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.244752 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 56345695 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 884920 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 63.673208 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.244752 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998525 # Average percentage of cache occupancy +system.toL2Bus.trans_dist::ReadReq 2732156 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2732156 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 777631 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 19617 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 14229 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 33846 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295242 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295242 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1237878 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4301883 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 762376 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 627158 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6929295 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39612096 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155765243 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24396032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357911 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 243131282 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 41895 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3873157 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.010774 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.103239 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3831426 98.92% 98.92% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41731 1.08% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3873157 # Request fanout histogram +system.iobus.trans_dist::ReadReq 7628 # Transaction distribution +system.iobus.trans_dist::ReadResp 7628 # Transaction distribution +system.iobus.trans_dist::WriteReq 56140 # Transaction distribution +system.iobus.trans_dist::WriteResp 14588 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14686 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18036 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 44074 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 127536 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 58744 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9018 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 86162 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2747818 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.icache.tags.replacements 618292 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 618804 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 78.969992 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 9786048500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.240644 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998517 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 345 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 58115703 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 58115703 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 56345695 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 56345695 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 56345695 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 56345695 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 56345695 # number of overall hits -system.cpu0.icache.overall_hits::total 56345695 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 885004 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 885004 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 885004 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 885004 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 885004 # number of overall misses -system.cpu0.icache.overall_misses::total 885004 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230699 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 57230699 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 57230699 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 57230699 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 57230699 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 57230699 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.015464 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.015464 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 50104825 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 50104825 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 48866947 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 48866947 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 48866947 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 48866947 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 48866947 # number of overall hits +system.cpu0.icache.overall_hits::total 48866947 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 618939 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 618939 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 618939 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 618939 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 618939 # number of overall misses +system.cpu0.icache.overall_misses::total 618939 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 49485886 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 49485886 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 49485886 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 49485886 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 49485886 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 49485886 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012507 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.012507 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012507 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.012507 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012507 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.012507 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -516,70 +615,70 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1978697 # number of replacements -system.cpu0.dcache.tags.tagsinuse 507.129647 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13123800 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1979209 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 6.630831 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1781371 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.187328 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10705763 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1781883 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 6.008118 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.129647 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.990488 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187328 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 446 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 62404315 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 62404315 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 7298365 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7298365 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5462282 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5462282 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186624 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 186624 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12760647 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12760647 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12760647 # number of overall hits -system.cpu0.dcache.overall_hits::total 12760647 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1683343 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1683343 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 285998 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 285998 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 714 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1969341 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1969341 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1969341 # number of overall misses -system.cpu0.dcache.overall_misses::total 1969341 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981708 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8981708 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748280 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5748280 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14729988 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14729988 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14729988 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14729988 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187419 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.187419 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049754 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085785 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085785 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003811 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003811 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133696 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.133696 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133696 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.133696 # miss rate for overall accesses +system.cpu0.dcache.tags.tag_accesses 51822042 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51822042 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6068881 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6068881 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4360082 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4360082 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127592 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 127592 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132846 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 132846 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10428963 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10428963 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10428963 # number of overall hits +system.cpu0.dcache.overall_hits::total 10428963 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1560069 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1560069 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 236541 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 236541 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12626 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 12626 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6924 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 6924 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1796610 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1796610 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1796610 # number of overall misses +system.cpu0.dcache.overall_misses::total 1796610 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628950 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7628950 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596623 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4596623 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 140218 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 140218 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 139770 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 139770 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12225573 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12225573 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12225573 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12225573 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204493 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.204493 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051460 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051460 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090046 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090046 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049539 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049539 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.146955 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.146955 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.146955 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.146955 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -588,29 +687,29 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 775643 # number of writebacks -system.cpu0.dcache.writebacks::total 775643 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 633103 # number of writebacks +system.cpu0.dcache.writebacks::total 633103 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1163439 # DTB read hits -system.cpu1.dtb.read_misses 3277 # DTB read misses +system.cpu1.dtb.read_hits 2831559 # DTB read hits +system.cpu1.dtb.read_misses 3191 # DTB read misses system.cpu1.dtb.read_acv 58 # DTB read access violations -system.cpu1.dtb.read_accesses 220342 # DTB read accesses -system.cpu1.dtb.write_hits 751446 # DTB write hits -system.cpu1.dtb.write_misses 415 # DTB write misses -system.cpu1.dtb.write_acv 58 # DTB write access violations -system.cpu1.dtb.write_accesses 103280 # DTB write accesses -system.cpu1.dtb.data_hits 1914885 # DTB hits -system.cpu1.dtb.data_misses 3692 # DTB misses -system.cpu1.dtb.data_acv 116 # DTB access violations -system.cpu1.dtb.data_accesses 323622 # DTB accesses -system.cpu1.itb.fetch_hits 1468399 # ITB hits -system.cpu1.itb.fetch_misses 1539 # ITB misses +system.cpu1.dtb.read_accesses 198160 # DTB read accesses +system.cpu1.dtb.write_hits 2101673 # DTB write hits +system.cpu1.dtb.write_misses 412 # DTB write misses +system.cpu1.dtb.write_acv 55 # DTB write access violations +system.cpu1.dtb.write_accesses 90619 # DTB write accesses +system.cpu1.dtb.data_hits 4933232 # DTB hits +system.cpu1.dtb.data_misses 3603 # DTB misses +system.cpu1.dtb.data_acv 113 # DTB access violations +system.cpu1.dtb.data_accesses 288779 # DTB accesses +system.cpu1.itb.fetch_hits 1950883 # ITB hits +system.cpu1.itb.fetch_misses 1451 # ITB misses system.cpu1.itb.fetch_acv 57 # ITB acv -system.cpu1.itb.fetch_accesses 1469938 # ITB accesses +system.cpu1.itb.fetch_accesses 1952334 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -623,175 +722,176 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3740248099 # number of cpu cycles simulated +system.cpu1.numCycles 3738296587 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5931963 # Number of instructions committed -system.cpu1.committedOps 5931963 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 5550581 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses -system.cpu1.num_func_calls 182742 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 577192 # number of instructions that are conditional controls -system.cpu1.num_int_insts 5550581 # number of integer instructions -system.cpu1.num_fp_insts 28590 # number of float instructions -system.cpu1.num_int_register_reads 7657293 # number of times the integer registers were read -system.cpu1.num_int_register_writes 4163277 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written -system.cpu1.num_mem_refs 1926244 # number of memory refs -system.cpu1.num_load_insts 1170888 # Number of load instructions -system.cpu1.num_store_insts 755356 # Number of store instructions -system.cpu1.num_idle_cycles 3734311403.078359 # Number of idle cycles -system.cpu1.num_busy_cycles 5936695.921641 # Number of busy cycles -system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles -system.cpu1.Branches 836749 # Number of branches fetched -system.cpu1.op_class::No_OpClass 239814 4.04% 4.04% # Class of executed instruction -system.cpu1.op_class::IntAlu 3533248 59.52% 63.56% # Class of executed instruction -system.cpu1.op_class::IntMult 9651 0.16% 63.73% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 63.73% # Class of executed instruction -system.cpu1.op_class::FloatAdd 7388 0.12% 63.85% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 63.85% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 63.85% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 63.85% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1421 0.02% 63.88% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::MemRead 1191429 20.07% 83.95% # Class of executed instruction -system.cpu1.op_class::MemWrite 755540 12.73% 96.68% # Class of executed instruction -system.cpu1.op_class::IprAccess 197280 3.32% 100.00% # Class of executed instruction +system.cpu1.committedInsts 15522159 # Number of instructions committed +system.cpu1.committedOps 15522159 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 14295544 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses +system.cpu1.num_func_calls 493140 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1540068 # number of instructions that are conditional controls +system.cpu1.num_int_insts 14295544 # number of integer instructions +system.cpu1.num_fp_insts 198941 # number of float instructions +system.cpu1.num_int_register_reads 19514289 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10457600 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written +system.cpu1.num_mem_refs 4961786 # number of memory refs +system.cpu1.num_load_insts 2849090 # Number of load instructions +system.cpu1.num_store_insts 2112696 # Number of store instructions +system.cpu1.num_idle_cycles 3722773649.474793 # Number of idle cycles +system.cpu1.num_busy_cycles 15522937.525207 # Number of busy cycles +system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles +system.cpu1.Branches 2214163 # Number of branches fetched +system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction +system.cpu1.op_class::IntAlu 9156766 58.98% 64.49% # Class of executed instruction +system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction +system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::MemRead 2937016 18.92% 83.66% # Class of executed instruction +system.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction +system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 5935771 # Class of executed instruction +system.cpu1.op_class::total 15525875 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2205 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1859122617500 99.41% 99.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1870124036000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 92290 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 31964 39.34% 39.34% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1906 2.35% 41.68% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 616 0.76% 42.44% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 46769 57.56% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 81255 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 30935 48.51% 48.51% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1856123490500 99.30% 99.30% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 12870743500 0.69% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1869146928500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed -system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed -system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed -system.cpu1.kern.syscall::6 10 10.00% 25.00% # number of syscalls executed -system.cpu1.kern.syscall::17 6 6.00% 31.00% # number of syscalls executed -system.cpu1.kern.syscall::19 2 2.00% 33.00% # number of syscalls executed -system.cpu1.kern.syscall::23 2 2.00% 35.00% # number of syscalls executed -system.cpu1.kern.syscall::24 2 2.00% 37.00% # number of syscalls executed -system.cpu1.kern.syscall::33 4 4.00% 41.00% # number of syscalls executed -system.cpu1.kern.syscall::45 17 17.00% 58.00% # number of syscalls executed -system.cpu1.kern.syscall::47 2 2.00% 60.00% # number of syscalls executed -system.cpu1.kern.syscall::48 2 2.00% 62.00% # number of syscalls executed -system.cpu1.kern.syscall::59 3 3.00% 65.00% # number of syscalls executed -system.cpu1.kern.syscall::71 24 24.00% 89.00% # number of syscalls executed -system.cpu1.kern.syscall::74 8 8.00% 97.00% # number of syscalls executed -system.cpu1.kern.syscall::90 1 1.00% 98.00% # number of syscalls executed -system.cpu1.kern.syscall::132 2 2.00% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 100 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.648271 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.784887 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 2 2.04% 2.04% # number of syscalls executed +system.cpu1.kern.syscall::3 10 10.20% 12.24% # number of syscalls executed +system.cpu1.kern.syscall::4 2 2.04% 14.29% # number of syscalls executed +system.cpu1.kern.syscall::6 10 10.20% 24.49% # number of syscalls executed +system.cpu1.kern.syscall::17 6 6.12% 30.61% # number of syscalls executed +system.cpu1.kern.syscall::19 2 2.04% 32.65% # number of syscalls executed +system.cpu1.kern.syscall::23 2 2.04% 34.69% # number of syscalls executed +system.cpu1.kern.syscall::24 2 2.04% 36.73% # number of syscalls executed +system.cpu1.kern.syscall::33 4 4.08% 40.82% # number of syscalls executed +system.cpu1.kern.syscall::45 17 17.35% 58.16% # number of syscalls executed +system.cpu1.kern.syscall::47 2 2.04% 60.20% # number of syscalls executed +system.cpu1.kern.syscall::48 2 2.04% 62.24% # number of syscalls executed +system.cpu1.kern.syscall::59 2 2.04% 64.29% # number of syscalls executed +system.cpu1.kern.syscall::71 24 24.49% 88.78% # number of syscalls executed +system.cpu1.kern.syscall::74 8 8.16% 96.94% # number of syscalls executed +system.cpu1.kern.syscall::90 1 1.02% 97.96% # number of syscalls executed +system.cpu1.kern.syscall::132 2 2.04% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 98 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 470 1.46% 1.50% # number of callpals executed -system.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed -system.cpu1.kern.callpal::swpipl 26238 81.66% 83.22% # number of callpals executed -system.cpu1.kern.callpal::rdps 2576 8.02% 91.24% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.25% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 91.26% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.01% 91.26% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.27% # number of callpals executed -system.cpu1.kern.callpal::rti 2607 8.11% 99.39% # number of callpals executed -system.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed -system.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 514 0.61% 0.61% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2506 2.96% 3.58% # number of callpals executed +system.cpu1.kern.callpal::tbi 14 0.02% 3.59% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.60% # number of callpals executed +system.cpu1.kern.callpal::swpipl 74617 88.26% 91.86% # number of callpals executed +system.cpu1.kern.callpal::rdps 2575 3.05% 94.91% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.91% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.00% 94.91% # number of callpals executed +system.cpu1.kern.callpal::rdusp 2 0.00% 94.91% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.92% # number of callpals executed +system.cpu1.kern.callpal::rti 4115 4.87% 99.79% # number of callpals executed +system.cpu1.kern.callpal::callsys 146 0.17% 99.96% # number of callpals executed +system.cpu1.kern.callpal::imb 34 0.04% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 32131 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches -system.cpu1.kern.mode_switch::user 580 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 612 -system.cpu1.kern.mode_good::user 580 -system.cpu1.kern.mode_good::idle 32 -system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 84542 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2548 # number of protection mode switches +system.cpu1.kern.mode_switch::user 564 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 3056 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 1106 +system.cpu1.kern.mode_good::user 564 +system.cpu1.kern.mode_good::idle 542 +system.cpu1.kern.mode_switch_good::kernel 0.434066 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 1373909000 0.07% 0.07% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1868002186500 99.90% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 471 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 103097 # number of replacements -system.cpu1.icache.tags.tagsinuse 427.126315 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 5832135 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 103609 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 56.289849 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1868932699000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 427.126315 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.834231 # Average percentage of cache occupancy +system.cpu1.kern.mode_switch_good::idle 0.177356 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 5986368000 0.32% 0.32% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1862102404500 99.66% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2507 # number of times the context was actually changed +system.cpu1.icache.tags.replacements 380647 # number of replacements +system.cpu1.icache.tags.tagsinuse 453.133719 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 381159 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.733253 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1859777157500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133719 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 6039407 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 6039407 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 5832135 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5832135 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5832135 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5832135 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5832135 # number of overall hits -system.cpu1.icache.overall_hits::total 5832135 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 103636 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 103636 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 103636 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 103636 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 103636 # number of overall misses -system.cpu1.icache.overall_misses::total 103636 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935771 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5935771 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5935771 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5935771 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5935771 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5935771 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017460 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.017460 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017460 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.017460 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017460 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.017460 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 15907063 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 15907063 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 15144687 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 15144687 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 15144687 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 15144687 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 15144687 # number of overall hits +system.cpu1.icache.overall_hits::total 15144687 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 381188 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 381188 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 381188 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 381188 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 381188 # number of overall misses +system.cpu1.icache.overall_misses::total 381188 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 15525875 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 15525875 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 15525875 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 15525875 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 15525875 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 15525875 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024552 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024552 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024552 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024552 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024552 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024552 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -801,69 +901,69 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 62047 # number of replacements -system.cpu1.dcache.tags.tagsinuse 421.558473 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 1836050 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 62385 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.430953 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1851115162500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.558473 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823356 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.823356 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.660156 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 7735314 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 7735314 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1109520 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1109520 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 707454 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 707454 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1816974 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1816974 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1816974 # number of overall hits -system.cpu1.dcache.overall_hits::total 1816974 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 41445 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 41445 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 25851 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 25851 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 67296 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 67296 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 67296 # number of overall misses -system.cpu1.dcache.overall_misses::total 67296 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036009 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036009 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035253 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.035253 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035715 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.035715 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035715 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035715 # miss rate for overall accesses +system.cpu1.dcache.tags.replacements 201757 # number of replacements +system.cpu1.dcache.tags.tagsinuse 497.601960 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4718401 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 202065 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.350907 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601960 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971879 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.971879 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.601562 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 20020608 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 20020608 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2632688 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2632688 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1954642 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1954642 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 61098 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 61098 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 64210 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 64210 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 4587330 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 4587330 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 4587330 # number of overall hits +system.cpu1.dcache.overall_hits::total 4587330 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 140885 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 140885 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 78318 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 78318 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11000 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11000 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 7305 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 7305 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 219203 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 219203 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 219203 # number of overall misses +system.cpu1.dcache.overall_misses::total 219203 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2773573 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2773573 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2032960 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2032960 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72098 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 72098 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 71515 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 71515 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4806533 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4806533 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4806533 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4806533 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050795 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.050795 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.038524 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.038524 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152570 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152570 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102146 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.102146 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.045605 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.045605 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.045605 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.045605 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -872,8 +972,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 41020 # number of writebacks -system.cpu1.dcache.writebacks::total 41020 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 144528 # number of writebacks +system.cpu1.dcache.writebacks::total 144528 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 8a7bfd4c1..d02473de7 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,58 +1,90 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.829332 # Number of seconds simulated -sim_ticks 1829332049000 # Number of ticks simulated -final_tick 1829332049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1829331993500 # Number of ticks simulated +final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2314619 # Simulator instruction rate (inst/s) -host_op_rate 2314617 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 70524837278 # Simulator tick rate (ticks/s) -host_mem_usage 315304 # Number of bytes of host memory used -host_seconds 25.94 # Real time elapsed on the host -sim_insts 60038433 # Number of instructions simulated -sim_ops 60038433 # Number of ops (including micro ops) simulated +host_inst_rate 2920462 # Simulator instruction rate (inst/s) +host_op_rate 2920460 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 88984410684 # Simulator tick rate (ticks/s) +host_mem_usage 366200 # Number of bytes of host memory used +host_seconds 20.56 # Real time elapsed on the host +sim_insts 60038469 # Number of instructions simulated +sim_ops 60038469 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 66856384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66856000 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 67715328 # Number of bytes read from this memory +system.physmem.bytes_read::total 67714944 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4754240 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 4753856 # Number of bytes written to this memory system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7413568 # Number of bytes written to this memory +system.physmem.bytes_written::total 7413184 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1044631 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1044625 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1058052 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 74285 # Number of write requests responded to by this memory +system.physmem.num_reads::total 1058046 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 74279 # Number of write requests responded to by this memory system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115837 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115831 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36546883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36546674 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37016422 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37016214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2598894 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2598684 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::tsunami.ide 1453715 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4052609 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2598894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 4052399 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2598684 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36546883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36546674 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1454240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41069032 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 41099809 # Throughput (bytes/s) -system.membus.data_through_bus 75185198 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.physmem.bw_total::total 41068613 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 948404 # Transaction distribution +system.membus.trans_dist::ReadResp 948404 # Transaction distribution +system.membus.trans_dist::WriteReq 9838 # Transaction distribution +system.membus.trans_dist::WriteResp 9838 # Transaction distribution +system.membus.trans_dist::Writeback 74279 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 132 # Transaction distribution +system.membus.trans_dist::UpgradeResp 132 # Transaction distribution +system.membus.trans_dist::ReadExReq 116985 # Transaction distribution +system.membus.trans_dist::ReadExResp 116985 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2190605 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 2224649 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83452 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83452 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2308101 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72467840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513966 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2670464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2670464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 75184430 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1174168 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 1174168 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 1174168 # Request fanout histogram system.iocache.tags.replacements 41686 # number of replacements -system.iocache.tags.tagsinuse 1.225568 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.225569 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.225568 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.225569 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -108,15 +140,15 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9710428 # DTB read hits +system.cpu.dtb.read_hits 9710423 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6352498 # DTB write hits +system.cpu.dtb.write_hits 6352496 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 16062926 # DTB hits +system.cpu.dtb.data_hits 16062919 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses @@ -136,32 +168,32 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3658664099 # number of cpu cycles simulated +system.cpu.numCycles 3658670345 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60038433 # Number of instructions committed -system.cpu.committedOps 60038433 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 55913650 # Number of integer alu accesses +system.cpu.committedInsts 60038469 # Number of instructions committed +system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses system.cpu.num_func_calls 1484182 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7110776 # number of instructions that are conditional controls -system.cpu.num_int_insts 55913650 # number of integer instructions +system.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls +system.cpu.num_int_insts 55913692 # number of integer instructions system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 76954165 # number of times the integer registers were read -system.cpu.num_int_register_writes 41740323 # number of times the integer registers were written +system.cpu.num_int_register_reads 76954245 # number of times the integer registers were read +system.cpu.num_int_register_writes 41740352 # number of times the integer registers were written system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 16115710 # number of memory refs -system.cpu.num_load_insts 9747514 # Number of load instructions -system.cpu.num_store_insts 6368196 # Number of store instructions -system.cpu.num_idle_cycles 3598608539.425618 # Number of idle cycles -system.cpu.num_busy_cycles 60055559.574382 # Number of busy cycles -system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.983585 # Percentage of idle cycles -system.cpu.Branches 9064413 # Number of branches fetched -system.cpu.op_class::No_OpClass 3199106 5.33% 5.33% # Class of executed instruction -system.cpu.op_class::IntAlu 39448354 65.69% 71.02% # Class of executed instruction -system.cpu.op_class::IntMult 60680 0.10% 71.12% # Class of executed instruction +system.cpu.num_mem_refs 16115703 # number of memory refs +system.cpu.num_load_insts 9747509 # Number of load instructions +system.cpu.num_store_insts 6368194 # Number of store instructions +system.cpu.num_idle_cycles 3598621002.088897 # Number of idle cycles +system.cpu.num_busy_cycles 60049342.911103 # Number of busy cycles +system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.983587 # Percentage of idle cycles +system.cpu.Branches 9064428 # Number of branches fetched +system.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction +system.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction +system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction @@ -189,11 +221,11 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::MemRead 9975082 16.61% 87.80% # Class of executed instruction -system.cpu.op_class::MemWrite 6374117 10.61% 98.42% # Class of executed instruction +system.cpu.op_class::MemRead 9975077 16.61% 87.80% # Class of executed instruction +system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 60050271 # Class of executed instruction +system.cpu.op_class::total 60050307 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed @@ -207,11 +239,11 @@ system.cpu.kern.ipl_good::21 243 0.16% 49.46% # nu system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1811927133000 99.05% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1811929127500 99.05% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 17304360500 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1829331841500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1829331786000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -275,9 +307,9 @@ system.cpu.kern.mode_switch_good::kernel 0.320726 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 26834199500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1801032572000 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1801033399500 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -310,15 +342,50 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1480181 # Throughput (bytes/s) -system.iobus.data_through_bus 2707742 # Total data (bytes) -system.cpu.icache.tags.replacements 919591 # number of replacements -system.cpu.icache.tags.tagsinuse 511.215239 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 59130053 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 920103 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 64.264602 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.215239 # Average occupied blocks per requestor +system.iobus.trans_dist::ReadReq 7358 # Transaction distribution +system.iobus.trans_dist::ReadResp 7358 # Transaction distribution +system.iobus.trans_dist::WriteReq 51390 # Transaction distribution +system.iobus.trans_dist::WriteResp 9838 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes) +system.cpu.icache.tags.replacements 919603 # number of replacements +system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 59130077 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 920115 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 64.263790 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -326,26 +393,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 63 system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60970489 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60970489 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 59130053 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59130053 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59130053 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59130053 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59130053 # number of overall hits -system.cpu.icache.overall_hits::total 59130053 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 920218 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 920218 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 920218 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 920218 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 920218 # number of overall misses -system.cpu.icache.overall_misses::total 920218 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 60050271 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60050271 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60050271 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60050271 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60050271 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60050271 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 60970537 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60970537 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 59130077 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59130077 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59130077 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59130077 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59130077 # number of overall hits +system.cpu.icache.overall_hits::total 59130077 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 920230 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 920230 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 920230 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 920230 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 920230 # number of overall misses +system.cpu.icache.overall_misses::total 920230 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60050307 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60050307 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60050307 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses @@ -361,17 +428,17 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 992295 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65424.374544 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2433214 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1057458 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.301003 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 992289 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65424.374569 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2433258 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1057452 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.301058 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 56309.107765 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.336412 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.930367 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 56310.337833 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4866.106258 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.930478 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.859228 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074251 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id @@ -381,64 +448,64 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3048 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54050 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 31737120 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 31737120 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 906794 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 811217 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1718011 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 833475 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 833475 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 31737481 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 31737481 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 906806 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 811234 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1718040 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 833484 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 833484 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187228 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187228 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906794 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998445 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1905239 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906794 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998445 # number of overall hits -system.cpu.l2cache.overall_hits::total 1905239 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187241 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187241 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 906806 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998475 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1905281 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 906806 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998475 # number of overall hits +system.cpu.l2cache.overall_hits::total 1905281 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 117111 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 117111 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 117105 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 117105 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1044751 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1058157 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1044745 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1058151 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1044751 # number of overall misses -system.cpu.l2cache.overall_misses::total 1058157 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 920200 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1738857 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2659057 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 833475 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 833475 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 1044745 # number of overall misses +system.cpu.l2cache.overall_misses::total 1058151 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 920212 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1738874 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2659086 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 833484 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 833484 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304339 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304339 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 920200 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2043196 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2963396 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 920200 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2043196 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2963396 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533477 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.353902 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 920212 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2963432 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 920212 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2963432 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014568 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.353898 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384804 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384804 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511332 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.357076 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511332 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.357076 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384776 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.384776 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014568 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.511323 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.357069 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014568 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.511323 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.357069 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,14 +514,14 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74285 # number of writebacks -system.cpu.l2cache.writebacks::total 74285 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74279 # number of writebacks +system.cpu.l2cache.writebacks::total 74279 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2042683 # number of replacements +system.cpu.dcache.tags.replacements 2042707 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14038451 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2043195 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 6.870833 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 14038420 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2043219 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 6.870737 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy @@ -464,52 +531,52 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 66369784 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 66369784 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7807792 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807792 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5848219 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5848219 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183142 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183142 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 66369780 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 66369780 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848210 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5848210 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13656011 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13656011 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13656011 # number of overall hits -system.cpu.dcache.overall_hits::total 13656011 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721696 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721696 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304355 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304355 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17161 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17161 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026051 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026051 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026051 # number of overall misses -system.cpu.dcache.overall_misses::total 2026051 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 9529488 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9529488 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 13655981 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655981 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655981 # number of overall hits +system.cpu.dcache.overall_hits::total 13655981 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses +system.cpu.dcache.overall_misses::total 2026074 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15682062 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15682062 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15682062 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15682062 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180670 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.180670 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049468 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049468 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085675 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085675 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.129195 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.129195 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.129195 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.129195 # miss rate for overall accesses +system.cpu.dcache.demand_accesses::cpu.data 15682055 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15682055 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -518,11 +585,35 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 833475 # number of writebacks -system.cpu.dcache.writebacks::total 833475 # number of writebacks +system.cpu.dcache.writebacks::writebacks 833484 # number of writebacks +system.cpu.dcache.writebacks::total 833484 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 134320283 # Throughput (bytes/s) -system.cpu.toL2Bus.data_through_bus 243047022 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 2669376 # Total snoop data (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 2666288 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2666288 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 833484 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304346 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304346 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1840460 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4954000 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6794460 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184155182 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 243049902 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 41883 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3838676 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.010870 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103691 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3796950 98.91% 98.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41726 1.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3838676 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 034bdfed2..977509ec9 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962815 # Number of seconds simulated -sim_ticks 1962815218500 # Number of ticks simulated -final_tick 1962815218500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.961827 # Number of seconds simulated +sim_ticks 1961826628500 # Number of ticks simulated +final_tick 1961826628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1506000 # Simulator instruction rate (inst/s) -host_op_rate 1505999 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49787604582 # Simulator tick rate (ticks/s) -host_mem_usage 317424 # Number of bytes of host memory used -host_seconds 39.42 # Real time elapsed on the host -sim_insts 59372159 # Number of instructions simulated -sim_ops 59372159 # Number of ops (including micro ops) simulated +host_inst_rate 1388652 # Simulator instruction rate (inst/s) +host_op_rate 1388652 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44739465331 # Simulator tick rate (ticks/s) +host_mem_usage 370560 # Number of bytes of host memory used +host_seconds 43.85 # Real time elapsed on the host +sim_insts 60892387 # Number of instructions simulated +sim_ops 60892387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 724992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24166912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 833152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24900864 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 138560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1080576 # Number of bytes read from this memory -system.physmem.bytes_read::total 26112000 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 724992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 138560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5090112 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 31872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 336832 # Number of bytes read from this memory +system.physmem.bytes_read::total 26103680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 833152 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 31872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5078656 # Number of bytes written to this memory system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7749440 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11328 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 377608 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7737984 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13018 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 389076 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16884 # Number of read requests responded to by this memory -system.physmem.num_reads::total 408000 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 79533 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 498 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 5263 # Number of read requests responded to by this memory +system.physmem.num_reads::total 407870 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 79354 # Number of write requests responded to by this memory system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121085 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 369363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12312372 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 120906 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 424682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12692693 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 70592 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 550524 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13303341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 369363 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 70592 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 439956 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2593271 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1354854 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3948125 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2593271 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 369363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12312372 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1355343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 70592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 550524 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17251466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 408000 # Number of read requests accepted -system.physmem.writeReqs 121085 # Number of write requests accepted -system.physmem.readBursts 408000 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121085 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26099968 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue -system.physmem.bytesWritten 7747840 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26112000 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7749440 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_read::cpu1.inst 16246 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 171693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13305804 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 424682 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 16246 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440928 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2588738 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1355537 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3944275 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2588738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 424682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12692693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1356026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 16246 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 171693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17250079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 407870 # Number of read requests accepted +system.physmem.writeReqs 120906 # Number of write requests accepted +system.physmem.readBursts 407870 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120906 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26092032 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11648 # Total number of bytes read from write queue +system.physmem.bytesWritten 7736064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26103680 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7737984 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 182 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3360 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25223 # Per bank write bursts -system.physmem.perBankRdBursts::1 25569 # Per bank write bursts -system.physmem.perBankRdBursts::2 25254 # Per bank write bursts -system.physmem.perBankRdBursts::3 25702 # Per bank write bursts -system.physmem.perBankRdBursts::4 25695 # Per bank write bursts -system.physmem.perBankRdBursts::5 25237 # Per bank write bursts -system.physmem.perBankRdBursts::6 25154 # Per bank write bursts -system.physmem.perBankRdBursts::7 25289 # Per bank write bursts -system.physmem.perBankRdBursts::8 25197 # Per bank write bursts -system.physmem.perBankRdBursts::9 25673 # Per bank write bursts -system.physmem.perBankRdBursts::10 25761 # Per bank write bursts -system.physmem.perBankRdBursts::11 25821 # Per bank write bursts -system.physmem.perBankRdBursts::12 25887 # Per bank write bursts -system.physmem.perBankRdBursts::13 25811 # Per bank write bursts -system.physmem.perBankRdBursts::14 25568 # Per bank write bursts -system.physmem.perBankRdBursts::15 24971 # Per bank write bursts -system.physmem.perBankWrBursts::0 7862 # Per bank write bursts -system.physmem.perBankWrBursts::1 7635 # Per bank write bursts -system.physmem.perBankWrBursts::2 7481 # Per bank write bursts -system.physmem.perBankWrBursts::3 8078 # Per bank write bursts -system.physmem.perBankWrBursts::4 7635 # Per bank write bursts -system.physmem.perBankWrBursts::5 7244 # Per bank write bursts -system.physmem.perBankWrBursts::6 7160 # Per bank write bursts -system.physmem.perBankWrBursts::7 6937 # Per bank write bursts -system.physmem.perBankWrBursts::8 6882 # Per bank write bursts -system.physmem.perBankWrBursts::9 7297 # Per bank write bursts -system.physmem.perBankWrBursts::10 7429 # Per bank write bursts -system.physmem.perBankWrBursts::11 7398 # Per bank write bursts -system.physmem.perBankWrBursts::12 8124 # Per bank write bursts -system.physmem.perBankWrBursts::13 8265 # Per bank write bursts -system.physmem.perBankWrBursts::14 8169 # Per bank write bursts -system.physmem.perBankWrBursts::15 7464 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 6995 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25277 # Per bank write bursts +system.physmem.perBankRdBursts::1 25718 # Per bank write bursts +system.physmem.perBankRdBursts::2 25598 # Per bank write bursts +system.physmem.perBankRdBursts::3 25075 # Per bank write bursts +system.physmem.perBankRdBursts::4 25186 # Per bank write bursts +system.physmem.perBankRdBursts::5 25258 # Per bank write bursts +system.physmem.perBankRdBursts::6 25824 # Per bank write bursts +system.physmem.perBankRdBursts::7 25548 # Per bank write bursts +system.physmem.perBankRdBursts::8 25573 # Per bank write bursts +system.physmem.perBankRdBursts::9 25196 # Per bank write bursts +system.physmem.perBankRdBursts::10 25177 # Per bank write bursts +system.physmem.perBankRdBursts::11 25610 # Per bank write bursts +system.physmem.perBankRdBursts::12 25669 # Per bank write bursts +system.physmem.perBankRdBursts::13 25717 # Per bank write bursts +system.physmem.perBankRdBursts::14 26016 # Per bank write bursts +system.physmem.perBankRdBursts::15 25246 # Per bank write bursts +system.physmem.perBankWrBursts::0 7929 # Per bank write bursts +system.physmem.perBankWrBursts::1 7788 # Per bank write bursts +system.physmem.perBankWrBursts::2 7545 # Per bank write bursts +system.physmem.perBankWrBursts::3 7026 # Per bank write bursts +system.physmem.perBankWrBursts::4 7134 # Per bank write bursts +system.physmem.perBankWrBursts::5 7133 # Per bank write bursts +system.physmem.perBankWrBursts::6 7657 # Per bank write bursts +system.physmem.perBankWrBursts::7 7252 # Per bank write bursts +system.physmem.perBankWrBursts::8 7395 # Per bank write bursts +system.physmem.perBankWrBursts::9 7084 # Per bank write bursts +system.physmem.perBankWrBursts::10 7119 # Per bank write bursts +system.physmem.perBankWrBursts::11 7401 # Per bank write bursts +system.physmem.perBankWrBursts::12 7832 # Per bank write bursts +system.physmem.perBankWrBursts::13 8315 # Per bank write bursts +system.physmem.perBankWrBursts::14 8567 # Per bank write bursts +system.physmem.perBankWrBursts::15 7699 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 6 # Number of times write queue was full causing retry -system.physmem.totGap 1962808109000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry +system.physmem.totGap 1961819616500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 408000 # Read request sizes (log2) +system.physmem.readPktSize::6 407870 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 121085 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407738 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120906 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -161,357 +161,363 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6075 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66023 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 512.666919 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 309.343673 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.043592 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15664 23.73% 23.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11865 17.97% 41.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5137 7.78% 49.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3080 4.67% 54.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3330 5.04% 59.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1778 2.69% 61.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1463 2.22% 64.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1306 1.98% 66.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22400 33.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66023 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5447 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 74.865981 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2190.069327 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 5442 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66427 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 509.252202 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 306.095148 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.238328 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15972 24.04% 24.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12116 18.24% 42.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5140 7.74% 50.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2994 4.51% 54.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3304 4.97% 59.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1746 2.63% 62.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1491 2.24% 64.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1317 1.98% 66.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22347 33.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66427 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5433 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.036996 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2192.886898 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 5428 99.91% 99.91% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5447 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5447 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.225078 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.080270 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 19.855094 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4780 87.75% 87.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 19 0.35% 88.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 16 0.29% 88.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 235 4.31% 92.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 38 0.70% 93.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 9 0.17% 93.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 13 0.24% 93.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 10 0.18% 94.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 23 0.42% 94.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 3 0.06% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.04% 94.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.02% 94.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 7 0.13% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.09% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.07% 94.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 29 0.53% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 14 0.26% 95.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 6 0.11% 95.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 6 0.11% 95.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 182 3.34% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.04% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.04% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 10 0.18% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.04% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 5 0.09% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 5 0.09% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 8 0.15% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.04% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5433 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5433 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.248482 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.059784 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 19.984616 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4773 87.85% 87.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 17 0.31% 88.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 17 0.31% 88.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 237 4.36% 92.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 33 0.61% 93.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 9 0.17% 93.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 6 0.11% 93.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 9 0.17% 93.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 24 0.44% 94.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.02% 94.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 10 0.18% 94.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.11% 94.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.06% 94.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.07% 94.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 32 0.59% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 11 0.20% 95.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.06% 95.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 9 0.17% 95.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 180 3.31% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.07% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.06% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 4 0.07% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.07% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 5 0.09% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 7 0.13% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 13 0.24% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-227 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5447 # Writes before turning the bus around for reads -system.physmem.totQLat 2167934250 # Total ticks spent queuing -system.physmem.totMemAccLat 9814409250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2039060000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5316.01 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5433 # Writes before turning the bus around for reads +system.physmem.totQLat 2198653000 # Total ticks spent queuing +system.physmem.totMemAccLat 9842803000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2038440000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5392.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24066.01 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24142.98 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.30 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.30 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.31 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.94 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.06 # Average write queue length when enqueuing -system.physmem.readRowHits 365758 # Number of row buffer hits during reads -system.physmem.writeRowHits 97091 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.69 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.18 # Row buffer hit rate for writes -system.physmem.avgGap 3709816.21 # Average gap between requests -system.physmem.pageHitRate 87.51 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1840831671000 # Time in different power states -system.physmem.memoryStateTime::REF 65542620000 # Time in different power states +system.physmem.avgWrQLen 26.12 # Average write queue length when enqueuing +system.physmem.readRowHits 365377 # Number of row buffer hits during reads +system.physmem.writeRowHits 96760 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.03 # Row buffer hit rate for writes +system.physmem.avgGap 3710114.71 # Average gap between requests +system.physmem.pageHitRate 87.43 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1840052567250 # Time in different power states +system.physmem.memoryStateTime::REF 65509600000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 56438386500 # Time in different power states +system.physmem.memoryStateTime::ACT 56261656500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 17291736 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292660 # Transaction distribution -system.membus.trans_dist::ReadResp 292660 # Transaction distribution -system.membus.trans_dist::WriteReq 12414 # Transaction distribution -system.membus.trans_dist::WriteResp 12414 # Transaction distribution -system.membus.trans_dist::Writeback 79533 # Transaction distribution +system.membus.trans_dist::ReadReq 292757 # Transaction distribution +system.membus.trans_dist::ReadResp 292757 # Transaction distribution +system.membus.trans_dist::WriteReq 14067 # Transaction distribution +system.membus.trans_dist::WriteResp 14067 # Transaction distribution +system.membus.trans_dist::Writeback 79354 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4556 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1019 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3360 # Transaction distribution -system.membus.trans_dist::ReadExReq 122803 # Transaction distribution -system.membus.trans_dist::ReadExResp 122701 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39228 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 904540 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 943768 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83295 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83295 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1027063 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68738 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31201152 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31269890 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 33930178 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 33930178 # Total data (bytes) -system.membus.snoop_data_through_bus 10304 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 39224500 # Layer occupancy (ticks) +system.membus.trans_dist::UpgradeReq 16159 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11272 # Transaction distribution +system.membus.trans_dist::UpgradeResp 6995 # Transaction distribution +system.membus.trans_dist::ReadExReq 123294 # Transaction distribution +system.membus.trans_dist::ReadExResp 122471 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42532 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 930313 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 972845 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83293 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83293 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1056138 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81954 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31181376 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31263330 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33923618 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 21418 # Total snoops (count) +system.membus.snoop_fanout::samples 557197 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 557197 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 557197 # Request fanout histogram +system.membus.reqLayer0.occupancy 40794500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1533573250 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1536995500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3826483141 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3833296255 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43139750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43122000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 342222 # number of replacements -system.l2c.tags.tagsinuse 65256.426750 # Cycle average of tags in use -system.l2c.tags.total_refs 2542307 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407368 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.240812 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8652281750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55518.260732 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3744.767678 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4299.632317 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1171.746225 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 522.019798 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.847141 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.057141 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.065607 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.017879 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.007965 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995734 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65146 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 748 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5288 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7253 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51739 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994049 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26946350 # Number of tag accesses -system.l2c.tags.data_accesses 26946350 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 527823 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 377901 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 461413 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 449863 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1817000 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 850078 # number of Writeback hits -system.l2c.Writeback_hits::total 850078 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 70 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 205 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 25 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 46 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 113452 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 85004 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 198456 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 527823 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 491353 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 461413 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 534867 # number of demand (read+write) hits -system.l2c.demand_hits::total 2015456 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 527823 # number of overall hits -system.l2c.overall_hits::cpu0.data 491353 # number of overall hits -system.l2c.overall_hits::cpu1.inst 461413 # number of overall hits -system.l2c.overall_hits::cpu1.data 534867 # number of overall hits -system.l2c.overall_hits::total 2015456 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11331 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 270739 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2173 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1052 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285295 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2603 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 469 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3072 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 62 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 80 # 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number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 827161250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17596749000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 162190250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 79449000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18665549500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 700470 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 348985 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1049455 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 162993 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 93496 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 256489 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7343632619 # 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number of overall miss cycles -system.l2c.overall_miss_latency::total 27166383354 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 539154 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 648640 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 463586 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 450915 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2102295 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 850078 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 850078 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2738 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 539 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3277 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 87 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 101 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 220452 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 100851 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 321303 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 539154 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 869092 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 463586 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 551766 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2423598 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 539154 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 869092 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 463586 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 551766 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2423598 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.021016 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.417395 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.004687 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.002333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.135706 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.950694 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.870130 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.937443 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.712644 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.792079 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.755319 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.485366 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.157133 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.382340 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.021016 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.434636 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004687 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.030627 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.168403 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.021016 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.434636 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004687 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.030627 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.168403 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72999.845556 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 64995.250038 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74638.863323 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 75521.863118 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 65425.435076 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 269.101037 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 744.104478 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 341.619466 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2628.919355 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1168.700000 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1806.260563 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68632.080551 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73023.363097 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 69198.546599 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 72999.845556 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 66025.434543 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 74638.863323 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 73178.900231 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 66561.107051 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 72999.845556 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 66025.434543 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 74638.863323 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 73178.900231 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 66561.107051 # average overall miss latency +system.l2c.tags.replacements 342092 # number of replacements +system.l2c.tags.tagsinuse 65220.775537 # Cycle average of tags in use +system.l2c.tags.total_refs 2444844 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 407280 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.002858 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8652068750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 55275.158075 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4808.073812 # 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number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4697 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 889 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 909 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1798 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 117934 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 5037 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 122971 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13018 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 389564 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 498 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 5275 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 408355 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13018 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 389564 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 498 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 5275 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 408355 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 787294250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14275629250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 30082250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 14147750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 15107153500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29547954 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 17431743 # 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number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 325358512 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 22081159750 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 787294250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 20938424738 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 30082250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 325358512 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 22081159750 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373183500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17608500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1390792000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2147807000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 674603500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2822410500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3520990500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 692212000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4213202500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018499 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.289029 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001596 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002278 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.138536 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941964 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.763135 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.866605 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.955914 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975322 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.965628 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.474650 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.106488 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.415771 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018499 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 54073.440389 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60477.358273 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53748.356465 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60406.124498 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61679.338768 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 54073.440389 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -646,54 +652,54 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # 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Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035621 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1755504878000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.569739 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035609 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035609 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375552 # Number of tag accesses -system.iocache.tags.data_accesses 375552 # Number of data accesses +system.iocache.tags.tag_accesses 375534 # Number of tag accesses +system.iocache.tags.data_accesses 375534 # Number of data accesses system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # 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number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21248383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21248383 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122013.539773 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122013.539773 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122117.143678 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122117.143678 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122117.143678 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122117.143678 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122117.143678 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122117.143678 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -702,22 +708,22 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12321383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2504351556 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2504351556 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12321383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12321383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12321383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12321383 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12199383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12199383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2501404806 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2501404806 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12199383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12199383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12199383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12199383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -726,14 +732,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60270.301213 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60270.301213 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70111.396552 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60199.384049 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60199.384049 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70111.396552 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70111.396552 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -751,22 +757,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 6067147 # DTB read hits +system.cpu0.dtb.read_hits 7562596 # DTB read hits system.cpu0.dtb.read_misses 7765 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 4265547 # DTB write hits +system.cpu0.dtb.write_hits 5147185 # DTB write hits system.cpu0.dtb.write_misses 910 # DTB write misses system.cpu0.dtb.write_acv 133 # DTB write access violations system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 10332694 # DTB hits +system.cpu0.dtb.data_hits 12709781 # DTB hits system.cpu0.dtb.data_misses 8675 # DTB misses system.cpu0.dtb.data_acv 343 # DTB access violations system.cpu0.dtb.data_accesses 726664 # DTB accesses -system.cpu0.itb.fetch_hits 3354719 # ITB hits +system.cpu0.itb.fetch_hits 3660706 # ITB hits system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3358703 # ITB accesses +system.cpu0.itb.fetch_accesses 3664690 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -779,91 +785,91 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3925630437 # number of cpu cycles simulated +system.cpu0.numCycles 3923653257 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 38276405 # Number of instructions committed -system.cpu0.committedOps 38276405 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 35596815 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 153493 # Number of float alu accesses -system.cpu0.num_func_calls 936479 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4465105 # number of instructions that are conditional controls -system.cpu0.num_int_insts 35596815 # number of integer instructions -system.cpu0.num_fp_insts 153493 # number of float instructions -system.cpu0.num_int_register_reads 48919188 # number of times the integer registers were read -system.cpu0.num_int_register_writes 26532196 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 75000 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 75910 # number of times the floating registers were written -system.cpu0.num_mem_refs 10365856 # number of memory refs -system.cpu0.num_load_insts 6090539 # Number of load instructions -system.cpu0.num_store_insts 4275317 # Number of store instructions -system.cpu0.num_idle_cycles 3742236660.998093 # Number of idle cycles -system.cpu0.num_busy_cycles 183393776.001907 # Number of busy cycles -system.cpu0.not_idle_fraction 0.046717 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.953283 # Percentage of idle cycles -system.cpu0.Branches 5694884 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2096297 5.48% 5.48% # Class of executed instruction -system.cpu0.op_class::IntAlu 24983670 65.26% 70.73% # Class of executed instruction -system.cpu0.op_class::IntMult 39322 0.10% 70.83% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 70.83% # Class of executed instruction -system.cpu0.op_class::FloatAdd 24596 0.06% 70.90% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1883 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::MemRead 6232893 16.28% 87.18% # Class of executed instruction -system.cpu0.op_class::MemWrite 4280562 11.18% 98.36% # Class of executed instruction -system.cpu0.op_class::IprAccess 626200 1.64% 100.00% # Class of executed instruction +system.cpu0.committedInsts 48127777 # Number of instructions committed +system.cpu0.committedOps 48127777 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44643925 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 213512 # Number of float alu accesses +system.cpu0.num_func_calls 1209739 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5647172 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44643925 # number of integer instructions +system.cpu0.num_fp_insts 213512 # number of float instructions +system.cpu0.num_int_register_reads 61387452 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33242964 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 104337 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 106136 # number of times the floating registers were written +system.cpu0.num_mem_refs 12750882 # number of memory refs +system.cpu0.num_load_insts 7590433 # Number of load instructions +system.cpu0.num_store_insts 5160449 # Number of store instructions +system.cpu0.num_idle_cycles 3699495012.998114 # Number of idle cycles +system.cpu0.num_busy_cycles 224158244.001886 # Number of busy cycles +system.cpu0.not_idle_fraction 0.057130 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.942870 # Percentage of idle cycles +system.cpu0.Branches 7246936 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2741568 5.70% 5.70% # Class of executed instruction +system.cpu0.op_class::IntAlu 31634980 65.72% 71.41% # Class of executed instruction +system.cpu0.op_class::IntMult 52525 0.11% 71.52% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.52% # Class of executed instruction +system.cpu0.op_class::FloatAdd 26830 0.06% 71.58% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1883 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::MemRead 7767201 16.14% 87.72% # Class of executed instruction +system.cpu0.op_class::MemWrite 5166567 10.73% 98.45% # Class of executed instruction +system.cpu0.op_class::IprAccess 745241 1.55% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 38285423 # Class of executed instruction +system.cpu0.op_class::total 48136795 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4863 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 138357 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 44808 38.76% 38.76% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.11% 38.88% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1975 1.71% 40.58% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 16 0.01% 40.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 68665 59.40% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 115595 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 44283 48.84% 48.84% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.14% 48.98% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1975 2.18% 51.16% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 16 0.02% 51.18% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 44267 48.82% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 90672 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1909699143000 97.29% 97.29% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 95243500 0.00% 97.30% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 764380500 0.04% 97.34% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 12585500 0.00% 97.34% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 52243094000 2.66% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1962814446500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.988283 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6805 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 166328 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 57239 40.25% 40.25% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.34% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1975 1.39% 41.73% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 424 0.30% 42.03% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82449 57.97% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 142218 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56706 49.09% 49.09% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1975 1.71% 50.91% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 424 0.37% 51.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 56283 48.72% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 115519 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1902225794500 96.96% 96.96% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 94977500 0.00% 96.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 767421000 0.04% 97.01% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 314336500 0.02% 97.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 58423341500 2.98% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1961825871000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990688 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.644681 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.784394 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.682640 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.812267 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed @@ -895,37 +901,37 @@ system.cpu0.kern.syscall::144 2 0.85% 99.15% # nu system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 86 0.07% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2216 1.80% 1.87% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.04% 1.92% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.01% 1.92% # number of callpals executed -system.cpu0.kern.callpal::swpipl 109456 88.95% 90.88% # number of callpals executed -system.cpu0.kern.callpal::rdps 6662 5.41% 96.29% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.29% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.29% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.30% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.30% # number of callpals executed -system.cpu0.kern.callpal::rti 4016 3.26% 99.57% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.32% 99.89% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.11% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 123047 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5724 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1372 # number of protection mode switches +system.cpu0.kern.callpal::wripir 506 0.34% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3105 2.06% 2.40% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.43% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.44% # number of callpals executed +system.cpu0.kern.callpal::swpipl 135265 89.81% 92.25% # number of callpals executed +system.cpu0.kern.callpal::rdps 6701 4.45% 96.70% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.70% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.70% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.71% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.71% # number of callpals executed +system.cpu0.kern.callpal::rti 4423 2.94% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 150611 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7020 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1371 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1371 -system.cpu0.kern.mode_good::user 1372 +system.cpu0.kern.mode_good::kernel 1370 +system.cpu0.kern.mode_good::user 1371 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.239518 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.195157 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.386556 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1959023925000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3790517000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.326660 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958053140500 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3772726000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2217 # number of times the context was actually changed +system.cpu0.kern.swap_context 3106 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -957,49 +963,59 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 109416622 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2148133 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2148118 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12414 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12414 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 850078 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 41558 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 4615 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1065 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 5680 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 322069 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 322069 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078328 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2181300 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 927173 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1598235 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5785036 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 34505856 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 81606637 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29669504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 63812309 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 209594306 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 209584002 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 5180608 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5075622491 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::ReadReq 2102030 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2102015 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14067 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14067 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 792816 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 41560 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16382 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11336 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 27718 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297616 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297616 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1407417 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3134555 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 624007 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 452565 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5618544 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 45036672 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120042720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 19968192 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16553666 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 201601250 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 98838 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3254541 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.012823 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112512 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3212807 98.72% 98.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41734 1.28% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3254541 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4795402363 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 715500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2428486244 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4030575545 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 2086565739 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3169257997 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 5536514081 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 1404115991 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 2646502814 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1391048 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7376 # Transaction distribution -system.iobus.trans_dist::ReadResp 7376 # Transaction distribution -system.iobus.trans_dist::WriteReq 53966 # Transaction distribution -system.iobus.trans_dist::WriteResp 53966 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10614 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 484 # Packet count per connected master and slave (bytes) +system.toL2Bus.respLayer3.occupancy 776560164 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 7373 # Transaction distribution +system.iobus.trans_dist::ReadResp 7373 # Transaction distribution +system.iobus.trans_dist::WriteReq 55619 # Transaction distribution +system.iobus.trans_dist::WriteResp 55619 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13922 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1010,30 +1026,29 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 39228 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 122684 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42456 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1936 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 68738 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2730370 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2730370 # Total data (bytes) -system.iobus.reqLayer0.occupancy 9969000 # Layer occupancy (ticks) +system.iobus.pkt_count_system.bridge.master::total 42532 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 125984 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55688 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 81954 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2743570 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13277000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 362000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1053,67 +1068,67 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 374413689 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374410189 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 26814000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28465000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42018250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42017000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 538541 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.393356 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 37746250 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 539053 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.023263 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 703089 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.385515 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47433077 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 703601 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.414738 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.393356 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992956 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992956 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.385515 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992940 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992940 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 442 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 38824598 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 38824598 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 37746250 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 37746250 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 37746250 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 37746250 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 37746250 # number of overall hits -system.cpu0.icache.overall_hits::total 37746250 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 539174 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 539174 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 539174 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 539174 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 539174 # number of overall misses -system.cpu0.icache.overall_misses::total 539174 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7756302744 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7756302744 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7756302744 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7756302744 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7756302744 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7756302744 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 38285424 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 38285424 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 38285424 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 38285424 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 38285424 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 38285424 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014083 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014083 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014083 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014083 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014083 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014083 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14385.528130 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14385.528130 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14385.528130 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14385.528130 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14385.528130 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14385.528130 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48840515 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48840515 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 47433077 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47433077 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47433077 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47433077 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47433077 # number of overall hits +system.cpu0.icache.overall_hits::total 47433077 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 703719 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 703719 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 703719 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 703719 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 703719 # number of overall misses +system.cpu0.icache.overall_misses::total 703719 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10017635497 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10017635497 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10017635497 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10017635497 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10017635497 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10017635497 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 48136796 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 48136796 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 48136796 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 48136796 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 48136796 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 48136796 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014619 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014619 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014619 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014619 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014619 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014619 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14235.277855 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14235.277855 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14235.277855 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14235.277855 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14235.277855 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14235.277855 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1122,119 +1137,119 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 539174 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 539174 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 539174 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 539174 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 539174 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 539174 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6673548256 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6673548256 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6673548256 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6673548256 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6673548256 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6673548256 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014083 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014083 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014083 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014083 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014083 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014083 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12377.355466 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12377.355466 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12377.355466 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12377.355466 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12377.355466 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12377.355466 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 703719 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 703719 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 703719 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 703719 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 703719 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 703719 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8605152503 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8605152503 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8605152503 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8605152503 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8605152503 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8605152503 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014619 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014619 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014619 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014619 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014619 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014619 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12228.108809 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12228.108809 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12228.108809 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12228.108809 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12228.108809 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12228.108809 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 871192 # number of replacements -system.cpu0.dcache.tags.tagsinuse 481.742326 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9465806 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 871704 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 10.858968 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1191194 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.224955 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11513307 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1191706 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.661197 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.742326 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.940903 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.940903 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.224955 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986767 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986767 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 42232679 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 42232679 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5299779 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5299779 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3905718 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3905718 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 124794 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 124794 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 131579 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 131579 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9205497 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9205497 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9205497 # number of overall hits -system.cpu0.dcache.overall_hits::total 9205497 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 645318 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 645318 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 224183 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 224183 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7829 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 7829 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 497 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 497 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 869501 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 869501 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 869501 # number of overall misses -system.cpu0.dcache.overall_misses::total 869501 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 23374202500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 23374202500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9262527483 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 9262527483 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 102834500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 102834500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3584562 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3584562 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 32636729983 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 32636729983 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 32636729983 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 32636729983 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5945097 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 5945097 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4129901 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4129901 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132623 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 132623 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 132076 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 132076 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10074998 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10074998 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10074998 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10074998 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.108546 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.108546 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.054283 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.054283 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059032 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059032 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003763 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003763 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086303 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.086303 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086303 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.086303 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 36221.215742 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 36221.215742 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41316.814758 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 41316.814758 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13135.074722 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13135.074722 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7212.398390 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7212.398390 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37535.011441 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 37535.011441 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37535.011441 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 37535.011441 # average overall miss latency +system.cpu0.dcache.tags.tag_accesses 52084143 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 52084143 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6477469 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6477469 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4731394 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4731394 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 141563 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 141563 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149256 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149256 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11208863 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11208863 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11208863 # number of overall hits +system.cpu0.dcache.overall_hits::total 11208863 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 942620 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 942620 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 258040 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 258040 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13696 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13696 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5452 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5452 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1200660 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1200660 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1200660 # number of overall misses +system.cpu0.dcache.overall_misses::total 1200660 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27232981250 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 27232981250 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10355566942 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10355566942 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149859500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 149859500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42011389 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 42011389 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 37588548192 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 37588548192 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 37588548192 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 37588548192 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7420089 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7420089 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4989434 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4989434 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 155259 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 155259 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 154708 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 154708 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12409523 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12409523 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12409523 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12409523 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127036 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127036 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051717 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051717 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088214 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088214 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035241 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035241 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096753 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.096753 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096753 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.096753 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28890.731419 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28890.731419 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40131.634406 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40131.634406 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10941.844334 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10941.844334 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7705.683969 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7705.683969 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31306.571546 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 31306.571546 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31306.571546 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31306.571546 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1243,62 +1258,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 405151 # number of writebacks -system.cpu0.dcache.writebacks::total 405151 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 645318 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 645318 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 224183 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 224183 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7829 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7829 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 497 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 497 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 869501 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 869501 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 869501 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 869501 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21958327500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21958327500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8765186517 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8765186517 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 87163500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 87163500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2590438 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2590438 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30723514017 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 30723514017 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30723514017 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 30723514017 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1004927000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1004927000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1718158000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1718158000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2723085000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2723085000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108546 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108546 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.054283 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.054283 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059032 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059032 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003763 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003763 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086303 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.086303 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086303 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.086303 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34027.142432 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34027.142432 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39098.354991 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39098.354991 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11133.414229 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11133.414229 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5212.148893 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5212.148893 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35334.650583 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35334.650583 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35334.650583 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35334.650583 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 686359 # number of writebacks +system.cpu0.dcache.writebacks::total 686359 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942620 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 942620 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 258040 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 258040 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13696 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13696 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5452 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5452 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1200660 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1200660 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1200660 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1200660 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25222171750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25222171750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9786377058 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9786377058 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 122453500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 122453500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31105611 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31105611 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35008548808 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 35008548808 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35008548808 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 35008548808 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465625500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465625500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2277904000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2277904000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3743529500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3743529500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127036 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127036 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051717 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051717 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088214 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088214 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035241 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035241 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096753 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.096753 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096753 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.096753 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26757.518141 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26757.518141 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37925.814052 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37925.814052 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8940.822138 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8940.822138 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5705.357850 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5705.357850 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29157.753909 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29157.753909 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29157.753909 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29157.753909 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1310,22 +1325,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 3617054 # DTB read hits +system.cpu1.dtb.read_hits 2348280 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 2433875 # DTB write hits +system.cpu1.dtb.write_hits 1676993 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 6050929 # DTB hits +system.cpu1.dtb.data_hits 4025273 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1988100 # ITB hits +system.cpu1.itb.fetch_hits 1801078 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1989164 # ITB accesses +system.cpu1.itb.fetch_accesses 1802142 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1338,87 +1353,87 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3923841470 # number of cpu cycles simulated +system.cpu1.numCycles 3921880878 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 21095754 # Number of instructions committed -system.cpu1.committedOps 21095754 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 19410964 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 175175 # Number of float alu accesses -system.cpu1.num_func_calls 648514 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2286581 # number of instructions that are conditional controls -system.cpu1.num_int_insts 19410964 # number of integer instructions -system.cpu1.num_fp_insts 175175 # number of float instructions -system.cpu1.num_int_register_reads 26520307 # number of times the integer registers were read -system.cpu1.num_int_register_writes 14289908 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 90745 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 92744 # number of times the floating registers were written -system.cpu1.num_mem_refs 6073169 # number of memory refs -system.cpu1.num_load_insts 3630901 # Number of load instructions -system.cpu1.num_store_insts 2442268 # Number of store instructions -system.cpu1.num_idle_cycles 3837673362.965370 # Number of idle cycles -system.cpu1.num_busy_cycles 86168107.034630 # Number of busy cycles -system.cpu1.not_idle_fraction 0.021960 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.978040 # Percentage of idle cycles -system.cpu1.Branches 3165037 # Number of branches fetched -system.cpu1.op_class::No_OpClass 1250062 5.92% 5.92% # Class of executed instruction -system.cpu1.op_class::IntAlu 13186802 62.50% 68.43% # Class of executed instruction -system.cpu1.op_class::IntMult 30198 0.14% 68.57% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.57% # Class of executed instruction -system.cpu1.op_class::FloatAdd 13644 0.06% 68.63% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.63% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.63% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.63% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1759 0.01% 68.64% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::MemRead 3726078 17.66% 86.30% # Class of executed instruction -system.cpu1.op_class::MemWrite 2443288 11.58% 97.88% # Class of executed instruction -system.cpu1.op_class::IprAccess 446802 2.12% 100.00% # Class of executed instruction +system.cpu1.committedInsts 12764610 # Number of instructions committed +system.cpu1.committedOps 12764610 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 11762987 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 170364 # Number of float alu accesses +system.cpu1.num_func_calls 404048 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1265459 # number of instructions that are conditional controls +system.cpu1.num_int_insts 11762987 # number of integer instructions +system.cpu1.num_fp_insts 170364 # number of float instructions +system.cpu1.num_int_register_reads 16177090 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8656212 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 88600 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 90534 # number of times the floating registers were written +system.cpu1.num_mem_refs 4047820 # number of memory refs +system.cpu1.num_load_insts 2361802 # Number of load instructions +system.cpu1.num_store_insts 1686018 # Number of store instructions +system.cpu1.num_idle_cycles 3873240792.459649 # Number of idle cycles +system.cpu1.num_busy_cycles 48640085.540351 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012402 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987598 # Percentage of idle cycles +system.cpu1.Branches 1821460 # Number of branches fetched +system.cpu1.op_class::No_OpClass 690637 5.41% 5.41% # Class of executed instruction +system.cpu1.op_class::IntAlu 7566798 59.27% 64.68% # Class of executed instruction +system.cpu1.op_class::IntMult 21839 0.17% 64.85% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.85% # Class of executed instruction +system.cpu1.op_class::FloatAdd 13058 0.10% 64.95% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1759 0.01% 64.96% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::MemRead 2432293 19.05% 84.01% # Class of executed instruction +system.cpu1.op_class::MemWrite 1686990 13.21% 97.23% # Class of executed instruction +system.cpu1.op_class::IprAccess 354115 2.77% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 21098633 # Class of executed instruction +system.cpu1.op_class::total 12767489 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3863 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 100733 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 37218 40.29% 40.29% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1970 2.13% 42.42% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 86 0.09% 42.51% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 53108 57.49% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 92382 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 36366 48.68% 48.68% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1970 2.64% 51.32% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 86 0.12% 51.43% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 36280 48.57% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 74702 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1906657223000 97.18% 97.18% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 706239500 0.04% 97.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 59367000 0.00% 97.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 54497875500 2.78% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1961920705000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.977108 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 77083 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26133 38.19% 38.19% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1969 2.88% 41.07% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 506 0.74% 41.81% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 39822 58.19% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 68430 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25289 48.13% 48.13% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1969 3.75% 51.87% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 506 0.96% 52.84% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 24783 47.16% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 52547 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909614154000 97.38% 97.38% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 700846000 0.04% 97.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 353816000 0.02% 97.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 50271593000 2.56% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1960940409000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.967704 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.683136 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.808621 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.622344 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.767894 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -1434,87 +1449,87 @@ system.cpu1.kern.syscall::74 9 9.78% 96.74% # nu system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2020 2.13% 2.15% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 2.16% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.16% # number of callpals executed -system.cpu1.kern.callpal::swpipl 87059 91.90% 94.06% # number of callpals executed -system.cpu1.kern.callpal::rdps 2187 2.31% 96.37% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 96.37% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 96.38% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 96.38% # number of callpals executed -system.cpu1.kern.callpal::rti 3266 3.45% 99.83% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.13% 99.95% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.04% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 424 0.60% 0.60% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1955 2.77% 3.37% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62269 88.12% 91.51% # number of callpals executed +system.cpu1.kern.callpal::rdps 2146 3.04% 94.54% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.54% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 94.55% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.55% # number of callpals executed +system.cpu1.kern.callpal::rti 3685 5.21% 99.77% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 94732 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2415 # number of protection mode switches +system.cpu1.kern.callpal::total 70663 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1918 # number of protection mode switches system.cpu1.kern.mode_switch::user 367 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2037 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 415 +system.cpu1.kern.mode_switch::idle 2888 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 797 system.cpu1.kern.mode_good::user 367 -system.cpu1.kern.mode_good::idle 48 -system.cpu1.kern.mode_switch_good::kernel 0.171843 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 430 +system.cpu1.kern.mode_switch_good::kernel 0.415537 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.023564 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.172235 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 65779284000 3.35% 3.35% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1486343500 0.08% 3.43% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893759051500 96.57% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2021 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 463035 # number of replacements -system.cpu1.icache.tags.tagsinuse 500.061178 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 20635046 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 463547 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 44.515542 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 97712638250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 500.061178 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.976682 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.976682 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 404 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 21562220 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 21562220 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 20635046 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 20635046 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 20635046 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 20635046 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 20635046 # number of overall hits -system.cpu1.icache.overall_hits::total 20635046 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 463587 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 463587 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 463587 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 463587 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 463587 # number of overall misses -system.cpu1.icache.overall_misses::total 463587 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6202855739 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6202855739 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6202855739 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6202855739 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6202855739 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6202855739 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 21098633 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 21098633 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 21098633 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 21098633 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 21098633 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 21098633 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021972 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.021972 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021972 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.021972 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021972 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.021972 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13380.133047 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13380.133047 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13380.133047 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13380.133047 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13380.133047 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13380.133047 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.148892 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.308138 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17565031500 0.90% 0.90% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1483893000 0.08% 0.97% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1941003590000 99.03% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1956 # number of times the context was actually changed +system.cpu1.icache.tags.replacements 311453 # number of replacements +system.cpu1.icache.tags.tagsinuse 446.345950 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12455485 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 311964 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.926033 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1960014862500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.345950 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871769 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.871769 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 71 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 440 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 13079493 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13079493 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 12455485 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12455485 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12455485 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12455485 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12455485 # number of overall hits +system.cpu1.icache.overall_hits::total 12455485 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 312004 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 312004 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 312004 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 312004 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 312004 # number of overall misses +system.cpu1.icache.overall_misses::total 312004 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4105450991 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4105450991 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4105450991 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4105450991 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4105450991 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4105450991 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 12767489 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 12767489 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 12767489 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 12767489 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 12767489 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 12767489 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024437 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024437 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024437 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024437 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024437 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024437 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13158.328070 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13158.328070 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13158.328070 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13158.328070 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13158.328070 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13158.328070 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1523,118 +1538,118 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463587 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 463587 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 463587 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 463587 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 463587 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 463587 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5274833261 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5274833261 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5274833261 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5274833261 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5274833261 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5274833261 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021972 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.021972 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.021972 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11378.302802 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11378.302802 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11378.302802 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 312004 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 312004 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 312004 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 312004 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 312004 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 312004 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3481247009 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3481247009 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3481247009 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3481247009 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3481247009 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3481247009 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024437 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024437 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024437 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024437 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024437 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024437 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11157.699930 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11157.699930 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11157.699930 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11157.699930 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11157.699930 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11157.699930 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 581700 # number of replacements -system.cpu1.dcache.tags.tagsinuse 492.027042 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 5462019 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 582040 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 9.384267 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 61159690250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.027042 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.960990 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.960990 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 340 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 298 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.664062 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 24828314 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 24828314 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3080149 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3080149 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2259986 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2259986 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 60927 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 60927 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71555 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71555 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 5340135 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5340135 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 5340135 # number of overall hits -system.cpu1.dcache.overall_hits::total 5340135 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 473178 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 473178 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 102501 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 102501 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11671 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11671 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 568 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 568 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 575679 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 575679 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 575679 # number of overall misses -system.cpu1.dcache.overall_misses::total 575679 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5938208750 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 5938208750 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2338814234 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2338814234 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 149892750 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 149892750 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4181580 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4181580 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8277022984 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8277022984 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8277022984 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8277022984 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3553327 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3553327 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2362487 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2362487 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72598 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 72598 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 72123 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 72123 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 5915814 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 5915814 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 5915814 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 5915814 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.133165 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.133165 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.043387 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.043387 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.160762 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.160762 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.007875 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.007875 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.097312 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.097312 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.097312 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.097312 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12549.629843 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12549.629843 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22817.477234 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22817.477234 # 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Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 155503 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.790879 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1048852145500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.308424 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949821 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.949821 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 16322131 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16322131 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2189503 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2189503 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1567525 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1567525 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 46972 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 46972 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 49481 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 49481 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3757028 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3757028 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3757028 # number of overall hits +system.cpu1.dcache.overall_hits::total 3757028 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 113756 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 113756 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 55958 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 55958 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8862 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8862 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5884 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5884 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 169714 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 169714 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 169714 # number of overall misses +system.cpu1.dcache.overall_misses::total 169714 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1372027750 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1372027750 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1020320505 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1020320505 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80442000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 80442000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43305909 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 43305909 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2392348255 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2392348255 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2392348255 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2392348255 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2303259 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2303259 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1623483 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1623483 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 55834 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 55834 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 55365 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 55365 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3926742 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3926742 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3926742 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3926742 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049389 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049389 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034468 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.034468 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.158720 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.158720 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106277 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106277 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043220 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.043220 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043220 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.043220 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.146225 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.146225 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18233.684281 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18233.684281 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9077.183480 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9077.183480 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7359.943746 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7359.943746 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14096.351833 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14096.351833 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14096.351833 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14096.351833 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1643,62 +1658,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 444927 # number of writebacks -system.cpu1.dcache.writebacks::total 444927 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 473178 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 473178 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 102501 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 102501 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11671 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11671 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 568 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 568 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 575679 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 575679 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 575679 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 575679 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4991497250 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4991497250 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2127317766 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2127317766 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 126550250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 126550250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3045420 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3045420 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7118815016 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7118815016 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7118815016 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7118815016 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 479658500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 479658500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 907862000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 907862000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1387520500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1387520500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.133165 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.133165 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.043387 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.043387 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.160762 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.160762 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.007875 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.007875 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.097312 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.097312 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.097312 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.097312 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10548.878540 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10548.878540 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20754.117189 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20754.117189 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10843.136835 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10843.136835 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5361.654930 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5361.654930 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12365.945285 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12365.945285 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12365.945285 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12365.945285 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 106457 # number of writebacks +system.cpu1.dcache.writebacks::total 106457 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 113756 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 113756 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 55958 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 55958 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8862 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8862 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5884 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5884 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 169714 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 169714 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 169714 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 169714 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1144439250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1144439250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 906162495 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 906162495 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62718000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62718000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31536091 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31536091 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2050601745 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2050601745 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2050601745 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2050601745 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18765500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18765500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 713325000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 713325000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 732090500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 732090500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049389 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049389 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034468 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034468 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.158720 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.158720 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106277 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106277 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043220 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043220 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043220 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043220 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10060.473733 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10060.473733 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16193.618339 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16193.618339 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7077.183480 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7077.183480 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5359.634772 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5359.634772 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12082.690556 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12082.690556 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12082.690556 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12082.690556 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 7916cb036..a960683a9 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.919439 # Number of seconds simulated -sim_ticks 1919438772000 # Number of ticks simulated -final_tick 1919438772000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1919439025000 # Number of ticks simulated +final_tick 1919439025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1398299 # Simulator instruction rate (inst/s) -host_op_rate 1398299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47840414078 # Simulator tick rate (ticks/s) -host_mem_usage 314348 # Number of bytes of host memory used -host_seconds 40.12 # Real time elapsed on the host -sim_insts 56102112 # Number of instructions simulated -sim_ops 56102112 # Number of ops (including micro ops) simulated +host_inst_rate 1426339 # Simulator instruction rate (inst/s) +host_op_rate 1426339 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48799693433 # Simulator tick rate (ticks/s) +host_mem_usage 367228 # Number of bytes of host memory used +host_seconds 39.33 # Real time elapsed on the host +sim_insts 56102180 # Number of instructions simulated +sim_ops 56102180 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 850816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24875968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24875904 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25727744 # Number of bytes read from this memory +system.physmem.bytes_read::total 25727680 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 850816 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 850816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4747712 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 4747520 # Number of bytes written to this memory system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7407040 # Number of bytes written to this memory +system.physmem.bytes_written::total 7406848 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 13294 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388687 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388686 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401996 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 74183 # Number of write requests responded to by this memory +system.physmem.num_reads::total 401995 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 74180 # Number of write requests responded to by this memory system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115735 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115732 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 443263 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12960022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12959987 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13403785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13403750 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 443263 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 443263 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2473490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1385472 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3858961 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2473490 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 2473389 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1385471 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3858861 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2473389 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 443263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12960022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12959987 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1385972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17262746 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401996 # Number of read requests accepted -system.physmem.writeReqs 115735 # Number of write requests accepted -system.physmem.readBursts 401996 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115735 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25716224 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11520 # Total number of bytes read from write queue -system.physmem.bytesWritten 7405312 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25727744 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7407040 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 180 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17262610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401995 # Number of read requests accepted +system.physmem.writeReqs 115732 # Number of write requests accepted +system.physmem.readBursts 401995 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115732 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25715968 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11712 # Total number of bytes read from write queue +system.physmem.bytesWritten 7405120 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25727680 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7406848 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 183 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 132 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25161 # Per bank write bursts -system.physmem.perBankRdBursts::1 25541 # Per bank write bursts +system.physmem.perBankRdBursts::1 25539 # Per bank write bursts system.physmem.perBankRdBursts::2 25618 # Per bank write bursts -system.physmem.perBankRdBursts::3 25537 # Per bank write bursts -system.physmem.perBankRdBursts::4 24981 # Per bank write bursts -system.physmem.perBankRdBursts::5 24976 # Per bank write bursts +system.physmem.perBankRdBursts::3 25536 # Per bank write bursts +system.physmem.perBankRdBursts::4 24982 # Per bank write bursts +system.physmem.perBankRdBursts::5 24977 # Per bank write bursts system.physmem.perBankRdBursts::6 24228 # Per bank write bursts system.physmem.perBankRdBursts::7 24506 # Per bank write bursts -system.physmem.perBankRdBursts::8 25159 # Per bank write bursts -system.physmem.perBankRdBursts::9 24820 # Per bank write bursts +system.physmem.perBankRdBursts::8 25158 # Per bank write bursts +system.physmem.perBankRdBursts::9 24823 # Per bank write bursts system.physmem.perBankRdBursts::10 25363 # Per bank write bursts -system.physmem.perBankRdBursts::11 24840 # Per bank write bursts -system.physmem.perBankRdBursts::12 24420 # Per bank write bursts +system.physmem.perBankRdBursts::11 24839 # Per bank write bursts +system.physmem.perBankRdBursts::12 24418 # Per bank write bursts system.physmem.perBankRdBursts::13 25388 # Per bank write bursts system.physmem.perBankRdBursts::14 25795 # Per bank write bursts -system.physmem.perBankRdBursts::15 25483 # Per bank write bursts +system.physmem.perBankRdBursts::15 25481 # Per bank write bursts system.physmem.perBankWrBursts::0 7550 # Per bank write bursts system.physmem.perBankWrBursts::1 7529 # Per bank write bursts system.physmem.perBankWrBursts::2 7880 # Per bank write bursts @@ -78,9 +78,9 @@ system.physmem.perBankWrBursts::3 7553 # Pe system.physmem.perBankWrBursts::4 7115 # Per bank write bursts system.physmem.perBankWrBursts::5 6983 # Per bank write bursts system.physmem.perBankWrBursts::6 6321 # Per bank write bursts -system.physmem.perBankWrBursts::7 6319 # Per bank write bursts +system.physmem.perBankWrBursts::7 6315 # Per bank write bursts system.physmem.perBankWrBursts::8 7293 # Per bank write bursts -system.physmem.perBankWrBursts::9 6554 # Per bank write bursts +system.physmem.perBankWrBursts::9 6555 # Per bank write bursts system.physmem.perBankWrBursts::10 7205 # Per bank write bursts system.physmem.perBankWrBursts::11 6861 # Per bank write bursts system.physmem.perBankWrBursts::12 6964 # Per bank write bursts @@ -88,23 +88,23 @@ system.physmem.perBankWrBursts::13 7821 # Pe system.physmem.perBankWrBursts::14 7980 # Per bank write bursts system.physmem.perBankWrBursts::15 7780 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 1919426851000 # Total gap between requests +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 1919427104000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401996 # Read request sizes (log2) +system.physmem.readPktSize::6 401995 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115735 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401802 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115732 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401798 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -151,124 +151,123 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 160 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63869 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 518.585480 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 313.979775 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.923527 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14875 23.29% 23.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11515 18.03% 41.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4721 7.39% 48.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3142 4.92% 53.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3018 4.73% 58.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1863 2.92% 61.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1301 2.04% 63.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1404 2.20% 65.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22030 34.49% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63869 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5101 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.768477 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2955.016496 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5098 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::44 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63991 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 517.589786 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 312.394273 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 414.375602 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15074 23.56% 23.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11584 18.10% 41.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4587 7.17% 48.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3091 4.83% 53.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3045 4.76% 58.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1807 2.82% 61.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1323 2.07% 63.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1474 2.30% 65.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22006 34.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63991 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5109 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.644353 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2952.702952 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5106 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5101 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5101 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.683395 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.235797 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.276820 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4452 87.28% 87.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 22 0.43% 87.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 15 0.29% 88.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 224 4.39% 92.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 41 0.80% 93.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 6 0.12% 93.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 9 0.18% 93.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.14% 93.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 19 0.37% 94.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.04% 94.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.08% 94.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.04% 94.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 11 0.22% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.06% 94.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 7 0.14% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 30 0.59% 95.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 13 0.25% 95.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.06% 95.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 166 3.25% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 10 0.20% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.04% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 6 0.12% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.08% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.04% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 6 0.12% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 9 0.18% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 9 0.18% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.06% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.04% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.06% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 4 0.08% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5101 # Writes before turning the bus around for reads -system.physmem.totQLat 2117396500 # Total ticks spent queuing -system.physmem.totMemAccLat 9651446500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2009080000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5269.57 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5109 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5109 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.647289 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.199358 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.195525 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4460 87.30% 87.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 21 0.41% 87.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 12 0.23% 87.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 224 4.38% 92.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 41 0.80% 93.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 20 0.39% 93.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 7 0.14% 93.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.12% 93.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 14 0.27% 94.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.08% 94.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.06% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.02% 94.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 9 0.18% 94.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.10% 94.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.08% 94.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 25 0.49% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 9 0.18% 95.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 15 0.29% 95.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 168 3.29% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.04% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.02% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.04% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.16% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 5 0.10% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 5 0.10% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 9 0.18% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 13 0.25% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.04% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 5 0.10% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 3 0.06% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5109 # Writes before turning the bus around for reads +system.physmem.totQLat 2129492750 # Total ticks spent queuing +system.physmem.totMemAccLat 9663467750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2009060000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5299.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24019.57 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24049.72 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.40 # Average system read bandwidth in MiByte/s @@ -278,100 +277,113 @@ system.physmem.busUtil 0.13 # Da system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.42 # Average write queue length when enqueuing -system.physmem.readRowHits 360116 # Number of row buffer hits during reads -system.physmem.writeRowHits 93539 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.62 # Row buffer hit rate for reads +system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing +system.physmem.readRowHits 359991 # Number of row buffer hits during reads +system.physmem.writeRowHits 93535 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.59 # Row buffer hit rate for reads system.physmem.writeRowHitRate 80.82 # Row buffer hit rate for writes -system.physmem.avgGap 3707382.50 # Average gap between requests -system.physmem.pageHitRate 87.65 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1800046548500 # Time in different power states +system.physmem.avgGap 3707411.64 # Average gap between requests +system.physmem.pageHitRate 87.63 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1800186005000 # Time in different power states system.physmem.memoryStateTime::REF 64094160000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 55294756500 # Time in different power states +system.physmem.memoryStateTime::ACT 55155300000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 17291227 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 292357 # Transaction distribution system.membus.trans_dist::ReadResp 292357 # Transaction distribution system.membus.trans_dist::WriteReq 9649 # Transaction distribution system.membus.trans_dist::WriteResp 9649 # Transaction distribution -system.membus.trans_dist::Writeback 74183 # Transaction distribution +system.membus.trans_dist::Writeback 74180 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116727 # Transaction distribution -system.membus.trans_dist::ReadExResp 116727 # Transaction distribution +system.membus.trans_dist::ReadExReq 116726 # Transaction distribution +system.membus.trans_dist::ReadExResp 116726 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878409 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911567 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878404 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911562 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 994859 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30474496 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30519052 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 33179340 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 33179340 # Total data (bytes) -system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 32375500 # Layer occupancy (ticks) +system.membus.pkt_count::total 994854 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30474240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30518796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33179084 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 158 # Total snoops (count) +system.membus.snoop_fanout::samples 518029 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 518029 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 518029 # Request fanout histogram +system.membus.reqLayer0.occupancy 30371000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1450892000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1451093000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3751806368 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3752017868 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43113000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43114250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.344805 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.344808 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1753524887000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.344805 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084050 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084050 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1753524972000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.344808 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.084051 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.084051 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375525 # Number of tag accesses -system.iocache.tags.data_accesses 375525 # Number of data accesses +system.iocache.tags.tag_accesses 375557 # Number of tag accesses +system.iocache.tags.data_accesses 375557 # Number of data accesses system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::tsunami.ide 4 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 4 # number of WriteInvalidateReq misses system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 24523133 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 24523133 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 24523133 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 24523133 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 24523133 # number of overall miss cycles +system.iocache.overall_miss_latency::total 24523133 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41556 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41556 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000096 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000096 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 141752.213873 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 141752.213873 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 141752.213873 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 141752.213873 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 141752.213873 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 141752.213873 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,30 +400,30 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2506570306 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2506570306 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 15526633 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 15526633 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512178304 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512178304 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 15526633 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 15526633 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 15526633 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 15526633 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999904 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999904 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60323.698161 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60323.698161 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 89749.323699 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60458.661533 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60458.661533 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -430,22 +442,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9052614 # DTB read hits -system.cpu.dtb.read_misses 10356 # DTB read misses +system.cpu.dtb.read_hits 9052455 # DTB read hits +system.cpu.dtb.read_misses 10357 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728915 # DTB read accesses -system.cpu.dtb.write_hits 6349217 # DTB write hits -system.cpu.dtb.write_misses 1144 # DTB write misses +system.cpu.dtb.read_accesses 728916 # DTB read accesses +system.cpu.dtb.write_hits 6349129 # DTB write hits +system.cpu.dtb.write_misses 1143 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291933 # DTB write accesses -system.cpu.dtb.data_hits 15401831 # DTB hits +system.cpu.dtb.write_accesses 291932 # DTB write accesses +system.cpu.dtb.data_hits 15401584 # DTB hits system.cpu.dtb.data_misses 11500 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020848 # DTB accesses -system.cpu.itb.fetch_hits 4974960 # ITB hits +system.cpu.itb.fetch_hits 4974880 # ITB hits system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979970 # ITB accesses +system.cpu.itb.fetch_accesses 4979890 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -458,34 +470,34 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3838877544 # number of cpu cycles simulated +system.cpu.numCycles 3838878050 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56102112 # Number of instructions committed -system.cpu.committedOps 56102112 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 51977185 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses -system.cpu.num_func_calls 1481236 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6460933 # number of instructions that are conditional controls -system.cpu.num_int_insts 51977185 # number of integer instructions -system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 71206533 # number of times the integer registers were read -system.cpu.num_int_register_writes 38459103 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 15454487 # number of memory refs -system.cpu.num_load_insts 9089505 # Number of load instructions -system.cpu.num_store_insts 6364982 # Number of store instructions -system.cpu.num_idle_cycles 3587234430.998131 # Number of idle cycles -system.cpu.num_busy_cycles 251643113.001869 # Number of busy cycles -system.cpu.not_idle_fraction 0.065551 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934449 # Percentage of idle cycles -system.cpu.Branches 8412678 # Number of branches fetched -system.cpu.op_class::No_OpClass 3197715 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36172357 64.46% 70.16% # Class of executed instruction -system.cpu.op_class::IntMult 61004 0.11% 70.27% # Class of executed instruction +system.cpu.committedInsts 56102180 # Number of instructions committed +system.cpu.committedOps 56102180 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 51977296 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324326 # Number of float alu accesses +system.cpu.num_func_calls 1481232 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6461044 # number of instructions that are conditional controls +system.cpu.num_int_insts 51977296 # number of integer instructions +system.cpu.num_fp_insts 324326 # number of float instructions +system.cpu.num_int_register_reads 71206831 # number of times the integer registers were read +system.cpu.num_int_register_writes 38459262 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163576 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166452 # number of times the floating registers were written +system.cpu.num_mem_refs 15454224 # number of memory refs +system.cpu.num_load_insts 9089337 # Number of load instructions +system.cpu.num_store_insts 6364887 # Number of store instructions +system.cpu.num_idle_cycles 3587231475.998131 # Number of idle cycles +system.cpu.num_busy_cycles 251646574.001869 # Number of busy cycles +system.cpu.not_idle_fraction 0.065552 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934448 # Percentage of idle cycles +system.cpu.Branches 8412776 # Number of branches fetched +system.cpu.op_class::No_OpClass 3197684 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36172751 64.46% 70.16% # Class of executed instruction +system.cpu.op_class::IntMult 60997 0.11% 70.27% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction -system.cpu.op_class::FloatAdd 38087 0.07% 70.34% # Class of executed instruction +system.cpu.op_class::FloatAdd 38083 0.07% 70.34% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction @@ -511,14 +523,14 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::MemRead 9316582 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6371054 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953544 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 9316413 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6370959 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953524 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56113979 # Class of executed instruction +system.cpu.op_class::total 56114047 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212019 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212017 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl @@ -529,11 +541,11 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.40% # nu system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149118 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857248521000 96.76% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91287500 0.00% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 737179000 0.04% 96.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 61361050500 3.20% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1919438038000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1857251860000 96.76% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91366000 0.00% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 736784000 0.04% 96.80% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 61358281000 3.20% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1919438291000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -574,8 +586,8 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpctx 4175 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed system.cpu.kern.callpal::swpipl 175949 91.22% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed @@ -586,21 +598,21 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192894 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5902 # number of protection mode switches +system.cpu.kern.callpal::total 192892 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches system.cpu.kern.mode_switch::user 1742 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1912 +system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1911 system.cpu.kern.mode_good::user 1742 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.323958 # fraction of useful protection mode switches +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.323734 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392567 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46116573000 2.40% 2.40% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5192895500 0.27% 2.67% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1868128567500 97.33% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392443 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46142250000 2.40% 2.40% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5192719000 0.27% 2.67% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1868103320000 97.33% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4176 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -632,11 +644,11 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1409873 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51201 # Transaction distribution +system.iobus.trans_dist::WriteReq 51197 # Transaction distribution system.iobus.trans_dist::WriteResp 51201 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 4 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) @@ -653,23 +665,22 @@ system.iobus.pkt_count_system.bridge.master::total 33158 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2706164 # Total data (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) @@ -692,21 +703,21 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 374407689 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374412187 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42014000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42016750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 927724 # number of replacements -system.cpu.icache.tags.tagsinuse 508.304001 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55185585 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 928235 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.452170 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 39855277250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.304001 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 927651 # number of replacements +system.cpu.icache.tags.tagsinuse 508.304035 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55185726 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 928162 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.456998 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 39853785250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 508.304035 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.992781 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.992781 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -715,44 +726,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 1 system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57042375 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57042375 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 55185585 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55185585 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55185585 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55185585 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55185585 # number of overall hits -system.cpu.icache.overall_hits::total 55185585 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928395 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928395 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928395 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 928395 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 928395 # 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average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13910.293033 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13910.293033 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13910.293033 # average overall miss latency +system.cpu.icache.tags.tag_accesses 57042370 # Number of tag accesses +system.cpu.icache.tags.data_accesses 57042370 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 55185726 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55185726 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55185726 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55185726 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55185726 # number of overall hits +system.cpu.icache.overall_hits::total 55185726 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 928322 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 928322 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 928322 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 928322 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 928322 # number of overall misses +system.cpu.icache.overall_misses::total 928322 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12909129000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12909129000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12909129000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12909129000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12909129000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12909129000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56114048 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56114048 # 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average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13905.874255 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13905.874255 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13905.874255 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13905.874255 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13905.874255 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -761,135 +772,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11052282500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016545 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016545 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016545 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016545 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016545 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016545 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11904.719974 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11904.719974 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11904.719974 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11047351000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11047351000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11047351000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11047351000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016543 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016543 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016543 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11900.343846 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11900.343846 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11900.343846 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11900.343846 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11900.343846 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11900.343846 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 336239 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65296.333666 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2445823 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 401400 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.093231 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 336238 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65296.035696 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2445623 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 401399 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.092748 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 6784872750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 55553.405547 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4767.094279 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4975.833840 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.847678 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 55554.100042 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4767.074149 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4974.861505 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.847688 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072740 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.075925 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996343 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.075910 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996338 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65161 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1074 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4872 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3266 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55772 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3263 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55775 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994278 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 25933937 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 25933937 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 915081 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 814447 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1729528 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 834526 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 834526 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 25932255 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 25932255 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 915008 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 814389 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1729397 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 834448 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 834448 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 187344 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 187344 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 915081 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1001791 # 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number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1086349 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2014651 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 834448 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 834448 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304190 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304190 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 928375 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1390597 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2318972 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 928375 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1390597 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2318972 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014320 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250330 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.141581 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304189 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304189 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 928302 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1390538 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2318840 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 928302 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1390538 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2318840 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014321 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250343 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.141590 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384122 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384122 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014320 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279596 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.173396 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014320 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279596 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.173396 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73195.238453 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65072.018863 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 65450.594032 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384120 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.384120 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014321 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.279608 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.173405 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014321 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.279608 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.173405 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72884.684820 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65060.810413 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 65425.434876 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7192 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7192 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69040.824085 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66515.840330 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72884.684820 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66298.077136 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66515.840330 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -898,66 +909,66 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74183 # number of writebacks -system.cpu.l2cache.writebacks::total 74183 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74180 # number of writebacks +system.cpu.l2cache.writebacks::total 74180 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13294 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271960 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 285254 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116846 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116846 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116845 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116845 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 13294 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20916027619 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21718395619 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334183000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334183000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893390000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893390000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3227573000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3227573000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014321 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250343 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141590 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384122 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384122 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014320 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279596 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173396 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014320 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279596 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173396 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60666.917406 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52570.305376 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52947.640524 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384120 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384120 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014321 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279608 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173405 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014321 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279608 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173405 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60355.649165 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52559.008678 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52922.363928 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56538.425526 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56538.425526 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60666.917406 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53762.825468 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53991.084603 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60666.917406 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53762.825468 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53991.084603 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56674.052112 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56674.052112 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60355.649165 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53795.675516 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54012.558149 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60355.649165 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53795.675516 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54012.558149 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -965,11 +976,11 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1390084 # number of replacements +system.cpu.dcache.tags.replacements 1390025 # number of replacements system.cpu.dcache.tags.tagsinuse 511.978881 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14030288 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1390596 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.089406 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 14030084 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390537 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.089688 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.978881 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy @@ -979,72 +990,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63074137 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63074137 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7802568 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7802568 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5845442 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5845442 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183034 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183034 # 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number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15021410 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15021410 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15021410 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120516 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120516 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049467 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049467 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085963 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085963 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091429 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091429 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091429 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091429 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27121.578377 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27121.578377 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35851.398495 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35851.398495 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13255.141164 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13255.141164 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29055.226541 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29055.226541 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29055.226541 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29055.226541 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63073026 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63073026 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7802461 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7802461 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5845351 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5845351 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183030 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183030 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199225 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199225 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13647812 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13647812 # 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number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28994287250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10922192632 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10922192632 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228270750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 228270750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39916479882 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39916479882 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39916479882 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39916479882 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8871595 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8871595 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6149557 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6149557 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200245 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200245 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15021152 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15021152 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15021152 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15021152 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120512 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120512 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049468 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049468 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085970 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085970 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091427 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091427 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091427 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091427 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27119.413703 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27119.413703 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35903.935596 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35903.935596 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13259.991287 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13259.991287 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29065.256879 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29065.256879 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29065.256879 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29065.256879 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1053,54 +1064,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834526 # number of writebacks -system.cpu.dcache.writebacks::total 834526 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069193 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069193 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304207 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304207 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17214 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17214 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373400 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373400 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373400 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373400 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26734131250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26734131250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10245126618 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245126618 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193732000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193732000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36979257868 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36979257868 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36979257868 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36979257868 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011219500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011219500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435455500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435455500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120516 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120516 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049467 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049467 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085963 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085963 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091429 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091429 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091429 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091429 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25004.027570 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25004.027570 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33678.142245 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33678.142245 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11254.327873 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11254.327873 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26925.337023 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26925.337023 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26925.337023 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26925.337023 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 834448 # number of writebacks +system.cpu.dcache.writebacks::total 834448 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069134 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069134 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304206 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304206 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17215 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17215 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373340 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373340 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373340 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373340 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26730348750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26730348750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10261067368 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10261067368 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193828250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193828250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36991416118 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 36991416118 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36991416118 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36991416118 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424273000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424273000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2009178000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2009178000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3433451000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3433451000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120512 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120512 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049468 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049468 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085970 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085970 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091427 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091427 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25001.869504 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25001.869504 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33730.654123 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33730.654123 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11259.265176 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11259.265176 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26935.366419 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26935.366419 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26935.366419 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26935.366419 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1108,32 +1119,41 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 106562255 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2021905 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2021888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2021774 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2021757 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 834526 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41563 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 834448 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41564 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304190 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304190 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856770 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649068 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5505838 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59416000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142462412 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 201878412 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 201868428 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 2671296 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2424407500 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 304189 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304189 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856624 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648872 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5505496 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59411328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142453644 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 201864972 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 41913 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3195062 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.013063 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.113544 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3153325 98.69% 98.69% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41737 1.31% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3195062 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2424224500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1395179500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1395050000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2186860632 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2186768132 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |