diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
| commit | ccfdc533b9d679f1596d43d647a093885d5e74ab (patch) | |
| tree | 4c785a5e7a7e2d7244fbdbb0a316405898f99e75 /tests/quick/fs/10.linux-boot/ref/alpha | |
| parent | 460cc77d6db46eef34b14a458816084bf6097b32 (diff) | |
| download | gem5-ccfdc533b9d679f1596d43d647a093885d5e74ab.tar.xz | |
stats: Bump stats to match DRAM controller changes
This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt | 2608 | ||||
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt | 1608 |
2 files changed, 2169 insertions, 2047 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index b46274bd4..676e01409 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,133 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.961841 # Number of seconds simulated -sim_ticks 1961841175000 # Number of ticks simulated -final_tick 1961841175000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.961837 # Number of seconds simulated +sim_ticks 1961837389000 # Number of ticks simulated +final_tick 1961837389000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1272238 # Simulator instruction rate (inst/s) -host_op_rate 1272238 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42053157352 # Simulator tick rate (ticks/s) -host_mem_usage 308880 # Number of bytes of host memory used -host_seconds 46.65 # Real time elapsed on the host -sim_insts 59351715 # Number of instructions simulated -sim_ops 59351715 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 831360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24914752 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 32192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 287808 # Number of bytes read from this memory -system.physmem.bytes_read::total 28716928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 831360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 32192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7746368 # Number of bytes written to this memory -system.physmem.bytes_written::total 7746368 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12990 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 389293 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 503 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 4497 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448702 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121037 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121037 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 423765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12699678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1351188 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 16409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 146703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14637744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 423765 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 16409 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3948519 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3948519 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3948519 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 423765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12699678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1351188 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 16409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 146703 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18586263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 448702 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 121037 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 448702 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 121037 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 28716928 # Total number of bytes read from memory -system.physmem.bytesWritten 7746368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28716928 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7746368 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 3165 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 27842 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28115 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28314 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28019 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27858 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28118 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27836 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27466 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27905 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27953 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27826 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28040 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28428 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28581 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 28092 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28236 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7663 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7614 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7774 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7534 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7350 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7579 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7314 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6876 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7222 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7326 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7279 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7591 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7943 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8207 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7875 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7890 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry -system.physmem.totGap 1961833946000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 448702 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 121037 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 407897 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2995 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1539 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1437 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 99 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +host_inst_rate 1325125 # Simulator instruction rate (inst/s) +host_op_rate 1325124 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42668778131 # Simulator tick rate (ticks/s) +host_mem_usage 308960 # Number of bytes of host memory used +host_seconds 45.98 # Real time elapsed on the host +sim_insts 60926932 # Number of instructions simulated +sim_ops 60926932 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 833280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24887104 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 31680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 338432 # Number of bytes read from this memory +system.physmem.bytes_read::total 28741376 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 833280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 31680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 864960 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7742464 # Number of bytes written to this memory +system.physmem.bytes_written::total 7742464 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13020 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 388861 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 495 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 5288 # Number of read requests responded to by this memory +system.physmem.num_reads::total 449084 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120976 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120976 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 424745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12685610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1351223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 16148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 172508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14650234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 424745 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 16148 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440893 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3946537 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3946537 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3946537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 424745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12685610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1351223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 16148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 172508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18596771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 449084 # Number of read requests accepted +system.physmem.writeReqs 120976 # Number of write requests accepted +system.physmem.readBursts 449084 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120976 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28737920 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3456 # Total number of bytes read from write queue +system.physmem.bytesWritten 7741568 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28741376 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7742464 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 54 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 7077 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28167 # Per bank write bursts +system.physmem.perBankRdBursts::1 28458 # Per bank write bursts +system.physmem.perBankRdBursts::2 28055 # Per bank write bursts +system.physmem.perBankRdBursts::3 27665 # Per bank write bursts +system.physmem.perBankRdBursts::4 27762 # Per bank write bursts +system.physmem.perBankRdBursts::5 27792 # Per bank write bursts +system.physmem.perBankRdBursts::6 28261 # Per bank write bursts +system.physmem.perBankRdBursts::7 27879 # Per bank write bursts +system.physmem.perBankRdBursts::8 28077 # Per bank write bursts +system.physmem.perBankRdBursts::9 27735 # Per bank write bursts +system.physmem.perBankRdBursts::10 27671 # Per bank write bursts +system.physmem.perBankRdBursts::11 28135 # Per bank write bursts +system.physmem.perBankRdBursts::12 28173 # Per bank write bursts +system.physmem.perBankRdBursts::13 28505 # Per bank write bursts +system.physmem.perBankRdBursts::14 28655 # Per bank write bursts +system.physmem.perBankRdBursts::15 28040 # Per bank write bursts +system.physmem.perBankWrBursts::0 7931 # Per bank write bursts +system.physmem.perBankWrBursts::1 7869 # Per bank write bursts +system.physmem.perBankWrBursts::2 7539 # Per bank write bursts +system.physmem.perBankWrBursts::3 7157 # Per bank write bursts +system.physmem.perBankWrBursts::4 7275 # Per bank write bursts +system.physmem.perBankWrBursts::5 7313 # Per bank write bursts +system.physmem.perBankWrBursts::6 7748 # Per bank write bursts +system.physmem.perBankWrBursts::7 7258 # Per bank write bursts +system.physmem.perBankWrBursts::8 7316 # Per bank write bursts +system.physmem.perBankWrBursts::9 7114 # Per bank write bursts +system.physmem.perBankWrBursts::10 7078 # Per bank write bursts +system.physmem.perBankWrBursts::11 7523 # Per bank write bursts +system.physmem.perBankWrBursts::12 7676 # Per bank write bursts +system.physmem.perBankWrBursts::13 8141 # Per bank write bursts +system.physmem.perBankWrBursts::14 8336 # Per bank write bursts +system.physmem.perBankWrBursts::15 7688 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 1961830378000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 449084 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 120976 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 409885 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 10531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2315 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2316 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 977 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -139,382 +141,444 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39515 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 922.589599 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 226.543369 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2381.494153 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 13878 35.12% 35.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6056 15.33% 50.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3741 9.47% 59.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2391 6.05% 65.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1744 4.41% 70.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1425 3.61% 73.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1039 2.63% 76.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 750 1.90% 78.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 668 1.69% 80.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 592 1.50% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 528 1.34% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 459 1.16% 84.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 301 0.76% 84.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 245 0.62% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 187 0.47% 86.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 264 0.67% 86.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 137 0.35% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 111 0.28% 87.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 92 0.23% 87.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 96 0.24% 87.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 88 0.22% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 105 0.27% 88.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 1100 2.78% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 187 0.47% 91.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 132 0.33% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 88 0.22% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 54 0.14% 92.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 43 0.11% 92.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 23 0.06% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 21 0.05% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 20 0.05% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 29 0.07% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 19 0.05% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 11 0.03% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 14 0.04% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 4 0.01% 92.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 9 0.02% 92.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 6 0.02% 92.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 1 0.00% 92.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 5 0.01% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 3 0.01% 92.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 1 0.00% 92.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 6 0.02% 92.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 2 0.01% 92.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 2 0.01% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 2 0.01% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 1 0.00% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 4 0.01% 92.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 4 0.01% 92.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 2 0.01% 92.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 1 0.00% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 3 0.01% 92.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 2 0.01% 92.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 3 0.01% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 2 0.01% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 4 0.01% 92.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 2 0.01% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 1 0.00% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 1 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 1 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 1 0.00% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 2 0.01% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 3 0.01% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 1 0.00% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 2 0.01% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 1 0.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 2 0.01% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 2 0.01% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 1 0.00% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 2 0.01% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 6 0.02% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2432 6.15% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 2 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 3 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14531 2 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 2 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 2 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 2 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 242 0.61% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 10 0.03% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 6 0.02% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 6 0.02% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 4 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 2 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 4 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-17987 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39515 # Bytes accessed per row activation -system.physmem.totQLat 3750140000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12006448750 # Sum of mem lat for all requests -system.physmem.totBusLat 2243145000 # Total cycles spent in databus access -system.physmem.totBankLat 6013163750 # Total cycles spent in bank access -system.physmem.avgQLat 8359.11 # Average queueing delay per request -system.physmem.avgBankLat 13403.42 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26762.53 # Average memory access latency -system.physmem.avgRdBW 14.64 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.64 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 4884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 24 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 49252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 740.628604 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 223.502021 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1737.958624 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 17638 35.81% 35.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 7255 14.73% 50.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 4934 10.02% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2938 5.97% 66.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1843 3.74% 70.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1471 2.99% 73.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1137 2.31% 75.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 871 1.77% 77.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 749 1.52% 78.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 678 1.38% 80.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 696 1.41% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 441 0.90% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 346 0.70% 83.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 295 0.60% 83.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 325 0.66% 84.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 366 0.74% 85.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 215 0.44% 85.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 196 0.40% 86.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 200 0.41% 86.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 126 0.26% 86.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 182 0.37% 87.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 862 1.75% 88.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 228 0.46% 89.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 113 0.23% 89.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 126 0.26% 89.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 100 0.20% 90.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 86 0.17% 90.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 47 0.10% 90.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 73 0.15% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 75 0.15% 90.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 79 0.16% 90.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 32 0.06% 90.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 84 0.17% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 62 0.13% 91.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 61 0.12% 91.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 26 0.05% 91.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 60 0.12% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 59 0.12% 91.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 68 0.14% 91.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 29 0.06% 91.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 67 0.14% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 63 0.13% 91.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 57 0.12% 92.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 25 0.05% 92.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 61 0.12% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 59 0.12% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 69 0.14% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 25 0.05% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 65 0.13% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 58 0.12% 92.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 65 0.13% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 25 0.05% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 59 0.12% 93.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 53 0.11% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 71 0.14% 93.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 22 0.04% 93.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 70 0.14% 93.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 53 0.11% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 60 0.12% 93.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 27 0.05% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 61 0.12% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 53 0.11% 94.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 63 0.13% 94.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 34 0.07% 94.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 63 0.13% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 57 0.12% 94.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 62 0.13% 94.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 28 0.06% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 58 0.12% 94.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 54 0.11% 94.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 66 0.13% 95.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 361 0.73% 95.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 57 0.12% 95.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 23 0.05% 95.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 53 0.11% 96.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 23 0.05% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 58 0.12% 96.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 23 0.05% 96.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 51 0.10% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 22 0.04% 96.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 54 0.11% 96.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 39 0.08% 96.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 55 0.11% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 21 0.04% 96.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 55 0.11% 96.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 27 0.05% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 50 0.10% 97.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 22 0.04% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 54 0.11% 97.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 25 0.05% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 53 0.11% 97.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 22 0.04% 97.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 52 0.11% 97.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 23 0.05% 97.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 54 0.11% 97.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 23 0.05% 97.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 52 0.11% 97.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 23 0.05% 97.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 54 0.11% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 23 0.05% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 53 0.11% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 23 0.05% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 55 0.11% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 26 0.05% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 57 0.12% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 421 0.85% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 12 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 2 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7491 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 2 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 6 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9027 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10947 4 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 2 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12099 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12291 3 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 3 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 4 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 4 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 40 0.08% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 179 0.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 49252 # Bytes accessed per row activation +system.physmem.totQLat 6314810500 # Total ticks spent queuing +system.physmem.totMemAccLat 14686644250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2245150000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6126683750 # Total ticks spent accessing banks +system.physmem.avgQLat 14063.23 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13644.26 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 32707.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.65 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 6.90 # Average write queue length over time -system.physmem.readRowHits 433153 # Number of row buffer hits during reads -system.physmem.writeRowHits 96987 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.13 # Row buffer hit rate for writes -system.physmem.avgGap 3443390.65 # Average gap between requests -system.membus.throughput 18639952 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292620 # Transaction distribution -system.membus.trans_dist::ReadResp 292620 # Transaction distribution -system.membus.trans_dist::WriteReq 12397 # Transaction distribution -system.membus.trans_dist::WriteResp 12397 # Transaction distribution -system.membus.trans_dist::Writeback 121037 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4186 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 858 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3168 # Transaction distribution -system.membus.trans_dist::ReadExReq 163944 # Transaction distribution -system.membus.trans_dist::ReadExResp 163855 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39192 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 902644 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 941836 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124669 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124669 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1066505 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68594 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31155200 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31223794 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5308096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36531890 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36531890 # Total data (bytes) -system.membus.snoop_data_through_bus 36736 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 39129000 # Layer occupancy (ticks) +system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.09 # Average write queue length when enqueuing +system.physmem.readRowHits 424855 # Number of row buffer hits during reads +system.physmem.writeRowHits 95885 # Number of row buffer hits during writes +system.physmem.readRowHitRate 94.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.26 # Row buffer hit rate for writes +system.physmem.avgGap 3441445.42 # Average gap between requests +system.physmem.pageHitRate 91.36 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.53 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 18657286 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292799 # Transaction distribution +system.membus.trans_dist::ReadResp 292799 # Transaction distribution +system.membus.trans_dist::WriteReq 14111 # Transaction distribution +system.membus.trans_dist::WriteResp 14111 # Transaction distribution +system.membus.trans_dist::Writeback 120976 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16467 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11554 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7080 # Transaction distribution +system.membus.trans_dist::ReadExReq 164905 # Transaction distribution +system.membus.trans_dist::ReadExResp 164053 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42620 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 930997 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 973617 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1098283 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 82306 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31175680 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31257986 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308160 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5308160 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36566146 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36566146 # Total data (bytes) +system.membus.snoop_data_through_bus 36416 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 43190000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1559666750 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1566162500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3812357322 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3824002662 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376257250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376301000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 341780 # number of replacements -system.l2c.tags.tagsinuse 65282.130402 # Cycle average of tags in use -system.l2c.tags.total_refs 2491702 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 406958 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.122750 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8422138750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55415.399962 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4783.359658 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4905.357732 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 160.897835 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 17.115216 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.845572 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.072988 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.074850 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002455 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000261 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996126 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 908184 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 776732 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 79667 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 28709 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1793292 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 820882 # number of Writeback hits -system.l2c.Writeback_hits::total 820882 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 160 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 41 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 201 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 18 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 18 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 36 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 176285 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 7535 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183820 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 908184 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 953017 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 79667 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 36244 # number of demand (read+write) hits -system.l2c.demand_hits::total 1977112 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 908184 # number of overall hits -system.l2c.overall_hits::cpu0.data 953017 # number of overall hits -system.l2c.overall_hits::cpu1.inst 79667 # number of overall hits -system.l2c.overall_hits::cpu1.data 36244 # number of overall hits -system.l2c.overall_hits::total 1977112 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 12993 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271572 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 511 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 178 # 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average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54067.075692 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62559.226968 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 54367.458789 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66696.016705 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 51041.000334 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67922.465209 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63024.342870 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 51693.177703 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66696.016705 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 51041.000334 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67922.465209 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63024.342870 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 51693.177703 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57451.052944 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63520.225475 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 57700.510194 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63928.725730 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53726.370751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64197.979798 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63681.296716 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 54193.418969 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63928.725730 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53726.370751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64197.979798 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63681.296716 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 54193.418969 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -649,39 +713,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41698 # number of replacements -system.iocache.tags.tagsinuse 0.564923 # Cycle average of tags in use +system.iocache.tags.replacements 41694 # number of replacements +system.iocache.tags.tagsinuse 0.571330 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1754539957000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.564923 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035308 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035308 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses -system.iocache.ReadReq_misses::total 178 # number of ReadReq misses +system.iocache.tags.warmup_cycle 1754532770000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.571330 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035708 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035708 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses -system.iocache.demand_misses::total 41730 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses -system.iocache.overall_misses::total 41730 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21912883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21912883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10439154521 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10439154521 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10461067404 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10461067404 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10461067404 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10461067404 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21248383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21248383 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12952701816 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12952701816 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 12973950199 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 12973950199 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 12973950199 # number of overall miss cycles +system.iocache.overall_miss_latency::total 12973950199 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -690,40 +754,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123106.084270 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123106.084270 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251231.096482 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 251231.096482 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 250684.577139 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 250684.577139 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 250684.577139 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 250684.577139 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 274830 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122117.143678 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122117.143678 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 311722.704467 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 311722.704467 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 310932.037555 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 310932.037555 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 310932.037555 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 310932.037555 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 405757 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27442 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 29467 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.014941 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.769878 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12655383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12655383 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8277077521 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8277077521 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8289732904 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8289732904 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8289732904 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8289732904 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12199383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12199383 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10790464816 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10790464816 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10802664199 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10802664199 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10802664199 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10802664199 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -732,14 +796,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71097.657303 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71097.657303 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199198.053547 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 199198.053547 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198651.639204 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 198651.639204 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198651.639204 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 198651.639204 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70111.396552 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 259685.810936 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 259685.810936 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 258895.273906 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 258895.273906 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 258895.273906 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 258895.273906 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -757,22 +821,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8725663 # DTB read hits +system.cpu0.dtb.read_hits 7530179 # DTB read hits system.cpu0.dtb.read_misses 7765 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 6139453 # DTB write hits +system.cpu0.dtb.write_hits 5118893 # DTB write hits system.cpu0.dtb.write_misses 910 # DTB write misses system.cpu0.dtb.write_acv 133 # DTB write access violations system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 14865116 # DTB hits +system.cpu0.dtb.data_hits 12649072 # DTB hits system.cpu0.dtb.data_misses 8675 # DTB misses system.cpu0.dtb.data_acv 343 # DTB access violations system.cpu0.dtb.data_accesses 726664 # DTB accesses -system.cpu0.itb.fetch_hits 4015307 # ITB hits +system.cpu0.itb.fetch_hits 3650586 # ITB hits system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 4019291 # ITB accesses +system.cpu0.itb.fetch_accesses 3654570 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -785,55 +849,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3923682350 # number of cpu cycles simulated +system.cpu0.numCycles 3923674778 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 54601969 # Number of instructions committed -system.cpu0.committedOps 54601969 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 50544405 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 297630 # Number of float alu accesses -system.cpu0.num_func_calls 1438477 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6291508 # number of instructions that are conditional controls -system.cpu0.num_int_insts 50544405 # number of integer instructions -system.cpu0.num_fp_insts 297630 # number of float instructions -system.cpu0.num_int_register_reads 69247284 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37427910 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 145753 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 148838 # number of times the floating registers were written -system.cpu0.num_mem_refs 14912078 # number of memory refs -system.cpu0.num_load_insts 8757685 # Number of load instructions -system.cpu0.num_store_insts 6154393 # Number of store instructions -system.cpu0.num_idle_cycles 3674902109.498127 # Number of idle cycles -system.cpu0.num_busy_cycles 248780240.501873 # Number of busy cycles -system.cpu0.not_idle_fraction 0.063405 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.936595 # Percentage of idle cycles +system.cpu0.committedInsts 47959136 # Number of instructions committed +system.cpu0.committedOps 47959136 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44491652 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 211334 # Number of float alu accesses +system.cpu0.num_func_calls 1203195 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5632072 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44491652 # number of integer instructions +system.cpu0.num_fp_insts 211334 # number of float instructions +system.cpu0.num_int_register_reads 61191395 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33136181 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 103249 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 105046 # number of times the floating registers were written +system.cpu0.num_mem_refs 12690027 # number of memory refs +system.cpu0.num_load_insts 7557911 # Number of load instructions +system.cpu0.num_store_insts 5132116 # Number of store instructions +system.cpu0.num_idle_cycles 3700191977.998114 # Number of idle cycles +system.cpu0.num_busy_cycles 223482800.001886 # Number of busy cycles +system.cpu0.not_idle_fraction 0.056958 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.943042 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 204697 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 73289 40.68% 40.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.07% 40.75% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1975 1.10% 41.85% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 6 0.00% 41.85% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 104766 58.15% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 180167 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71920 49.28% 49.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.09% 49.37% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1975 1.35% 50.72% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71914 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 145946 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1899196330000 96.81% 96.81% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 95025500 0.00% 96.81% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 769055500 0.04% 96.85% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 5164500 0.00% 96.85% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 61774827500 3.15% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1961840403000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981321 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6812 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 165228 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56779 40.23% 40.23% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.33% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1974 1.40% 41.72% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 435 0.31% 42.03% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 81809 57.97% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141128 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56269 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1974 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 435 0.38% 51.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55834 48.70% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114643 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1902446374500 96.97% 96.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 95095000 0.00% 96.98% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 766988500 0.04% 97.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 322426000 0.02% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 58205747500 2.97% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1961836631500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.991018 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.686425 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810060 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.682492 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.812333 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed @@ -865,37 +929,37 @@ system.cpu0.kern.syscall::144 2 0.85% 99.15% # nu system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 88 0.05% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3942 2.08% 2.13% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.16% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.16% # number of callpals executed -system.cpu0.kern.callpal::swpipl 173212 91.45% 93.61% # number of callpals executed -system.cpu0.kern.callpal::rdps 6702 3.54% 97.15% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.15% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 97.16% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 97.16% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.16% # number of callpals executed -system.cpu0.kern.callpal::rti 4842 2.56% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.21% 99.93% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 189397 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7440 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1369 # number of protection mode switches +system.cpu0.kern.callpal::wripir 517 0.35% 0.35% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.35% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.35% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.35% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3084 2.06% 2.41% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.45% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134176 89.75% 92.20% # number of callpals executed +system.cpu0.kern.callpal::rdps 6701 4.48% 96.68% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.69% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed +system.cpu0.kern.callpal::rti 4411 2.95% 99.64% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 149500 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7010 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1373 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1368 -system.cpu0.kern.mode_good::user 1369 +system.cpu0.kern.mode_good::kernel 1372 +system.cpu0.kern.mode_good::user 1373 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.183871 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.195720 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.310705 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958025785500 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3814613000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.327448 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958037655500 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3798971500 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3943 # number of times the context was actually changed +system.cpu0.kern.swap_context 3085 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -927,47 +991,47 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 105075557 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2099191 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2099176 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12397 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12397 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 820882 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 4248 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 894 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 5142 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 348581 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 307031 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1842377 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3534341 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 160357 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 115223 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5652298 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58955328 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 137106504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 5131392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4050090 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 205243314 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 205232754 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 908800 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4911962990 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 742500 # Layer occupancy (ticks) +system.toL2Bus.throughput 103908079 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2101783 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2101768 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14111 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14111 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 792069 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16689 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11613 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28302 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 338794 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297244 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1394675 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3121086 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 636287 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 464415 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5616463 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44628928 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119461456 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20361152 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17008562 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 201460098 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 201449794 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 2400960 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4792055385 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4148559004 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3140628756 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 6195378103 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5519397625 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 360929992 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 206344318 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1431747492 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 796288703 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1391673 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7377 # Transaction distribution -system.iobus.trans_dist::ReadResp 7377 # Transaction distribution -system.iobus.trans_dist::WriteReq 53949 # Transaction distribution -system.iobus.trans_dist::WriteResp 53949 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10582 # Packet count per connected master and slave (bytes) +system.iobus.throughput 1398649 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7373 # Transaction distribution +system.iobus.trans_dist::ReadResp 7373 # Transaction distribution +system.iobus.trans_dist::WriteReq 55663 # Transaction distribution +system.iobus.trans_dist::WriteResp 55663 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14010 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -979,11 +1043,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 39192 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 122652 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42620 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 126072 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 56040 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -995,12 +1059,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 68594 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2730242 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2730242 # Total data (bytes) -system.iobus.reqLayer0.occupancy 9937000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 82306 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2743922 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2743922 # Total data (bytes) +system.iobus.reqLayer0.occupancy 13365000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1022,59 +1086,59 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378297154 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 377760199 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 26795000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28509000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43124750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42664000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 920572 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.501962 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 53689788 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 921084 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 58.289785 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 39101383250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.501962 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993168 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.993168 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 53689788 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 53689788 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 53689788 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 53689788 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 53689788 # number of overall hits -system.cpu0.icache.overall_hits::total 53689788 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 921200 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 921200 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 921200 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 921200 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 921200 # number of overall misses -system.cpu0.icache.overall_misses::total 921200 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12937764004 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12937764004 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12937764004 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12937764004 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12937764004 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12937764004 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 54610988 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 54610988 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 54610988 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 54610988 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 54610988 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 54610988 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016868 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.016868 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016868 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.016868 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016868 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.016868 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14044.468089 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14044.468089 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14044.468089 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14044.468089 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14044.468089 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14044.468089 # average overall miss latency +system.cpu0.icache.tags.replacements 696718 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.401211 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47270807 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 697230 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.798011 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 40083254250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.401211 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992971 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992971 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 47270807 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47270807 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47270807 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47270807 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47270807 # number of overall hits +system.cpu0.icache.overall_hits::total 47270807 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 697348 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 697348 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 697348 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 697348 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 697348 # number of overall misses +system.cpu0.icache.overall_misses::total 697348 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9977651756 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9977651756 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9977651756 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9977651756 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9977651756 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9977651756 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47968155 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47968155 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47968155 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47968155 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47968155 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47968155 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014538 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014538 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014538 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014538 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014538 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014538 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14307.995084 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14307.995084 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14307.995084 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14307.995084 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14307.995084 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14307.995084 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1083,112 +1147,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 921200 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 921200 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 921200 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 921200 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 921200 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 921200 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11089045996 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11089045996 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11089045996 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11089045996 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11089045996 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11089045996 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016868 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016868 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016868 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016868 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016868 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016868 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12037.609635 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12037.609635 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12037.609635 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 697348 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 697348 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 697348 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 697348 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 697348 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 697348 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8577830244 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8577830244 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8577830244 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8577830244 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8577830244 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8577830244 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014538 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014538 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014538 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014538 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014538 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014538 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12300.645078 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12300.645078 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12300.645078 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12300.645078 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12300.645078 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12300.645078 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1349865 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.612721 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13528796 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1350377 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 10.018533 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 105754250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.612721 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.989478 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.989478 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7507195 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7507195 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5646858 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5646858 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 177791 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 177791 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 193304 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 193304 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 13154053 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 13154053 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 13154053 # number of overall hits -system.cpu0.dcache.overall_hits::total 13154053 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1040730 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1040730 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 297940 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 297940 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16884 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16884 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 399 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 399 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1338670 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1338670 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1338670 # number of overall misses -system.cpu0.dcache.overall_misses::total 1338670 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27787431256 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 27787431256 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10644315314 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10644315314 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 223091000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 223091000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2495533 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 2495533 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 38431746570 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 38431746570 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 38431746570 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 38431746570 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8547925 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8547925 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5944798 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5944798 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194675 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 194675 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 193703 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 193703 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14492723 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14492723 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14492723 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14492723 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.121752 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.121752 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050118 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.050118 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086729 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086729 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002060 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002060 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092368 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.092368 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092368 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092368 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26699.942594 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26699.942594 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35726.372135 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 35726.372135 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13213.160389 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13213.160389 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6254.468672 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6254.468672 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 28708.902545 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 28708.902545 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 28708.902545 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 28708.902545 # average overall miss latency +system.cpu0.dcache.tags.replacements 1186136 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.274988 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11457169 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1186648 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.655070 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 107469250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.274988 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986865 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986865 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6449366 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6449366 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4705451 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4705451 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140478 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 140478 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147984 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 147984 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11154817 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11154817 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11154817 # number of overall hits +system.cpu0.dcache.overall_hits::total 11154817 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 939343 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 939343 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 256772 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 256772 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13639 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13639 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5591 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5591 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1196115 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1196115 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1196115 # number of overall misses +system.cpu0.dcache.overall_misses::total 1196115 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27074316502 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 27074316502 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10448735954 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10448735954 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 148878750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 148878750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43336419 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 43336419 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 37523052456 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 37523052456 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 37523052456 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 37523052456 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7388709 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7388709 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4962223 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4962223 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154117 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 154117 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153575 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153575 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12350932 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12350932 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12350932 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12350932 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127132 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127132 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051745 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051745 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088498 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088498 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036406 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036406 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096844 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.096844 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096844 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.096844 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28822.609528 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28822.609528 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40692.661014 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40692.661014 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10915.664638 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10915.664638 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7751.103380 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7751.103380 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31370.773258 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 31370.773258 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31370.773258 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31370.773258 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1197,62 +1261,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 798646 # number of writebacks -system.cpu0.dcache.writebacks::total 798646 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1040730 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1040730 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297940 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 297940 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16884 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16884 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 399 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 399 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1338670 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1338670 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1338670 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1338670 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25571734744 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25571734744 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9990567686 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9990567686 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 189290000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 189290000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1697467 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1697467 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35562302430 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 35562302430 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35562302430 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 35562302430 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465580500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465580500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2094321000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2094321000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3559901500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3559901500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.121752 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.121752 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050118 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050118 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086729 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086729 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002060 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002060 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092368 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092368 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092368 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092368 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24570.959561 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24570.959561 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33532.146358 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33532.146358 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11211.205875 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11211.205875 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4254.303258 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4254.303258 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26565.398814 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26565.398814 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26565.398814 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26565.398814 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 682430 # number of writebacks +system.cpu0.dcache.writebacks::total 682430 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939343 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 939343 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256772 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 256772 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13639 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13639 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5590 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5590 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1196115 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1196115 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1196115 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1196115 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25063726498 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25063726498 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9880374046 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9880374046 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121588250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121588250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32154581 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32154581 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34944100544 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 34944100544 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34944100544 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 34944100544 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465575000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465575000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2284904500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2284904500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3750479500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3750479500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127132 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127132 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051745 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051745 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088498 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088498 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036399 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036399 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096844 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.096844 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096844 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.096844 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26682.187974 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26682.187974 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38479.172363 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38479.172363 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8914.748149 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8914.748149 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5752.161181 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5752.161181 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29214.666269 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29214.666269 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29214.666269 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29214.666269 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1264,22 +1328,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 957039 # DTB read hits +system.cpu1.dtb.read_hits 2385380 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 556340 # DTB write hits +system.cpu1.dtb.write_hits 1707840 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 1513379 # DTB hits +system.cpu1.dtb.data_hits 4093220 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1320031 # ITB hits +system.cpu1.itb.fetch_hits 1814538 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1321095 # ITB accesses +system.cpu1.itb.fetch_accesses 1815602 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1292,51 +1356,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3921887017 # number of cpu cycles simulated +system.cpu1.numCycles 3921880904 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 4749746 # Number of instructions committed -system.cpu1.committedOps 4749746 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 4446088 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 30301 # Number of float alu accesses -system.cpu1.num_func_calls 145582 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 455512 # number of instructions that are conditional controls -system.cpu1.num_int_insts 4446088 # number of integer instructions -system.cpu1.num_fp_insts 30301 # number of float instructions -system.cpu1.num_int_register_reads 6169769 # number of times the integer registers were read -system.cpu1.num_int_register_writes 3384887 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 19629 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 19442 # number of times the floating registers were written -system.cpu1.num_mem_refs 1521715 # number of memory refs -system.cpu1.num_load_insts 962201 # Number of load instructions -system.cpu1.num_store_insts 559514 # Number of store instructions -system.cpu1.num_idle_cycles 3904242469.193159 # Number of idle cycles -system.cpu1.num_busy_cycles 17644547.806841 # Number of busy cycles -system.cpu1.not_idle_fraction 0.004499 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.995501 # Percentage of idle cycles +system.cpu1.committedInsts 12967796 # Number of instructions committed +system.cpu1.committedOps 12967796 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 11946960 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 174217 # Number of float alu accesses +system.cpu1.num_func_calls 410982 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1284197 # number of instructions that are conditional controls +system.cpu1.num_int_insts 11946960 # number of integer instructions +system.cpu1.num_fp_insts 174217 # number of float instructions +system.cpu1.num_int_register_reads 16422187 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8787604 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 90513 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 92474 # number of times the floating registers were written +system.cpu1.num_mem_refs 4116157 # number of memory refs +system.cpu1.num_load_insts 2399132 # Number of load instructions +system.cpu1.num_store_insts 1717025 # Number of store instructions +system.cpu1.num_idle_cycles 3872385828.119347 # Number of idle cycles +system.cpu1.num_busy_cycles 49495075.880653 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012620 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987380 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2329 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 33659 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 8392 30.97% 30.97% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1970 7.27% 38.24% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 88 0.32% 38.57% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 16645 61.43% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 27095 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 8384 44.74% 44.74% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1970 10.51% 55.26% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 88 0.47% 55.73% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 8296 44.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 18738 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1917649813500 97.79% 97.79% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 700167000 0.04% 97.83% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 60318500 0.00% 97.83% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 42533179500 2.17% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1960943478500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999047 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2742 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78306 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26634 38.27% 38.27% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1969 2.83% 41.10% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 517 0.74% 41.84% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40476 58.16% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69596 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25767 48.16% 48.16% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1969 3.68% 51.84% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 517 0.97% 52.81% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25250 47.19% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53503 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909643308000 97.38% 97.38% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 700945000 0.04% 97.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 361639500 0.02% 97.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 50234529500 2.56% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1960940422000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.967448 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.498408 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.691567 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.623826 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.768765 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -1352,81 +1416,81 @@ system.cpu1.kern.syscall::74 9 9.78% 96.74% # nu system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 6 0.02% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 283 1.02% 1.06% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 1.07% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.03% 1.09% # number of callpals executed -system.cpu1.kern.callpal::swpipl 22604 81.73% 82.82% # number of callpals executed -system.cpu1.kern.callpal::rdps 2147 7.76% 90.59% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 90.59% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 90.60% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 90.61% # number of callpals executed -system.cpu1.kern.callpal::rti 2432 8.79% 99.41% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.44% 99.84% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.15% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 435 0.61% 0.61% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2001 2.78% 3.39% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.40% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.41% # number of callpals executed +system.cpu1.kern.callpal::swpipl 63390 88.19% 91.60% # number of callpals executed +system.cpu1.kern.callpal::rdps 2146 2.99% 94.59% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.59% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 94.59% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed +system.cpu1.kern.callpal::rti 3719 5.17% 99.77% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 27656 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 652 # number of protection mode switches -system.cpu1.kern.mode_switch::user 367 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2065 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 379 -system.cpu1.kern.mode_good::user 367 -system.cpu1.kern.mode_good::idle 12 -system.cpu1.kern.mode_switch_good::kernel 0.581288 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 71875 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1956 # number of protection mode switches +system.cpu1.kern.mode_switch::user 368 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2907 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 809 +system.cpu1.kern.mode_good::user 368 +system.cpu1.kern.mode_good::idle 441 +system.cpu1.kern.mode_switch_good::kernel 0.413599 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.005811 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.245785 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 2892019000 0.15% 0.15% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1487213000 0.08% 0.22% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1955685685000 99.78% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 284 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 79630 # number of replacements -system.cpu1.icache.tags.tagsinuse 421.213832 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 4672446 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 80140 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 58.303544 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1959882431000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 421.213832 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.822683 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.822683 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 4672446 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 4672446 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 4672446 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 4672446 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 4672446 # number of overall hits -system.cpu1.icache.overall_hits::total 4672446 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 80179 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 80179 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 80179 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 80179 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 80179 # number of overall misses -system.cpu1.icache.overall_misses::total 80179 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1082064992 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1082064992 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1082064992 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1082064992 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1082064992 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1082064992 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 4752625 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 4752625 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 4752625 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 4752625 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 4752625 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 4752625 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016870 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.016870 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016870 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.016870 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016870 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.016870 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13495.615959 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13495.615959 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13495.615959 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13495.615959 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13495.615959 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13495.615959 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.151703 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.309310 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17986321500 0.92% 0.92% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1483696000 0.08% 0.99% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1940592550000 99.01% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2002 # number of times the context was actually changed +system.cpu1.icache.tags.replacements 317593 # number of replacements +system.cpu1.icache.tags.tagsinuse 446.454785 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12652531 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 318104 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.774825 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1959964216000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.454785 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871982 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.871982 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 12652531 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12652531 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12652531 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12652531 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12652531 # number of overall hits +system.cpu1.icache.overall_hits::total 12652531 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 318144 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 318144 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 318144 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 318144 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 318144 # number of overall misses +system.cpu1.icache.overall_misses::total 318144 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4187615492 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4187615492 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4187615492 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4187615492 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4187615492 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4187615492 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 12970675 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 12970675 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 12970675 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 12970675 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 12970675 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 12970675 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024528 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024528 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024528 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024528 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024528 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024528 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13162.641735 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13162.641735 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13162.641735 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13162.641735 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13162.641735 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13162.641735 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1435,112 +1499,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 80179 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 80179 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 80179 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 80179 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 80179 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 80179 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 921458008 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 921458008 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 921458008 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 921458008 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 921458008 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 921458008 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016870 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016870 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016870 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.016870 # 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number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 318144 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 318144 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 318144 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 318144 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3551128508 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3551128508 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3551128508 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3551128508 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3551128508 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3551128508 # 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average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11162.016282 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11162.016282 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 40890 # number of replacements -system.cpu1.dcache.tags.tagsinuse 416.865345 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 1457107 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 41228 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.342655 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1941571028000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 416.865345 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.814190 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.814190 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 917421 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 917421 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 531046 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 531046 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 9250 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 9250 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 9554 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 9554 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1448467 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1448467 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1448467 # number of overall hits -system.cpu1.dcache.overall_hits::total 1448467 # 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Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949618 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.949618 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2222453 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2222453 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1596000 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1596000 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48034 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 48034 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50617 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50617 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3818453 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3818453 # 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average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7351.224805 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14118.788545 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14118.788545 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14118.788545 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14118.788545 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1549,62 +1613,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 22236 # number of writebacks -system.cpu1.dcache.writebacks::total 22236 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 31971 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 31971 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 13337 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 13337 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 850 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 850 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 495 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 495 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 45308 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 45308 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 45308 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 45308 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 334917000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 334917000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 427133505 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 427133505 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 7677750 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 7677750 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2708927 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2708927 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 762050505 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 762050505 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 762050505 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 762050505 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18768000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18768000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 527878500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 527878500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 546646500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 546646500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033675 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033675 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024499 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.024499 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.084158 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.084158 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.049259 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.049259 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030331 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030331 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030331 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030331 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10475.649808 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10475.649808 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32026.205668 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32026.205668 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9032.647059 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9032.647059 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5472.579798 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5472.579798 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16819.336651 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16819.336651 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16819.336651 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16819.336651 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 109639 # number of writebacks +system.cpu1.dcache.writebacks::total 109639 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116850 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 116850 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57159 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 57159 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9086 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9086 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6023 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 6023 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 174009 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 174009 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 174009 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 174009 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1177711751 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1177711751 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 928682973 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 928682973 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 64347500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 64347500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32228573 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32228573 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2106394724 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2106394724 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2106394724 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2106394724 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18769000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18769000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 718428000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 718428000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 737197000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 737197000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049951 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049951 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034576 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034576 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.159069 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.159069 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106338 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106338 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043584 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043584 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043584 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043584 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10078.833984 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10078.833984 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16247.362148 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16247.362148 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7082.049307 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7082.049307 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5350.916985 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5350.916985 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12105.090679 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12105.090679 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12105.090679 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12105.090679 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 0de871519..479e1f707 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,123 +1,125 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.918473 # Number of seconds simulated -sim_ticks 1918473094000 # Number of ticks simulated -final_tick 1918473094000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.920428 # Number of seconds simulated +sim_ticks 1920428041000 # Number of ticks simulated +final_tick 1920428041000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 948634 # Simulator instruction rate (inst/s) -host_op_rate 948634 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32389976926 # Simulator tick rate (ticks/s) -host_mem_usage 304780 # Number of bytes of host memory used -host_seconds 59.23 # Real time elapsed on the host -sim_insts 56188014 # Number of instructions simulated -sim_ops 56188014 # Number of ops (including micro ops) simulated +host_inst_rate 1218375 # Simulator instruction rate (inst/s) +host_op_rate 1218374 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41646226437 # Simulator tick rate (ticks/s) +host_mem_usage 305884 # Number of bytes of host memory used +host_seconds 46.11 # Real time elapsed on the host +sim_insts 56182750 # Number of instructions simulated +sim_ops 56182750 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24847488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24846912 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28350528 # Number of bytes read from this memory +system.physmem.bytes_read::total 28349952 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 850688 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 850688 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7389888 # Number of bytes written to this memory -system.physmem.bytes_written::total 7389888 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7389824 # Number of bytes written to this memory +system.physmem.bytes_written::total 7389824 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 13292 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388242 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388233 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 442977 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115467 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115467 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 443419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12951700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1382533 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14777652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 443419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3851963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3851963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3851963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 443419 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12951700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1382533 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18629615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 442977 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 115467 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 442977 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 115467 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 28350528 # Total number of bytes read from memory -system.physmem.bytesWritten 7389888 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28350528 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7389888 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 27963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28090 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28297 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28045 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27408 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27547 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 26911 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 26768 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27805 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27257 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27713 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27329 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27431 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28072 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 28025 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28266 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7723 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7594 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7833 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7543 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7011 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6984 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6467 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6223 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7221 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6661 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7097 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6780 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7013 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7721 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7774 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7822 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1918461222000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 442977 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 115467 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 402244 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7043 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3263 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3011 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1562 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see +system.physmem.num_reads::total 442968 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115466 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115466 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442968 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12938216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1381125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14762309 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3848009 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3848009 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3848009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12938216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1381125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18610318 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 442968 # Number of read requests accepted +system.physmem.writeReqs 115466 # Number of write requests accepted +system.physmem.readBursts 442968 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115466 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28346688 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3264 # Total number of bytes read from write queue +system.physmem.bytesWritten 7389440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28349952 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7389824 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 51 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 27966 # Per bank write bursts +system.physmem.perBankRdBursts::1 28089 # Per bank write bursts +system.physmem.perBankRdBursts::2 28297 # Per bank write bursts +system.physmem.perBankRdBursts::3 28053 # Per bank write bursts +system.physmem.perBankRdBursts::4 27407 # Per bank write bursts +system.physmem.perBankRdBursts::5 27545 # Per bank write bursts +system.physmem.perBankRdBursts::6 26911 # Per bank write bursts +system.physmem.perBankRdBursts::7 26762 # Per bank write bursts +system.physmem.perBankRdBursts::8 27807 # Per bank write bursts +system.physmem.perBankRdBursts::9 27255 # Per bank write bursts +system.physmem.perBankRdBursts::10 27714 # Per bank write bursts +system.physmem.perBankRdBursts::11 27327 # Per bank write bursts +system.physmem.perBankRdBursts::12 27431 # Per bank write bursts +system.physmem.perBankRdBursts::13 28073 # Per bank write bursts +system.physmem.perBankRdBursts::14 28024 # Per bank write bursts +system.physmem.perBankRdBursts::15 28256 # Per bank write bursts +system.physmem.perBankWrBursts::0 7722 # Per bank write bursts +system.physmem.perBankWrBursts::1 7593 # Per bank write bursts +system.physmem.perBankWrBursts::2 7833 # Per bank write bursts +system.physmem.perBankWrBursts::3 7543 # Per bank write bursts +system.physmem.perBankWrBursts::4 7010 # Per bank write bursts +system.physmem.perBankWrBursts::5 6982 # Per bank write bursts +system.physmem.perBankWrBursts::6 6469 # Per bank write bursts +system.physmem.perBankWrBursts::7 6223 # Per bank write bursts +system.physmem.perBankWrBursts::8 7224 # Per bank write bursts +system.physmem.perBankWrBursts::9 6661 # Per bank write bursts +system.physmem.perBankWrBursts::10 7099 # Per bank write bursts +system.physmem.perBankWrBursts::11 6780 # Per bank write bursts +system.physmem.perBankWrBursts::12 7009 # Per bank write bursts +system.physmem.perBankWrBursts::13 7722 # Per bank write bursts +system.physmem.perBankWrBursts::14 7773 # Per bank write bursts +system.physmem.perBankWrBursts::15 7817 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 1920416169000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 442968 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 115466 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 403787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 10503 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2702 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1381 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1335 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1436 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1247 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 965 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 958 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 953 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -129,233 +131,289 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37132 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 962.378541 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 229.718891 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2449.750918 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 13161 35.44% 35.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 5591 15.06% 50.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3357 9.04% 59.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2263 6.09% 65.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1589 4.28% 69.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1303 3.51% 73.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 971 2.61% 76.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 731 1.97% 78.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 647 1.74% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 569 1.53% 81.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 543 1.46% 82.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 425 1.14% 83.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 308 0.83% 84.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 237 0.64% 85.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 163 0.44% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 235 0.63% 86.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 101 0.27% 86.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 93 0.25% 86.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 98 0.26% 87.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 98 0.26% 87.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 85 0.23% 87.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 107 0.29% 88.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 1046 2.82% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 157 0.42% 91.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 87 0.23% 91.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 55 0.15% 91.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 46 0.12% 91.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 40 0.11% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 31 0.08% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 18 0.05% 91.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 16 0.04% 92.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 26 0.07% 92.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 19 0.05% 92.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 8 0.02% 92.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 8 0.02% 92.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 15 0.04% 92.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 14 0.04% 92.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 3 0.01% 92.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 6 0.02% 92.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 4 0.01% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 4 0.01% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 1 0.00% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 3 0.01% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 2 0.01% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 4 0.01% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 2 0.01% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 1 0.00% 92.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 3 0.01% 92.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 4 0.01% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 3 0.01% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 3 0.01% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 1 0.00% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 4 0.01% 92.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 1 0.00% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 1 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 1 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 2 0.01% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 3 0.01% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 2 0.01% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.00% 92.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 4 0.01% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 2 0.01% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.01% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 1 0.00% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 2 0.01% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 2 0.01% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 1 0.00% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 1 0.00% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 3 0.01% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 2 0.01% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 3 0.01% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 3 0.01% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 4 0.01% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2437 6.56% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 2 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 242 0.65% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 9 0.02% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 9 0.02% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 3 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 3 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 2 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 4 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 3 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17347 2 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37132 # Bytes accessed per row activation -system.physmem.totQLat 3659130000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11798708750 # Sum of mem lat for all requests -system.physmem.totBusLat 2214635000 # Total cycles spent in databus access -system.physmem.totBankLat 5924943750 # Total cycles spent in bank access -system.physmem.avgQLat 8261.25 # Average queueing delay per request -system.physmem.avgBankLat 13376.80 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26638.04 # Average memory access latency -system.physmem.avgRdBW 14.78 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.78 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.85 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 4636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 46254 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 772.575777 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 229.901205 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1785.674907 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 16351 35.35% 35.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 6669 14.42% 49.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 4598 9.94% 59.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2705 5.85% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1760 3.81% 69.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1480 3.20% 72.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1070 2.31% 74.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 848 1.83% 76.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 733 1.58% 78.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 614 1.33% 79.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 629 1.36% 80.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 417 0.90% 81.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 327 0.71% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 305 0.66% 83.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 281 0.61% 83.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 335 0.72% 84.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 208 0.45% 85.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 173 0.37% 85.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 157 0.34% 85.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 138 0.30% 86.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 163 0.35% 86.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 903 1.95% 88.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 167 0.36% 88.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 98 0.21% 88.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 103 0.22% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 86 0.19% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 86 0.19% 89.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 55 0.12% 89.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 76 0.16% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 70 0.15% 89.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 69 0.15% 90.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 49 0.11% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 76 0.16% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 62 0.13% 90.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 63 0.14% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 35 0.08% 90.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 62 0.13% 90.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 58 0.13% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 65 0.14% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 35 0.08% 91.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 74 0.16% 91.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 59 0.13% 91.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 59 0.13% 91.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 26 0.06% 91.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 59 0.13% 91.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 60 0.13% 91.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 63 0.14% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 34 0.07% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 64 0.14% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 58 0.13% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 54 0.12% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 33 0.07% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 54 0.12% 92.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 58 0.13% 92.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 64 0.14% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 34 0.07% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 65 0.14% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 57 0.12% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 56 0.12% 93.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 28 0.06% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 54 0.12% 93.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 53 0.11% 93.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 65 0.14% 93.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 31 0.07% 93.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 67 0.14% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 53 0.11% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 55 0.12% 94.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 27 0.06% 94.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 54 0.12% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 56 0.12% 94.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 66 0.14% 94.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 372 0.80% 95.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 49 0.11% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 28 0.06% 95.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 48 0.10% 95.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 28 0.06% 95.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 51 0.11% 95.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 28 0.06% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 52 0.11% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 28 0.06% 96.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 51 0.11% 96.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 40 0.09% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 53 0.11% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 25 0.05% 96.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 51 0.11% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 26 0.06% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 51 0.11% 96.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 24 0.05% 96.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 50 0.11% 97.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 28 0.06% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 50 0.11% 97.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 26 0.06% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 50 0.11% 97.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 27 0.06% 97.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 51 0.11% 97.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 28 0.06% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 50 0.11% 97.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 26 0.06% 97.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 49 0.11% 97.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 26 0.06% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 52 0.11% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 25 0.05% 98.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 52 0.11% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 25 0.05% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 52 0.11% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 425 0.92% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 13 0.03% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 4 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 2 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 8 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 2 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9923 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10880-10883 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12291 3 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 3 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13507 3 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 4 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 2 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 2 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 35 0.08% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 180 0.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 46254 # Bytes accessed per row activation +system.physmem.totQLat 6257775000 # Total ticks spent queuing +system.physmem.totMemAccLat 14505282500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2214585000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6032922500 # Total ticks spent accessing banks +system.physmem.avgQLat 14128.55 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13620.89 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 32749.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.76 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.76 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 13.19 # Average write queue length over time -system.physmem.readRowHits 427838 # Number of row buffer hits during reads -system.physmem.writeRowHits 93417 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.59 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.90 # Row buffer hit rate for writes -system.physmem.avgGap 3435369.03 # Average gap between requests -system.membus.throughput 18671288 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292313 # Transaction distribution -system.membus.trans_dist::ReadResp 292313 # Transaction distribution -system.membus.trans_dist::WriteReq 9649 # Transaction distribution -system.membus.trans_dist::WriteResp 9649 # Transaction distribution -system.membus.trans_dist::Writeback 115467 # Transaction distribution +system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.25 # Average write queue length when enqueuing +system.physmem.readRowHits 419360 # Number of row buffer hits during reads +system.physmem.writeRowHits 92763 # Number of row buffer hits during writes +system.physmem.readRowHitRate 94.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.34 # Row buffer hit rate for writes +system.physmem.avgGap 3438931.31 # Average gap between requests +system.physmem.pageHitRate 91.72 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.52 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 18651952 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292310 # Transaction distribution +system.membus.trans_dist::ReadResp 292310 # Transaction distribution +system.membus.trans_dist::WriteReq 9650 # Transaction distribution +system.membus.trans_dist::WriteResp 9650 # Transaction distribution +system.membus.trans_dist::Writeback 115466 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 158147 # Transaction distribution -system.membus.trans_dist::ReadExResp 158147 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 877556 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910714 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 158141 # Transaction distribution +system.membus.trans_dist::ReadExResp 158141 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 877537 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910697 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1035394 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30431296 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475852 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1035377 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30430656 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475220 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 35784972 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35784972 # Total data (bytes) +system.membus.tot_pkt_size::total 35784340 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35784340 # Total data (bytes) system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 32373000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 32377500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1487941500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1489694250 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3745756604 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3746415596 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376206000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376299750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.345474 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.352288 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1752558313000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.345474 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084092 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084092 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1753529489000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.352288 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -364,14 +422,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21343633 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21343633 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10434225282 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10434225282 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10455568915 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10455568915 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10455568915 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10455568915 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12989922573 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12989922573 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 13011056956 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 13011056956 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 13011056956 # number of overall miss cycles +system.iocache.overall_miss_latency::total 13011056956 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -388,19 +446,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123373.601156 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123373.601156 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251112.468281 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 251112.468281 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 250582.837987 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 250582.837987 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 250582.837987 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 250582.837987 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 272640 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312618.467775 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 312618.467775 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 311828.806615 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 311828.806615 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 311828.806615 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 311828.806615 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 403484 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27184 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 29141 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.029429 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.845922 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -414,14 +472,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12346133 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12346133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8272160782 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8272160782 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8284506915 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8284506915 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8284506915 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8284506915 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10827670073 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10827670073 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10839807456 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10839807456 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10839807456 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10839807456 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -430,14 +488,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71364.930636 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71364.930636 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199079.726174 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 199079.726174 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198550.195686 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 198550.195686 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198550.195686 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 198550.195686 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260581.201218 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 260581.201218 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259791.670605 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 259791.670605 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259791.670605 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 259791.670605 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -455,22 +513,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9065600 # DTB read hits -system.cpu.dtb.read_misses 10324 # DTB read misses +system.cpu.dtb.read_hits 9064966 # DTB read hits +system.cpu.dtb.read_misses 10312 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728853 # DTB read accesses -system.cpu.dtb.write_hits 6356756 # DTB write hits -system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.dtb.read_accesses 728817 # DTB read accesses +system.cpu.dtb.write_hits 6356267 # DTB write hits +system.cpu.dtb.write_misses 1140 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15422356 # DTB hits -system.cpu.dtb.data_misses 11466 # DTB misses +system.cpu.dtb.write_accesses 291929 # DTB write accesses +system.cpu.dtb.data_hits 15421233 # DTB hits +system.cpu.dtb.data_misses 11452 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020784 # DTB accesses -system.cpu.itb.fetch_hits 4974352 # ITB hits -system.cpu.itb.fetch_misses 5010 # ITB misses +system.cpu.dtb.data_accesses 1020746 # DTB accesses +system.cpu.itb.fetch_hits 4973920 # ITB hits +system.cpu.itb.fetch_misses 4997 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979362 # ITB accesses +system.cpu.itb.fetch_accesses 4978917 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -483,51 +541,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3836946188 # number of cpu cycles simulated +system.cpu.numCycles 3840856082 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56188014 # Number of instructions committed -system.cpu.committedOps 56188014 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52059797 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324527 # Number of float alu accesses -system.cpu.num_func_calls 1483456 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6468822 # number of instructions that are conditional controls -system.cpu.num_int_insts 52059797 # number of integer instructions -system.cpu.num_fp_insts 324527 # number of float instructions -system.cpu.num_int_register_reads 71330046 # number of times the integer registers were read -system.cpu.num_int_register_writes 38525190 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163675 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166554 # number of times the floating registers were written -system.cpu.num_mem_refs 15474978 # number of memory refs -system.cpu.num_load_insts 9102456 # Number of load instructions -system.cpu.num_store_insts 6372522 # Number of store instructions -system.cpu.num_idle_cycles 3586988416.498130 # Number of idle cycles -system.cpu.num_busy_cycles 249957771.501870 # Number of busy cycles -system.cpu.not_idle_fraction 0.065145 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934855 # Percentage of idle cycles +system.cpu.committedInsts 56182750 # Number of instructions committed +system.cpu.committedOps 56182750 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52054772 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324326 # Number of float alu accesses +system.cpu.num_func_calls 1483342 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6468084 # number of instructions that are conditional controls +system.cpu.num_int_insts 52054772 # number of integer instructions +system.cpu.num_fp_insts 324326 # number of float instructions +system.cpu.num_int_register_reads 71321847 # number of times the integer registers were read +system.cpu.num_int_register_writes 38521555 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163576 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166452 # number of times the floating registers were written +system.cpu.num_mem_refs 15473812 # number of memory refs +system.cpu.num_load_insts 9101789 # Number of load instructions +system.cpu.num_store_insts 6372023 # Number of store instructions +system.cpu.num_idle_cycles 3588896828.998131 # Number of idle cycles +system.cpu.num_busy_cycles 251959253.001869 # Number of busy cycles +system.cpu.not_idle_fraction 0.065600 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934400 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211982 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74893 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211963 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106209 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183164 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73526 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106216 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183174 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73526 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149114 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857159489000 96.80% 96.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91367000 0.00% 96.81% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 736929000 0.04% 96.85% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 60484575000 3.15% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1918472360000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149119 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1858257404500 96.76% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91623500 0.00% 96.77% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 737068500 0.04% 96.81% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 61341210500 3.19% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1920427307000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692277 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814101 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692250 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814084 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -563,33 +621,33 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4178 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpctx 4175 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175945 91.21% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175953 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192891 # number of callpals executed +system.cpu.kern.callpal::total 192898 # number of callpals executed system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1740 -system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.323734 # fraction of useful protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1739 +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.323225 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46124802000 2.40% 2.40% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5245072500 0.27% 2.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1867102483500 97.32% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4179 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.391907 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46222890000 2.41% 2.41% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5212630500 0.27% 2.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1868991784500 97.32% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4176 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -621,12 +679,12 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1410582 # Throughput (bytes/s) +system.iobus.throughput 1409150 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51201 # Transaction distribution -system.iobus.trans_dist::WriteResp 51201 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51202 # Transaction distribution +system.iobus.trans_dist::WriteResp 51202 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -638,11 +696,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33158 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -654,12 +712,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2706164 # Total data (bytes) -system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2706172 # Total data (bytes) +system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -681,59 +739,59 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378268915 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 377727206 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43091000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42674250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 928665 # number of replacements -system.cpu.icache.tags.tagsinuse 508.413691 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55270512 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 929176 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.483362 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 38814414250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.413691 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.992995 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.992995 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55270512 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55270512 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55270512 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55270512 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55270512 # number of overall hits -system.cpu.icache.overall_hits::total 55270512 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929336 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929336 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929336 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929336 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929336 # number of overall misses -system.cpu.icache.overall_misses::total 929336 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13015346257 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13015346257 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13015346257 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13015346257 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13015346257 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13015346257 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56199848 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56199848 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56199848 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56199848 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56199848 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56199848 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016536 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016536 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016536 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016536 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016536 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016536 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14004.995241 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14004.995241 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14004.995241 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14004.995241 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14004.995241 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14004.995241 # average overall miss latency +system.cpu.icache.tags.replacements 928358 # number of replacements +system.cpu.icache.tags.tagsinuse 508.321671 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55265541 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 928869 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.497670 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 39723654250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 508.321671 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.992816 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.992816 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55265541 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55265541 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55265541 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55265541 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55265541 # number of overall hits +system.cpu.icache.overall_hits::total 55265541 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929029 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929029 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929029 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929029 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929029 # number of overall misses +system.cpu.icache.overall_misses::total 929029 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12961853258 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12961853258 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12961853258 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12961853258 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12961853258 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12961853258 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56194570 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56194570 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56194570 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56194570 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56194570 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56194570 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016532 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016532 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016532 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016532 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016532 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016532 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13952.043755 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13952.043755 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13952.043755 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13952.043755 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13952.043755 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13952.043755 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -742,126 +800,126 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929336 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929336 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929336 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929336 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929336 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929336 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11150220743 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11150220743 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11150220743 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11150220743 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11150220743 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11150220743 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016536 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016536 # 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average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929029 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 929029 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 929029 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 929029 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 929029 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 929029 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11098555742 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11098555742 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11098555742 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11098555742 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11098555742 # 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number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895431500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895431500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229575000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229575000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014303 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250181 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141459 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6731491626 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6731491626 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 845706258 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20896316135 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21742022393 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 845706258 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20896316135 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21742022393 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334145500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334145500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895642000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895642000 # 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mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279314 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173191 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014303 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279314 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173191 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67190.284156 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49740.362006 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50553.602654 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383463 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383463 # 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average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57678.065137 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63625.207493 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53770.147765 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54096.071042 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63625.207493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53770.147765 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54096.071042 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -937,79 +995,79 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1390866 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.979110 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14050029 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1391378 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.097924 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 105729250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.979110 # 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number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120380 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120380 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049437 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049437 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086189 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086189 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091341 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091341 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091341 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091341 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27000.061487 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27000.061487 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36256.113076 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36256.113076 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13264.108581 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13264.108581 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29050.711070 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29050.711070 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29050.711070 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29050.711070 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1018,54 +1076,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835407 # number of writebacks -system.cpu.dcache.writebacks::total 835407 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069668 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069668 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304510 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304510 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17219 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17219 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1374178 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1374178 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1374178 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1374178 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25967193744 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 25967193744 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9940394617 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9940394617 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194939500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194939500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 35907588361 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 35907588361 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 35907588361 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 35907588361 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424233500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424233500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011219500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011219500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435453000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435453000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120394 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120394 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049456 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049456 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085985 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085985 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091357 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091357 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091357 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091357 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24275.937715 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24275.937715 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32643.902062 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32643.902062 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11321.185899 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11321.185899 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26130.230844 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26130.230844 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26130.230844 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26130.230844 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 835114 # number of writebacks +system.cpu.dcache.writebacks::total 835114 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069470 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069470 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304370 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304370 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17259 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17259 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373840 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373840 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373840 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373840 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26604805241 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26604805241 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10372104863 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10372104863 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194393750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194393750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36976910104 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 36976910104 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36976910104 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36976910104 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011442000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011442000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435677500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435677500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120380 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120380 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049437 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049437 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086189 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086189 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091341 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091341 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091341 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091341 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24876.626031 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24876.626031 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34077.290347 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34077.290347 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11263.326380 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11263.326380 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26915.004734 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26915.004734 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26915.004734 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26915.004734 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1073,31 +1131,31 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 105316327 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2023326 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2023309 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 835407 # Transaction distribution +system.cpu.toL2Bus.throughput 105179195 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2022861 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2022844 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 835114 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 346045 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304495 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858652 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3651517 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5510169 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59476224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142569036 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 202045260 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 202035148 # Total data (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 345905 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304355 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858038 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3650630 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5508668 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59456576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142531220 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 201987796 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 201977684 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 11392 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2426591000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 2425850000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 237000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1397230757 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1396163258 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2194639139 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2191612646 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |