all: Update stats for memory per master and total fix.

3 files changed, 115 insertions, 35 deletions

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
index b18e2b725..31269f9bd 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
@@ -12,6 +12,7 @@ children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview
 atags_addr=256
 boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+early_kernel_symbols=false
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
@@ -19,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=atomic
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
 midr_regval=890224640
 num_work_ids=16
 readfile=tests/halt.sh
@@ -299,9 +300,8 @@ type=IntrControl
 sys=system
 
 [system.iobus]
-type=Bus
+type=NoncoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -360,10 +360,9 @@ cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
 
 [system.membus]
-type=Bus
+type=CoherentBus
 children=badaddr_responder
 block_size=64
-bus_id=1
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -775,9 +774,8 @@ output=true
 port=3456
 
 [system.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
index 17a6394ef..be4dcf157 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May 10 2012 12:36:36
-gem5 started May 10 2012 12:36:42
-gem5 executing on u200540-lin
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 17:25:17
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 911653589000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
index 96669edc4..002831edb 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
@@ -4,32 +4,90 @@ sim_seconds                                  0.911654                       # Nu
 sim_ticks                                911653589000                       # Number of ticks simulated
 final_tick                               911653589000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1682178                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2174115                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            25299801897                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 379752                       # Number of bytes of host memory used
-host_seconds                                    36.03                       # Real time elapsed on the host
+host_inst_rate                                1520101                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1964640                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            22862175544                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 382804                       # Number of bytes of host memory used
+host_seconds                                    39.88                       # Real time elapsed on the host
 sim_insts                                    60615585                       # Number of instructions simulated
 sim_ops                                      78342060                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                    50963556                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                1003776                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 10224784                       # Number of bytes written to this memory
-system.physmem.num_reads                      5103504                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      869236                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       55902326                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                   1101050                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      11215646                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                      67117972                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bytes_read                   68                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read              68                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_written                 0                       # Number of bytes written to this memory
-system.realview.nvmem.num_reads                    17                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_writes                    0                       # Number of write requests responded to by this memory
-system.realview.nvmem.num_other                     0                       # Number of other requests responded to by this memory
-system.realview.nvmem.bw_read                      75                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read                 75                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total                     75                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst           22                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst           53                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               75                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst           22                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst           53                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total           75                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst           22                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst           53                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              75                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::realview.clcd     39321600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker          768                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          512                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           661924                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          6760756                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker         1024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker         1152                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           341852                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          3873968                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             50963556                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       661924                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       341852                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1003776                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7197696                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data       3010088                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          10224784                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd       4915200                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker           12                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            8                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             16561                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            105709                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           16                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker           18                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              5423                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             60557                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               5103504                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          112464                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data           752522                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               869236                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        43132173                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker           842                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker           562                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              726070                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             7415926                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          1123                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          1264                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              374980                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             4249386                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                55902326                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         726070                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         374980                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1101050                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           7895209                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data              18647                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            3301789                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               11215646                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           7895209                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       43132173                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          842                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker          562                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             726070                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            7434574                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         1123                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         1264                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             374980                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            7551175                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               67117972                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        127935                       # number of replacements
 system.l2c.tagsinuse                     26245.835103                       # Cycle average of tags in use
 system.l2c.total_refs                         1477463                       # Total number of references to valid blocks.
@@ -175,12 +233,16 @@ system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.003715
 system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.011465                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.inst      0.014612                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.data      0.073080                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.027957                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu0.data     0.882345                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu1.data     0.805848                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.855220                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.845087                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.655949                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.765972                       # miss rate for SCUpgradeReq accesses
 system.l2c.ReadExReq_miss_rate::cpu0.data     0.590549                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu1.data     0.604811                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.595343                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu0.dtb.walker     0.002262                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.itb.walker     0.003625                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.inst       0.020038                       # miss rate for demand accesses
@@ -189,6 +251,7 @@ system.l2c.demand_miss_rate::cpu1.dtb.walker     0.003715
 system.l2c.demand_miss_rate::cpu1.itb.walker     0.011465                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.inst       0.014612                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.data       0.274157                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.123526                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu0.dtb.walker     0.002262                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.itb.walker     0.003625                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.inst      0.020038                       # miss rate for overall accesses
@@ -197,6 +260,7 @@ system.l2c.overall_miss_rate::cpu1.dtb.walker     0.003715
 system.l2c.overall_miss_rate::cpu1.itb.walker     0.011465                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.inst      0.014612                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.data      0.274157                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.123526                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -308,8 +372,11 @@ system.cpu0.icache.demand_accesses::total     34685670                       # n
 system.cpu0.icache.overall_accesses::cpu0.inst     34685670                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_accesses::total     34685670                       # number of overall (read+write) accesses
 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014349                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.014349                       # miss rate for ReadReq accesses
 system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014349                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.014349                       # miss rate for demand accesses
 system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014349                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.014349                       # miss rate for overall accesses
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -367,11 +434,17 @@ system.cpu0.dcache.demand_accesses::total     14721592                       # n
 system.cpu0.dcache.overall_accesses::cpu0.data     14721592                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::total     14721592                       # number of overall (read+write) accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.030010                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.030010                       # miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.027741                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.027741                       # miss rate for WriteReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054599                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054599                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.040342                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.040342                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.demand_miss_rate::cpu0.data     0.028976                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.028976                       # miss rate for demand accesses
 system.cpu0.dcache.overall_miss_rate::cpu0.data     0.028976                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.028976                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -477,8 +550,11 @@ system.cpu1.icache.demand_accesses::total     26945412                       # n
 system.cpu1.icache.overall_accesses::cpu1.inst     26945412                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_accesses::total     26945412                       # number of overall (read+write) accesses
 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.013596                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.013596                       # miss rate for ReadReq accesses
 system.cpu1.icache.demand_miss_rate::cpu1.inst     0.013596                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.013596                       # miss rate for demand accesses
 system.cpu1.icache.overall_miss_rate::cpu1.inst     0.013596                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.013596                       # miss rate for overall accesses
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -536,11 +612,17 @@ system.cpu1.dcache.demand_accesses::total      9644704                       # n
 system.cpu1.dcache.overall_accesses::cpu1.data      9644704                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::total      9644704                       # number of overall (read+write) accesses
 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.027294                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.027294                       # miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.029093                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.029093                       # miss rate for WriteReq accesses
 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.158141                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.158141                       # miss rate for LoadLockedReq accesses
 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.149298                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.149298                       # miss rate for StoreCondReq accesses
 system.cpu1.dcache.demand_miss_rate::cpu1.data     0.027992                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.027992                       # miss rate for demand accesses
 system.cpu1.dcache.overall_miss_rate::cpu1.data     0.027992                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.027992                       # miss rate for overall accesses
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked