diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2012-01-28 07:24:45 -0800 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2012-01-28 07:24:45 -0800 |
commit | 57e07ac2d2daaa7469241372510395e43ebe14c0 (patch) | |
tree | dc338f4fbe8b26f7d7d3532ea0abe324846ca33d /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt | |
parent | ec20ee2f7cdaff22e63a5ae492f925d0d4839849 (diff) | |
download | gem5-57e07ac2d2daaa7469241372510395e43ebe14c0.tar.xz |
SE/FS: Make both SE and FS tests available all the time.
--HG--
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
rename : tests/long/10.linux-boot/test.py => tests/long/fs/10.linux-boot/test.py
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm
rename : tests/long/80.solaris-boot/test.py => tests/long/fs/80.solaris-boot/test.py
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simout => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simout => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simout => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/test.py => tests/long/se/00.gzip/test.py
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simout => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simout => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simout => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/test.py => tests/long/se/10.mcf/test.py
rename : tests/long/20.parser/ref/alpha/tru64/NOTE => tests/long/se/20.parser/ref/alpha/tru64/NOTE
rename : tests/long/20.parser/ref/arm/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/arm/linux/o3-timing/simerr => tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
rename : tests/long/20.parser/ref/arm/linux/o3-timing/simout => tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
rename : tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simerr => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simout => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/20.parser/ref/arm/linux/simple-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
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rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal
rename : tests/quick/10.linux-boot/test.py => tests/quick/fs/10.linux-boot/test.py
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
rename : tests/quick/80.netperf-stream/test.py => tests/quick/fs/80.netperf-stream/test.py
rename : tests/quick/00.hello.mp/test.py => tests/quick/se/00.hello.mp/test.py
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
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rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/test.py => tests/quick/se/00.hello/test.py
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rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
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rename : tests/quick/01.hello-2T-smt/test.py => tests/quick/se/01.hello-2T-smt/test.py
rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
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rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr
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rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
rename : tests/quick/02.insttest/test.py => tests/quick/se/02.insttest/test.py
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/config.ini
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rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
rename : tests/quick/20.eio-short/test.py => tests/quick/se/20.eio-short/test.py
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
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rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
rename : tests/quick/30.eio-mp/test.py => tests/quick/se/30.eio-mp/test.py
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
rename : tests/quick/40.m5threads-test-atomic/test.py => tests/quick/se/40.m5threads-test-atomic/test.py
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
rename : tests/quick/50.memtest/test.py => tests/quick/se/50.memtest/test.py
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
rename : tests/quick/60.rubytest/test.py => tests/quick/se/60.rubytest/test.py
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt')
-rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt | 441 |
1 files changed, 441 insertions, 0 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt new file mode 100644 index 000000000..e3050fa31 --- /dev/null +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -0,0 +1,441 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 2.332317 # Number of seconds simulated +sim_ticks 2332316587000 # Number of ticks simulated +final_tick 2332316587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 2072038 # Simulator instruction rate (inst/s) +host_tick_rate 63144661085 # Simulator tick rate (ticks/s) +host_mem_usage 379208 # Number of bytes of host memory used +host_seconds 36.94 # Real time elapsed on the host +sim_insts 76532931 # Number of instructions simulated +system.nvmem.bytes_read 20 # Number of bytes read from this memory +system.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory +system.nvmem.bytes_written 0 # Number of bytes written to this memory +system.nvmem.num_reads 5 # Number of read requests responded to by this memory +system.nvmem.num_writes 0 # Number of write requests responded to by this memory +system.nvmem.num_other 0 # Number of other requests responded to by this memory +system.nvmem.bw_read 9 # Total read bandwidth from this memory (bytes/s) +system.nvmem.bw_inst_read 9 # Instruction read bandwidth from this memory (bytes/s) +system.nvmem.bw_total 9 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read 122663536 # Number of bytes read from this memory +system.physmem.bytes_inst_read 941280 # Number of instructions bytes read from this memory +system.physmem.bytes_written 9577800 # Number of bytes written to this memory +system.physmem.num_reads 14137126 # Number of read requests responded to by this memory +system.physmem.num_writes 856485 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 52593004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 403582 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 4106561 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 56699565 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 116822 # number of replacements +system.l2c.tagsinuse 24240.388378 # Cycle average of tags in use +system.l2c.total_refs 1520830 # Total number of references to valid blocks. +system.l2c.sampled_refs 146847 # Sample count of references to valid blocks. +system.l2c.avg_refs 10.356562 # Average number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::0 10591.091336 # Average occupied blocks per context +system.l2c.occ_blocks::1 13649.297042 # Average occupied blocks per context +system.l2c.occ_percent::0 0.161607 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.208272 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1188216 # number of ReadReq hits +system.l2c.ReadReq_hits::1 10669 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1198885 # number of ReadReq hits +system.l2c.Writeback_hits::0 604613 # number of Writeback hits +system.l2c.Writeback_hits::total 604613 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 26 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::0 105791 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 105791 # number of ReadExReq hits +system.l2c.demand_hits::0 1294007 # number of demand (read+write) hits +system.l2c.demand_hits::1 10669 # number of demand (read+write) hits +system.l2c.demand_hits::total 1304676 # number of demand (read+write) hits +system.l2c.overall_hits::0 1294007 # number of overall hits +system.l2c.overall_hits::1 10669 # number of overall hits +system.l2c.overall_hits::total 1304676 # number of overall hits +system.l2c.ReadReq_misses::0 31716 # number of ReadReq misses +system.l2c.ReadReq_misses::1 27 # number of ReadReq misses +system.l2c.ReadReq_misses::total 31743 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 2911 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2911 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 141169 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 141169 # number of ReadExReq misses +system.l2c.demand_misses::0 172885 # number of demand (read+write) misses +system.l2c.demand_misses::1 27 # number of demand (read+write) misses +system.l2c.demand_misses::total 172912 # number of demand (read+write) misses +system.l2c.overall_misses::0 172885 # number of overall misses +system.l2c.overall_misses::1 27 # number of overall misses +system.l2c.overall_misses::total 172912 # number of overall misses +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 1219932 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 10696 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1230628 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 604613 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 604613 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 2937 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2937 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 246960 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246960 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 1466892 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 10696 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1477588 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 1466892 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 10696 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1477588 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.025998 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.002524 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028522 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.991147 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.571627 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.117858 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.002524 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.120382 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.117858 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.002524 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.120382 # miss rate for overall accesses +system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks 102531 # number of writebacks +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses +system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 14940566 # DTB read hits +system.cpu.dtb.read_misses 7288 # DTB read misses +system.cpu.dtb.write_hits 11198205 # DTB write hits +system.cpu.dtb.write_misses 2199 # DTB write misses +system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 14947854 # DTB read accesses +system.cpu.dtb.write_accesses 11200404 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 26138771 # DTB hits +system.cpu.dtb.misses 9487 # DTB misses +system.cpu.dtb.accesses 26148258 # DTB accesses +system.cpu.itb.inst_hits 60273889 # ITB inst hits +system.cpu.itb.inst_misses 4471 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 60278360 # ITB inst accesses +system.cpu.itb.hits 60273889 # DTB hits +system.cpu.itb.misses 4471 # DTB misses +system.cpu.itb.accesses 60278360 # DTB accesses +system.cpu.numCycles 4664556206 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 76532931 # Number of instructions executed +system.cpu.num_int_alu_accesses 68161177 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses +system.cpu.num_func_calls 1971944 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7572657 # number of instructions that are conditional controls +system.cpu.num_int_insts 68161177 # number of integer instructions +system.cpu.num_fp_insts 10269 # number of float instructions +system.cpu.num_int_register_reads 345365607 # number of times the integer registers were read +system.cpu.num_int_register_writes 72877692 # number of times the integer registers were written +system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written +system.cpu.num_mem_refs 27310784 # number of memory refs +system.cpu.num_load_insts 15607074 # Number of load instructions +system.cpu.num_store_insts 11703710 # Number of store instructions +system.cpu.num_idle_cycles 4586920150.977920 # Number of idle cycles +system.cpu.num_busy_cycles 77636055.022080 # Number of busy cycles +system.cpu.not_idle_fraction 0.016644 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.983356 # Percentage of idle cycles +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 82751 # number of quiesce instructions executed +system.cpu.icache.replacements 847054 # number of replacements +system.cpu.icache.tagsinuse 511.678552 # Cycle average of tags in use +system.cpu.icache.total_refs 59429083 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 847566 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 70.117351 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 5705452000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 511.678552 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.999372 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 59429083 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59429083 # number of ReadReq hits +system.cpu.icache.demand_hits::0 59429083 # number of demand (read+write) hits +system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59429083 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 59429083 # number of overall hits +system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::total 59429083 # number of overall hits +system.cpu.icache.ReadReq_misses::0 847566 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 847566 # number of ReadReq misses +system.cpu.icache.demand_misses::0 847566 # number of demand (read+write) misses +system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 847566 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 847566 # number of overall misses +system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::total 847566 # number of overall misses +system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 60276649 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60276649 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 60276649 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60276649 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 60276649 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60276649 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.014061 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.014061 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::0 0.014061 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 44721 # number of writebacks +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 622134 # number of replacements +system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use +system.cpu.dcache.total_refs 23580069 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 622646 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.870747 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 511.997030 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::0 13150366 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13150366 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 9943631 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9943631 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 235999 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 235999 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 247136 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247136 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 23093997 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23093997 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 23093997 # number of overall hits +system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::total 23093997 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 364548 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 364548 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 249897 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 249897 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 11138 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11138 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::0 614445 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 614445 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 614445 # number of overall misses +system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::total 614445 # number of overall misses +system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 13514914 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13514914 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 10193528 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10193528 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 247137 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247137 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 247136 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247136 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 23708442 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23708442 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 23708442 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23708442 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.026974 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.024515 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.045068 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::0 0.025917 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::0 0.025917 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 559892 # number of writebacks +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.replacements 0 # number of replacements +system.iocache.tagsinuse 0 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.avg_refs no_value # Average number of references to valid blocks. +system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 0 # number of demand (read+write) misses +system.iocache.demand_misses::total 0 # number of demand (read+write) misses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 0 # number of overall misses +system.iocache.overall_misses::total 0 # number of overall misses +system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 0 # number of overall miss cycles +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks 0 # number of writebacks +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 0 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- |