diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:18:29 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:18:29 -0500 |
| commit | 93c0307d418e08db609818f19f5d2b02d45e7465 (patch) | |
| tree | 1f72a6617fb4a74d904a933bc48136fa0760bd19 /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt | |
| parent | f2db2a96d181f796e6e475121f10230b9d1d007f (diff) | |
| download | gem5-93c0307d418e08db609818f19f5d2b02d45e7465.tar.xz | |
tests: Update regressions for the new kernels and various preceeding fixes.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt | 997 |
1 files changed, 534 insertions, 463 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 227319fff..e8036ea95 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,171 +1,203 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.321335 # Number of seconds simulated -sim_ticks 2321335404000 # Number of ticks simulated -final_tick 2321335404000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.783853 # Number of seconds simulated +sim_ticks 2783853461500 # Number of ticks simulated +final_tick 2783853461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1308981 # Simulator instruction rate (inst/s) -host_op_rate 1576286 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50301976363 # Simulator tick rate (ticks/s) -host_mem_usage 455960 # Number of bytes of host memory used -host_seconds 46.15 # Real time elapsed on the host -sim_insts 60406834 # Number of instructions simulated -sim_ops 72742429 # Number of ops (including micro ops) simulated +host_inst_rate 1369296 # Simulator instruction rate (inst/s) +host_op_rate 1666897 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26699855189 # Simulator tick rate (ticks/s) +host_mem_usage 553552 # Number of bytes of host memory used +host_seconds 104.26 # Real time elapsed on the host +sim_insts 142769281 # Number of instructions simulated +sim_ops 173798567 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1210980 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10345892 # Number of bytes read from this memory +system.physmem.bytes_read::total 11558408 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1210980 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6521472 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory +system.physmem.bytes_written::total 8857332 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 27375 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 162174 # Number of read requests responded to by this memory +system.physmem.num_reads::total 189573 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 101898 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142503 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 435001 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3716392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4151946 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 435001 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2342606 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3181680 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2342606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 435001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3722687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7333626 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 24 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 24 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 6 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 110100480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 705416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9071832 # Number of bytes read from this memory -system.physmem.bytes_read::total 119878240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 705416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705416 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3703872 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory -system.physmem.bytes_written::total 6719688 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 13762560 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17234 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141773 # Number of read requests responded to by this memory -system.physmem.num_reads::total 13921575 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57873 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811827 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47429803 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 83 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 303884 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3908023 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51641930 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 303884 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 303884 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1595578 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1299173 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2894751 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1595578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47429803 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 83 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 303884 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5207196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54536681 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 14973631 # Transaction distribution -system.membus.trans_dist::ReadResp 14973631 # Transaction distribution -system.membus.trans_dist::WriteReq 763122 # Transaction distribution -system.membus.trans_dist::WriteResp 763122 # Transaction distribution -system.membus.trans_dist::Writeback 57873 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4517 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4517 # Transaction distribution -system.membus.trans_dist::ReadExReq 131874 # Transaction distribution -system.membus.trans_dist::ReadExResp 131874 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382824 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3360 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1892845 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4279041 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 27525120 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 27525120 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31804161 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390127 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 6720 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16497448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18894319 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 110100480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 110100480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 128994799 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 74236 # Transaction distribution +system.membus.trans_dist::ReadResp 74236 # Transaction distribution +system.membus.trans_dist::WriteReq 27560 # Transaction distribution +system.membus.trans_dist::WriteResp 27560 # Transaction distribution +system.membus.trans_dist::Writeback 101898 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution +system.membus.trans_dist::ReadExReq 146085 # Transaction distribution +system.membus.trans_dist::ReadExResp 146085 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498794 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606198 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 679126 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096444 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259463 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20593159 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 214751 # Request fanout histogram +system.membus.snoop_fanout::samples 322857 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 214751 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 322857 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 214751 # Request fanout histogram +system.membus.snoop_fanout::total 322857 # Request fanout histogram +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 14945841 # Transaction distribution -system.iobus.trans_dist::ReadResp 14945841 # Transaction distribution -system.iobus.trans_dist::WriteReq 8131 # Transaction distribution -system.iobus.trans_dist::WriteResp 8131 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7900 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 476 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 984 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 631 # Number of DMA write transactions. +system.iobus.trans_dist::ReadReq 30171 # Transaction distribution +system.iobus.trans_dist::ReadResp 30171 # Transaction distribution +system.iobus.trans_dist::WriteReq 59016 # Transaction distribution +system.iobus.trans_dist::WriteResp 22792 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 732 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382824 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 27525120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 27525120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 29907944 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39247 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15800 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 952 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 1968 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 390 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 2390127 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 110100480 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::total 110100480 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 112490607 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -190,25 +222,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 13142243 # DTB read hits -system.cpu.dtb.read_misses 7297 # DTB read misses -system.cpu.dtb.write_hits 11216207 # DTB write hits -system.cpu.dtb.write_misses 2181 # DTB write misses -system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3399 # Number of entries that have been flushed from TLB +system.cpu.dtb.read_hits 31525428 # DTB read hits +system.cpu.dtb.read_misses 8580 # DTB read misses +system.cpu.dtb.write_hits 23123837 # DTB write hits +system.cpu.dtb.write_misses 1448 # DTB write misses +system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 13149540 # DTB read accesses -system.cpu.dtb.write_accesses 11218388 # DTB write accesses +system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 31534008 # DTB read accesses +system.cpu.dtb.write_accesses 23125285 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 24358450 # DTB hits -system.cpu.dtb.misses 9478 # DTB misses -system.cpu.dtb.accesses 24367928 # DTB accesses +system.cpu.dtb.hits 54649265 # DTB hits +system.cpu.dtb.misses 10028 # DTB misses +system.cpu.dtb.accesses 54659293 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -230,130 +262,130 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 61430007 # ITB inst hits -system.cpu.itb.inst_misses 4471 # ITB inst misses +system.cpu.itb.inst_hits 147035651 # ITB inst hits +system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2370 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61434478 # ITB inst accesses -system.cpu.itb.hits 61430007 # DTB hits -system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61434478 # DTB accesses -system.cpu.numCycles 4642753590 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 147040413 # ITB inst accesses +system.cpu.itb.hits 147035651 # DTB hits +system.cpu.itb.misses 4762 # DTB misses +system.cpu.itb.accesses 147040413 # DTB accesses +system.cpu.numCycles 5567710004 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60406834 # Number of instructions committed -system.cpu.committedOps 72742429 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 64191430 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2135762 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7544984 # number of instructions that are conditional controls -system.cpu.num_int_insts 64191430 # number of integer instructions -system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 116427347 # number of times the integer registers were read -system.cpu.num_int_register_writes 42818107 # number of times the integer registers were written -system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_cc_register_reads 217570004 # number of times the CC registers were read -system.cpu.num_cc_register_writes 28977741 # number of times the CC registers were written -system.cpu.num_mem_refs 25221274 # number of memory refs -system.cpu.num_load_insts 13499937 # Number of load instructions -system.cpu.num_store_insts 11721337 # Number of store instructions -system.cpu.num_idle_cycles 4568976022.512934 # Number of idle cycles -system.cpu.num_busy_cycles 73777567.487067 # Number of busy cycles -system.cpu.not_idle_fraction 0.015891 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.984109 # Percentage of idle cycles -system.cpu.Branches 10298517 # Number of branches fetched -system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction -system.cpu.op_class::IntAlu 47536032 65.23% 65.27% # Class of executed instruction -system.cpu.op_class::IntMult 87771 0.12% 65.39% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 2113 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::MemRead 13499937 18.52% 83.92% # Class of executed instruction -system.cpu.op_class::MemWrite 11721337 16.08% 100.00% # Class of executed instruction +system.cpu.committedInsts 142769281 # Number of instructions committed +system.cpu.committedOps 173798567 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 153158502 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses +system.cpu.num_func_calls 16873305 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18730015 # number of instructions that are conditional controls +system.cpu.num_int_insts 153158502 # number of integer instructions +system.cpu.num_fp_insts 11484 # number of float instructions +system.cpu.num_int_register_reads 285052059 # number of times the integer registers were read +system.cpu.num_int_register_writes 107176408 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written +system.cpu.num_cc_register_reads 530840054 # number of times the CC registers were read +system.cpu.num_cc_register_writes 62363143 # number of times the CC registers were written +system.cpu.num_mem_refs 55937812 # number of memory refs +system.cpu.num_load_insts 31855061 # Number of load instructions +system.cpu.num_store_insts 24082751 # Number of store instructions +system.cpu.num_idle_cycles 5389631214.604722 # Number of idle cycles +system.cpu.num_busy_cycles 178078789.395278 # Number of busy cycles +system.cpu.not_idle_fraction 0.031984 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.968016 # Percentage of idle cycles +system.cpu.Branches 36396067 # Number of branches fetched +system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 121149664 68.36% 68.36% # Class of executed instruction +system.cpu.op_class::IntMult 116881 0.07% 68.43% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 68.43% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction +system.cpu.op_class::MemRead 31855061 17.98% 86.41% # Class of executed instruction +system.cpu.op_class::MemWrite 24082751 13.59% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 72875708 # Class of executed instruction +system.cpu.op_class::total 177215263 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 82781 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 850504 # number of replacements -system.cpu.icache.tags.tagsinuse 511.689630 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60581751 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 851016 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 71.187558 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 5451547500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.689630 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999394 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999394 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed +system.cpu.icache.tags.replacements 1698994 # number of replacements +system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 145339246 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1699506 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 85.518525 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 7831492000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 62283783 # Number of tag accesses -system.cpu.icache.tags.data_accesses 62283783 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 60581751 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60581751 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60581751 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60581751 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60581751 # number of overall hits -system.cpu.icache.overall_hits::total 60581751 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 851016 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 851016 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 851016 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 851016 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 851016 # number of overall misses -system.cpu.icache.overall_misses::total 851016 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 61432767 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61432767 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61432767 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61432767 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61432767 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61432767 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013853 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013853 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013853 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013853 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013853 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013853 # miss rate for overall accesses +system.cpu.icache.tags.tag_accesses 148738270 # Number of tag accesses +system.cpu.icache.tags.data_accesses 148738270 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 145339246 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145339246 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 145339246 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 145339246 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 145339246 # number of overall hits +system.cpu.icache.overall_hits::total 145339246 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1699512 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699512 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1699512 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699512 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1699512 # number of overall misses +system.cpu.icache.overall_misses::total 1699512 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 147038758 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 147038758 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 147038758 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 147038758 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 147038758 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 147038758 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -363,115 +395,121 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 62250 # number of replacements -system.cpu.l2cache.tags.tagsinuse 50006.820137 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1669876 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 127635 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.083214 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2306275686000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36897.819647 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.959772 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993972 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.485209 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6090.561537 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.563016 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 110027 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65155.315266 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2727659 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 175308 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 15.559239 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 48893.414938 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.653997 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.309992 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107033 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.092935 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.763044 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.138316 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.109776 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65380 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3672 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9281 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997620 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 17035355 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 17035355 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7540 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3151 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 838782 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 366774 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1216247 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 592630 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 592630 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113709 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113709 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 7540 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3151 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 838782 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 480483 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1329956 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 7540 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3151 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 838782 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 480483 # number of overall hits -system.cpu.l2cache.overall_hits::total 1329956 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 10608 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 9871 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 20487 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2917 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2917 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133474 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133474 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 10608 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143345 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 153961 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 10608 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143345 # number of overall misses -system.cpu.l2cache.overall_misses::total 153961 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7545 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 849390 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 376645 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1236734 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 592630 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 592630 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2943 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2943 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247183 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247183 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7545 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 849390 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 623828 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1483917 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7545 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 849390 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 623828 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1483917 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000663 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000951 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012489 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016565 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991165 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991165 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539981 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.539981 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000663 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000951 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012489 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.229783 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.103753 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000663 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000951 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012489 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.229783 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.103753 # miss rate for overall accesses +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 26202376 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 26202376 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1681137 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 505491 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2197846 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 682038 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 682038 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 151041 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 151041 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1681137 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 656532 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2348887 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681137 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 656532 # number of overall hits +system.cpu.l2cache.overall_hits::total 2348887 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 18358 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 15534 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 33901 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 147864 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 147864 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 18358 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 163398 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 181765 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 18358 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 163398 # number of overall misses +system.cpu.l2cache.overall_misses::total 181765 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699495 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 521025 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2231747 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 682038 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 682038 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 298905 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 298905 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699495 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2530652 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699495 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2530652 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010802 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029814 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015190 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494686 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.494686 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010802 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.071825 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010802 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.071825 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -480,77 +518,81 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 57873 # number of writebacks -system.cpu.l2cache.writebacks::total 57873 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks +system.cpu.l2cache.writebacks::total 101898 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 623316 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997018 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21798557 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 623828 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.943217 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 21757000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997018 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 819402 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 53783051 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.595966 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 23054000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 291 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 90313368 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 90313368 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11240238 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11240238 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9961313 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9961313 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 110856 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 110856 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236011 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236011 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247196 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247196 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21201551 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21201551 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21312407 # number of overall hits -system.cpu.dcache.overall_hits::total 21312407 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 292017 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 292017 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250126 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250126 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 73442 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 73442 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11186 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11186 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 542143 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 542143 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 615585 # number of overall misses -system.cpu.dcache.overall_misses::total 615585 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 11532255 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 11532255 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10211439 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10211439 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 184298 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 184298 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247197 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247197 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247196 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247196 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21743694 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21743694 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21927992 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21927992 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025322 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025322 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.398496 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.398496 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045251 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045251 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024933 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024933 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.028073 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.028073 # miss rate for overall accesses +system.cpu.dcache.tags.tag_accesses 219231854 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219231854 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 30128262 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30128262 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22339512 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22339512 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 395063 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 395063 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 52467774 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52467774 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52862837 # number of overall hits +system.cpu.dcache.overall_hits::total 52862837 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 396291 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 396291 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 301661 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 301661 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116123 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116123 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 697952 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 697952 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 814075 # number of overall misses +system.cpu.dcache.overall_misses::total 814075 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 30524553 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30524553 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641173 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641173 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 53165726 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53165726 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53676912 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53676912 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012983 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227164 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.227164 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -559,59 +601,88 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 592630 # number of writebacks -system.cpu.dcache.writebacks::total 592630 # number of writebacks +system.cpu.dcache.writebacks::writebacks 682038 # number of writebacks +system.cpu.dcache.writebacks::total 682038 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2445766 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2445766 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 763122 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 763122 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 592630 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2943 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2943 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247183 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247183 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1715294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5740322 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17852 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37190 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7510658 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54491548 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83266131 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 35704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74380 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 137867763 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2097938 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 2288345 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2288345 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 682038 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 298905 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 298905 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417070 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444678 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5917174 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108804860 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308747 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205224459 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 36632 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3268415 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.105033 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 2097938 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3231951 98.88% 98.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 36464 1.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2097938 # Request fanout histogram -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3268415 # Request fanout histogram +system.iocache.tags.replacements 36430 # number of replacements +system.iocache.tags.tagsinuse 0.909886 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.tags.tag_accesses 0 # Number of tag accesses -system.iocache.tags.data_accesses 0 # Number of data accesses +system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 227409698009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.909886 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 328176 # Number of tag accesses +system.iocache.tags.data_accesses 328176 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses +system.iocache.ReadReq_misses::total 240 # number of ReadReq misses +system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses +system.iocache.demand_misses::total 240 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 240 # number of overall misses +system.iocache.overall_misses::total 240 # number of overall misses +system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 240 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 36224 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |