stats: Update stats for CPU and cache changes

This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.

1 files changed, 312 insertions, 302 deletions

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index 04261a831..511b86cf1 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -1,18 +1,56 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.332812                       # Number of seconds simulated
-sim_ticks                                2332811899500                       # Number of ticks simulated
-final_tick                               2332811899500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.321351                       # Number of seconds simulated
+sim_ticks                                2321351025500                       # Number of ticks simulated
+final_tick                               2321351025500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 975328                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1254205                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            37662621026                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 462792                       # Number of bytes of host memory used
-host_seconds                                    61.94                       # Real time elapsed on the host
-sim_insts                                    60411489                       # Number of instructions simulated
-sim_ops                                      77685090                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 818788                       # Simulator instruction rate (inst/s)
+host_op_rate                                   985991                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            31464875718                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 430844                       # Number of bytes of host memory used
+host_seconds                                    73.78                       # Real time elapsed on the host
+sim_insts                                    60406834                       # Number of instructions simulated
+sim_ops                                      72742429                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.bytes_read::realview.clcd    110100480                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            705416                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9071832                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            119878240                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       705416                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          705416                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3703872                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data        3015816                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6719688                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      13762560                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker            5                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            3                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              17234                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             141773                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              13921575                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           57873                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data            753954                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               811827                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47429483                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            138                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             83                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               303882                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3907997                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51641582                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          303882                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             303882                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1595567                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1299164                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2894732                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1595567                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47429483                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           138                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            83                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              303882                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             5207161                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               54536314                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
@@ -25,46 +63,8 @@ system.realview.nvmem.bw_inst_read::cpu.inst            9
 system.realview.nvmem.bw_inst_read::total            9                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst            9                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               9                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.clcd    111673344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            705160                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9071768                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            121450784                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       705160                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          705160                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3703424                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data        3015816                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6719240                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      13959168                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            3                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              17230                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             141782                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              14118188                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           57866                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data            753954                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               811820                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47870702                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker            137                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             82                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               302279                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3888770                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                52061970                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          302279                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             302279                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1587536                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1292781                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2880318                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1587536                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47870702                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           137                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            82                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              302279                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             5181551                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               54942288                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     55969769                       # Throughput (bytes/s)
-system.membus.data_through_bus              130566943                       # Total data (bytes)
+system.membus.throughput                     55568847                       # Throughput (bytes/s)
+system.membus.data_through_bus              128994799                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
@@ -72,8 +72,8 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.iobus.throughput                      48895283                       # Throughput (bytes/s)
-system.iobus.data_through_bus               114063499                       # Total data (bytes)
+system.iobus.throughput                      48459111                       # Throughput (bytes/s)
+system.iobus.data_through_bus               112490607                       # Total data (bytes)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -98,25 +98,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     14971763                       # DTB read hits
-system.cpu.dtb.read_misses                       7294                       # DTB read misses
-system.cpu.dtb.write_hits                    11217184                       # DTB write hits
+system.cpu.dtb.read_hits                     13142244                       # DTB read hits
+system.cpu.dtb.read_misses                       7297                       # DTB read misses
+system.cpu.dtb.write_hits                    11216207                       # DTB write hits
 system.cpu.dtb.write_misses                      2181                       # DTB write misses
 system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     3403                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries                     3399                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.prefetch_faults                    174                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                       452                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 14979057                       # DTB read accesses
-system.cpu.dtb.write_accesses                11219365                       # DTB write accesses
+system.cpu.dtb.read_accesses                 13149541                       # DTB read accesses
+system.cpu.dtb.write_accesses                11218388                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          26188947                       # DTB hits
-system.cpu.dtb.misses                            9475                       # DTB misses
-system.cpu.dtb.accesses                      26198422                       # DTB accesses
+system.cpu.dtb.hits                          24358451                       # DTB hits
+system.cpu.dtb.misses                            9478                       # DTB misses
+system.cpu.dtb.accesses                      24367929                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -138,7 +138,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                     61434680                       # ITB inst hits
+system.cpu.itb.inst_hits                     61430007                       # ITB inst hits
 system.cpu.itb.inst_misses                       4471                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
@@ -155,105 +155,107 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 61439151                       # ITB inst accesses
-system.cpu.itb.hits                          61434680                       # DTB hits
+system.cpu.itb.inst_accesses                 61434478                       # ITB inst accesses
+system.cpu.itb.hits                          61430007                       # DTB hits
 system.cpu.itb.misses                            4471                       # DTB misses
-system.cpu.itb.accesses                      61439151                       # DTB accesses
-system.cpu.numCycles                       4665623800                       # number of cpu cycles simulated
+system.cpu.itb.accesses                      61434478                       # DTB accesses
+system.cpu.numCycles                       4642702052                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    60411489                       # Number of instructions committed
-system.cpu.committedOps                      77685090                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              69133554                       # Number of integer alu accesses
+system.cpu.committedInsts                    60406834                       # Number of instructions committed
+system.cpu.committedOps                      72742429                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              64191430                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  10269                       # Number of float alu accesses
-system.cpu.num_func_calls                     2136078                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      7942566                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     69133554                       # number of integer instructions
+system.cpu.num_func_calls                     2135762                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      7544984                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     64191430                       # number of integer instructions
 system.cpu.num_fp_insts                         10269                       # number of float instructions
-system.cpu.num_int_register_reads           355910547                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           74442273                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           116427347                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           42818107                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                 7493                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                2780                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      27362421                       # number of memory refs
-system.cpu.num_load_insts                    15640088                       # Number of load instructions
-system.cpu.num_store_insts                   11722333                       # Number of store instructions
-system.cpu.num_idle_cycles               4586822073.007144                       # Number of idle cycles
-system.cpu.num_busy_cycles               78801726.992856                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.016890                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.983110                       # Percentage of idle cycles
-system.cpu.Branches                          10299261                       # Number of branches fetched
+system.cpu.num_cc_register_reads            217570004                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            28977741                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      25221274                       # number of memory refs
+system.cpu.num_load_insts                    13499937                       # Number of load instructions
+system.cpu.num_store_insts                   11721337                       # Number of store instructions
+system.cpu.num_idle_cycles               4568843017.980124                       # Number of idle cycles
+system.cpu.num_busy_cycles               73859034.019877                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.015909                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.984091                       # Percentage of idle cycles
+system.cpu.Branches                          10298517                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                 28518      0.04%      0.04% # Class of executed instruction
-system.cpu.op_class::IntAlu                  50337551     64.69%     64.72% # Class of executed instruction
-system.cpu.op_class::IntMult                    87780      0.11%     64.84% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc               2117      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     64.84% # Class of executed instruction
-system.cpu.op_class::MemRead                 15640088     20.10%     84.94% # Class of executed instruction
-system.cpu.op_class::MemWrite                11722333     15.06%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                  47536032     65.23%     65.27% # Class of executed instruction
+system.cpu.op_class::IntMult                    87771      0.12%     65.39% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc               2113      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     65.39% # Class of executed instruction
+system.cpu.op_class::MemRead                 13499937     18.52%     83.92% # Class of executed instruction
+system.cpu.op_class::MemWrite                11721337     16.08%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   77818387                       # Class of executed instruction
+system.cpu.op_class::total                   72875708                       # Class of executed instruction
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
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-system.cpu.icache.tags.replacements            850590                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.678462                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            60586338                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            851102                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             71.185754                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle        5711018500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.678462                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999372                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999372                       # Average percentage of cache occupancy
+system.cpu.kern.inst.quiesce                    82781                       # number of quiesce instructions executed
+system.cpu.icache.tags.replacements            850515                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.689593                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            60581740                       # Total number of references to valid blocks.
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+system.cpu.icache.tags.avg_refs             71.186625                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle        5455017500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.689593                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999394                       # Average percentage of cache occupancy
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 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
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-system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
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 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          62288542                       # Number of tag accesses
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-system.cpu.icache.overall_accesses::total     61437440                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses          62283794                       # Number of tag accesses
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 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013853                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.013853                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.013853                       # miss rate for demand accesses
@@ -269,115 +271,115 @@ system.cpu.icache.avg_blocked_cycles::no_targets          nan
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            62245                       # number of replacements
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-system.cpu.l2cache.tags.total_refs            1669929                       # Total number of references to valid blocks.
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-system.cpu.l2cache.tags.avg_refs            13.084142                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     2316903124500                       # Cycle when the warmup percentage was hit.
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-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     2.960146                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.993931                       # Average occupied blocks per requestor
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+system.cpu.l2cache.Writeback_accesses::writebacks       592642                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       592642                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2943                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         2943                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       247180                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       247180                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7546                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker         3154                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       849401                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       623841                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1483942                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7546                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker         3154                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       849401                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       623841                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1483942                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000663                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000951                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012489                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026207                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.016565                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.991165                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991165                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.539987                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.539987                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000663                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000951                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012489                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.229778                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.103751                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000663                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000951                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012489                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.229778                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.103751                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -386,69 +388,77 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        57866                       # number of writebacks
-system.cpu.l2cache.writebacks::total            57866                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        57873                       # number of writebacks
+system.cpu.l2cache.writebacks::total            57873                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            623343                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.997030                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            23629012                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            623855                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             37.875808                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          21768000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.997030                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements            623329                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.997018                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            21798545                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            623841                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             34.942469                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          21757000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.997018                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999994                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          278                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          208                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          291                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          197                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          97635323                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         97635323                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     13180574                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13180574                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      9962233                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        9962233                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       236039                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       236039                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       247221                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       247221                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      23142807                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         23142807                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     23142807                       # number of overall hits
-system.cpu.dcache.overall_hits::total        23142807                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       365463                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        365463                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       250154                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       250154                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        11183                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        11183                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data       615617                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         615617                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       615617                       # number of overall misses
-system.cpu.dcache.overall_misses::total        615617                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data     13546037                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13546037                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10212387                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10212387                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247222                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       247222                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       247221                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       247221                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     23758424                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     23758424                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     23758424                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     23758424                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.026979                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.026979                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024495                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.024495                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045235                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045235                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.025912                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.025912                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.025912                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.025912                       # miss rate for overall accesses
+system.cpu.dcache.tags.tag_accesses          90313385                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         90313385                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     11240226                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        11240226                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      9961316                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        9961316                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       110856                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        110856                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       236008                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       236008                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       247196                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       247196                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      21201542                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         21201542                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     21312398                       # number of overall hits
+system.cpu.dcache.overall_hits::total        21312398                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       292030                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        292030                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       250123                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       250123                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data        73442                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total        73442                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        11189                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        11189                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data       542153                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         542153                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       615595                       # number of overall misses
+system.cpu.dcache.overall_misses::total        615595                       # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data     11532256                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     11532256                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10211439                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10211439                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       184298                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       184298                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247197                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       247197                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       247196                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       247196                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21743695                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21743695                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21927993                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21927993                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025323                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.025323                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024494                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.024494                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.398496                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.398496                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045263                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045263                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.024934                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.024934                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.028073                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.028073                       # miss rate for overall accesses
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -457,11 +467,11 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       592648                       # number of writebacks
-system.cpu.dcache.writebacks::total            592648                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks       592642                       # number of writebacks
+system.cpu.dcache.writebacks::total            592642                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                59102995                       # Throughput (bytes/s)
-system.cpu.toL2Bus.data_through_bus         137876171                       # Total data (bytes)
+system.cpu.toL2Bus.throughput                59392167                       # Throughput (bytes/s)
+system.cpu.toL2Bus.data_through_bus         137870067                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.iocache.tags.replacements                    0                       # number of replacements
 system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use