diff options
author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
---|---|---|
committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
commit | 84f138ba96201431513eb2ae5f847389ac731aa2 (patch) | |
tree | 3aee721699295c85e4e0c2d3d4a6bb27595bfabd /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic | |
parent | a288c94387b110112461ff5686fa727a43ddbe9c (diff) | |
download | gem5-84f138ba96201431513eb2ae5f847389ac731aa2.tar.xz |
stats: update references
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic')
4 files changed, 518 insertions, 270 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index bf0fe93f0..1daf4d9e6 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -12,11 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/dist/m5/system/binaries/boot_emm.arm +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -29,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -41,10 +42,14 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= thermal_components= @@ -61,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -89,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/m5/system/disks/linux-aarch32-ael.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -107,6 +117,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -125,6 +136,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -146,12 +161,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -170,8 +190,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -194,9 +219,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -210,9 +240,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -223,12 +258,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -247,8 +287,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -306,9 +351,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -322,9 +372,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -335,12 +390,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -359,8 +419,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 @@ -368,10 +433,15 @@ size=4194304 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -416,9 +486,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -432,12 +507,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -456,8 +536,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -465,10 +550,15 @@ size=1024 type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -482,11 +572,16 @@ slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side s [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -502,11 +597,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=2147483648:2415919103 port=system.membus.master[5] @@ -521,10 +621,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -605,14 +710,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -621,13 +731,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -708,10 +823,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -791,17 +911,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -827,13 +952,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -841,14 +971,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -934,14 +1069,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -950,13 +1090,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -965,13 +1110,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -979,11 +1129,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -997,11 +1152,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1015,12 +1175,17 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] @@ -1088,10 +1253,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -1100,11 +1270,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -1114,21 +1289,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=16 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=0 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -1138,12 +1323,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -1152,10 +1342,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -1165,12 +1360,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -1180,26 +1380,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -1208,10 +1418,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -1219,10 +1434,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -1230,21 +1450,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1258,11 +1488,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -1273,11 +1508,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -1285,10 +1525,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr index cda172af7..6faf0d2fc 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr @@ -1,6 +1,7 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: Not doing anything for miscreg ACTLR warn: Not doing anything for write of miscreg ACTLR diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index a7a925724..82b86dbb8 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -3,16 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:45:42 -gem5 started Jan 21 2016 14:46:33 -gem5 executing on zizzer, pid 20752 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:38:22 +gem5 executing on e108600-lin, pid 23078 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 +info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2783854535000 because m5_exit instruction encountered +Exiting @ tick 2783855034000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index e85c0f849..d33acaf94 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.783855 # Number of seconds simulated -sim_ticks 2783854535000 # Number of ticks simulated -final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2783855034000 # Number of ticks simulated +final_tick 2783855034000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 972221 # Simulator instruction rate (inst/s) -host_op_rate 1183523 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18956985191 # Simulator tick rate (ticks/s) -host_mem_usage 578524 # Number of bytes of host memory used -host_seconds 146.85 # Real time elapsed on the host -sim_insts 142771651 # Number of instructions simulated -sim_ops 173801592 # Number of ops (including micro ops) simulated +host_inst_rate 694880 # Simulator instruction rate (inst/s) +host_op_rate 845905 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13549194588 # Simulator tick rate (ticks/s) +host_mem_usage 573680 # Number of bytes of host memory used +host_seconds 205.46 # Real time elapsed on the host +sim_insts 142771937 # Number of instructions simulated +sim_ops 173801895 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10324836 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10324900 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11533384 # Number of bytes read from this memory +system.physmem.bytes_read::total 11533448 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 8840960 # Number of bytes written to this memory @@ -28,31 +28,31 @@ system.physmem.bytes_written::total 8858484 # Nu system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 161845 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 161846 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189182 # Number of read requests responded to by this memory +system.physmem.num_reads::total 189183 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 138140 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::total 142521 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3708827 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3708850 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4142955 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4142977 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 3175798 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3182093 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3182092 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 3175798 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3715122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3715145 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7325048 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states +system.physmem.bw_total::total 7325070 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -65,9 +65,9 @@ system.realview.nvmem.bw_inst_read::cpu.inst 7 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -75,7 +75,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -105,7 +105,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 10028 # Table walker walks requested system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency @@ -126,9 +126,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31525950 # DTB read hits +system.cpu.dtb.read_hits 31526014 # DTB read hits system.cpu.dtb.read_misses 8580 # DTB read misses -system.cpu.dtb.write_hits 23124105 # DTB write hits +system.cpu.dtb.write_hits 23124171 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -139,13 +139,13 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534530 # DTB read accesses -system.cpu.dtb.write_accesses 23125553 # DTB write accesses +system.cpu.dtb.read_accesses 31534594 # DTB read accesses +system.cpu.dtb.write_accesses 23125619 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54650055 # DTB hits +system.cpu.dtb.hits 54650185 # DTB hits system.cpu.dtb.misses 10028 # DTB misses -system.cpu.dtb.accesses 54660083 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.accesses 54660213 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -175,7 +175,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 4762 # Table walker walks requested system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency @@ -194,7 +194,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 147038166 # ITB inst hits +system.cpu.itb.inst_hits 147038452 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -211,55 +211,55 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 147042928 # ITB inst accesses -system.cpu.itb.hits 147038166 # DTB hits +system.cpu.itb.inst_accesses 147043214 # ITB inst accesses +system.cpu.itb.hits 147038452 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 147042928 # DTB accesses +system.cpu.itb.accesses 147043214 # DTB accesses system.cpu.numPwrStateTransitions 6160 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 3080 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 874939482.384091 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17329944773.080986 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 874939595.358117 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17329944407.298908 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 3002 97.47% 97.47% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 72 2.34% 99.81% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 3080 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 89040929257 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2694813605743 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5567712151 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 89041080297 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2694813953703 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 5567713149 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed -system.cpu.committedInsts 142771651 # Number of instructions committed -system.cpu.committedOps 173801592 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 153161279 # Number of integer alu accesses +system.cpu.committedInsts 142771937 # Number of instructions committed +system.cpu.committedOps 173801895 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 153161571 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses -system.cpu.num_func_calls 16873962 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18730275 # number of instructions that are conditional controls -system.cpu.num_int_insts 153161279 # number of integer instructions +system.cpu.num_func_calls 16873976 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18730294 # number of instructions that are conditional controls +system.cpu.num_int_insts 153161571 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions -system.cpu.num_int_register_reads 285030145 # number of times the integer registers were read -system.cpu.num_int_register_writes 107178468 # number of times the integer registers were written +system.cpu.num_int_register_reads 285030696 # number of times the integer registers were read +system.cpu.num_int_register_writes 107178579 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 530849543 # number of times the CC registers were read -system.cpu.num_cc_register_writes 62363904 # number of times the CC registers were written -system.cpu.num_mem_refs 55938616 # number of memory refs -system.cpu.num_load_insts 31855585 # Number of load instructions -system.cpu.num_store_insts 24083031 # Number of store instructions -system.cpu.num_idle_cycles 5389630193.939007 # Number of idle cycles -system.cpu.num_busy_cycles 178081957.060993 # Number of busy cycles +system.cpu.num_cc_register_reads 530850452 # number of times the CC registers were read +system.cpu.num_cc_register_writes 62364047 # number of times the CC registers were written +system.cpu.num_mem_refs 55938751 # number of memory refs +system.cpu.num_load_insts 31855653 # Number of load instructions +system.cpu.num_store_insts 24083098 # Number of store instructions +system.cpu.num_idle_cycles 5389630889.858858 # Number of idle cycles +system.cpu.num_busy_cycles 178082259.141142 # Number of busy cycles system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles system.cpu.idle_fraction 0.968015 # Percentage of idle cycles -system.cpu.Branches 36396978 # Number of branches fetched +system.cpu.Branches 36397005 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 121152037 68.36% 68.36% # Class of executed instruction -system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction +system.cpu.op_class::IntAlu 121152199 68.36% 68.36% # Class of executed instruction +system.cpu.op_class::IntMult 116879 0.07% 68.43% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction @@ -287,17 +287,17 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::MemRead 31855585 17.98% 86.41% # Class of executed instruction -system.cpu.op_class::MemWrite 24083031 13.59% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 31855653 17.98% 86.41% # Class of executed instruction +system.cpu.op_class::MemWrite 24083098 13.59% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 177218432 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 819392 # number of replacements +system.cpu.op_class::total 177218735 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 819389 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53783872 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.597768 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 53784005 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819901 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.598170 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -307,63 +307,63 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219235088 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219235088 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 30128801 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30128801 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22339792 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22339792 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 219235605 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219235605 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 30128867 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30128867 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22339858 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22339858 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 395067 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 395067 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 457333 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 457333 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52468593 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52468593 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52863658 # number of overall hits -system.cpu.dcache.overall_hits::total 52863658 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 396281 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 396281 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 52468725 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52468725 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52863792 # number of overall hits +system.cpu.dcache.overall_hits::total 52863792 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 396279 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 396279 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116119 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116119 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 697944 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses -system.cpu.dcache.overall_misses::total 814065 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30525082 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30525082 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641455 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641455 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 697942 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 697942 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 814061 # number of overall misses +system.cpu.dcache.overall_misses::total 814061 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 30525146 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30525146 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641521 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641521 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53166537 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53166537 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53677723 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53677723 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 53166667 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53166667 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53677853 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53677853 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227156 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.227156 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018483 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018483 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.013127 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.013127 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -374,13 +374,13 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks system.cpu.dcache.writebacks::total 682017 # number of writebacks -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1698998 # number of replacements +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1698989 # number of replacements system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145341757 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1699510 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 85.519801 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.total_refs 145342052 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1699501 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 85.520427 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 7831497000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy @@ -390,27 +390,27 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77 system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 148740789 # Number of tag accesses -system.cpu.icache.tags.data_accesses 148740789 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 145341757 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145341757 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145341757 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145341757 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145341757 # number of overall hits -system.cpu.icache.overall_hits::total 145341757 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1699516 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1699516 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1699516 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1699516 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1699516 # number of overall misses -system.cpu.icache.overall_misses::total 1699516 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 147041273 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 147041273 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 147041273 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 147041273 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 147041273 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 147041273 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 148741066 # Number of tag accesses +system.cpu.icache.tags.data_accesses 148741066 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 145342052 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145342052 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 145342052 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 145342052 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 145342052 # number of overall hits +system.cpu.icache.overall_hits::total 145342052 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1699507 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699507 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1699507 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699507 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1699507 # number of overall misses +system.cpu.icache.overall_misses::total 1699507 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 147041559 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 147041559 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 147041559 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 147041559 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 147041559 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 147041559 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses @@ -423,21 +423,21 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1698998 # number of writebacks -system.cpu.icache.writebacks::total 1698998 # number of writebacks -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 109913 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65155.314985 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4524855 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 25.827682 # Average number of references to valid blocks. +system.cpu.icache.writebacks::writebacks 1698989 # number of writebacks +system.cpu.icache.writebacks::total 1698989 # number of writebacks +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 109914 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65155.312641 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4524828 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 175195 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.827381 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 48764.050695 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 48764.064013 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931994 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.704513 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.623437 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.744080 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.693007 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.619283 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.744081 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139903 # Average percentage of cache occupancy @@ -453,34 +453,34 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40578944 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40578944 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.tag_accesses 40578737 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40578737 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 11218 # number of ReadReq hits system.cpu.l2cache.WritebackDirty_hits::writebacks 682017 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 682017 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1666999 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1666999 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1666988 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1666988 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 151131 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 151131 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681201 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1681201 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505445 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 505445 # number of ReadSharedReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 151130 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 151130 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681192 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1681192 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505442 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 505442 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1681201 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 656576 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2348995 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1681192 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 656572 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2348982 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1681201 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 656576 # number of overall hits -system.cpu.l2cache.overall_hits::total 2348995 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681192 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 656572 # number of overall hits +system.cpu.l2cache.overall_hits::total 2348982 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses @@ -488,8 +488,8 @@ system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 147776 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 147776 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 147777 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 147777 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18298 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15568 # number of ReadSharedReq misses @@ -497,40 +497,40 @@ system.cpu.l2cache.ReadSharedReq_misses::total 15568 system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 18298 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 163344 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 181651 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 163345 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 181652 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 163344 # number of overall misses -system.cpu.l2cache.overall_misses::total 181651 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 163345 # number of overall misses +system.cpu.l2cache.overall_misses::total 181652 # number of overall misses system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 11227 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::writebacks 682017 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 682017 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1666999 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1666999 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1666988 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1666988 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699499 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1699499 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521013 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 521013 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699490 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1699490 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521010 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 521010 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1699499 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819920 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2530646 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699490 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819917 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2530634 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1699499 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819920 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2530646 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699490 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819917 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2530634 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.000802 # miss rate for ReadReq accesses @@ -538,8 +538,8 @@ system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494388 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.494388 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494391 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.494391 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010767 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029880 # miss rate for ReadSharedReq accesses @@ -547,13 +547,13 @@ system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029880 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010767 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.199219 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.071780 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.199221 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.071781 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010767 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.199219 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.071780 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.199221 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.071781 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -562,50 +562,51 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks system.cpu.l2cache.writebacks::total 101950 # number of writebacks -system.cpu.toL2Bus.snoop_filter.tot_requests 5059903 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540486 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5059879 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540474 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39263 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2288329 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2288317 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 682017 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1698998 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 137375 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1698989 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 137372 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699516 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 521013 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116074 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581970 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699507 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 521010 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116047 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581961 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7753470 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217540984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96306721 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7753434 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96306529 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 313958557 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 182975 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5318737 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018478 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.134674 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 313957213 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 182976 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 8840960 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5318714 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018479 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.134677 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5220455 98.15% 98.15% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 98282 1.85% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5220428 98.15% 98.15% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98286 1.85% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5318737 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.snoop_fanout::total 5318714 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -656,14 +657,14 @@ system.iobus.pkt_size_system.bridge.master::total 159061 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909892 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 227410175509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.909892 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -671,7 +672,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328176 # Number of tag accesses system.iocache.tags.data_accesses 328176 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses system.iocache.ReadReq_misses::total 240 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -704,64 +705,65 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.membus.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 40087 # Transaction distribution system.membus.trans_dist::ReadResp 74202 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution system.membus.trans_dist::WritebackDirty 138140 # Transaction distribution -system.membus.trans_dist::CleanEvict 8203 # Transaction distribution +system.membus.trans_dist::CleanEvict 8204 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution -system.membus.trans_dist::ReadExReq 145997 # Transaction distribution -system.membus.trans_dist::ReadExResp 145997 # Transaction distribution +system.membus.trans_dist::ReadExReq 145998 # Transaction distribution +system.membus.trans_dist::ReadExResp 145998 # Transaction distribution system.membus.trans_dist::ReadSharedReq 34115 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506581 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613941 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506584 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613944 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723299 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723302 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092476 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255449 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092540 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255513 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20586969 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20587033 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 434821 # Request fanout histogram +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 434823 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 434821 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 434823 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 434821 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 434823 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -793,28 +795,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- |