diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-11-03 10:14:42 -0600 |
---|---|---|
committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-11-03 10:14:42 -0600 |
commit | ae82551496155588786751a3a92191069488d7f3 (patch) | |
tree | e4521fdada5b41c67f3ba02e5ea058350364c33d /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic | |
parent | 2c2c3a4ce98480a4b14a72ceb6e43e268e7a1aee (diff) | |
download | gem5-ae82551496155588786751a3a92191069488d7f3.tar.xz |
tests: Update stats no match.
Bootloader I had on my sytem was an older version with a couple of
instruction differences.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic')
3 files changed, 207 insertions, 207 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 8b9ee8e26..ce59aa175 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -43,7 +43,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/work/gem5.ext/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index 624db6e54..f25d6db4c 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -1,13 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 15:46:15 -gem5 started Oct 29 2014 15:56:38 +gem5 compiled Oct 31 2014 10:01:44 +gem5 started Oct 31 2014 11:25:21 gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 - 0: system.cpu.isa: ISA system set to: 0x55e4b00 0x55e4b00 + 0: system.cpu.isa: ISA system set to: 0x5299680 0x5299680 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 @@ -28,4 +28,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2783853461500 because m5_exit instruction encountered +Exiting @ tick 2783854177000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index e8036ea95..5bbc68c06 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.783853 # Number of seconds simulated -sim_ticks 2783853461500 # Number of ticks simulated -final_tick 2783853461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.783854 # Number of seconds simulated +sim_ticks 2783854177000 # Number of ticks simulated +final_tick 2783854177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1369296 # Simulator instruction rate (inst/s) -host_op_rate 1666897 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26699855189 # Simulator tick rate (ticks/s) -host_mem_usage 553552 # Number of bytes of host memory used -host_seconds 104.26 # Real time elapsed on the host -sim_insts 142769281 # Number of instructions simulated -sim_ops 173798567 # Number of ops (including micro ops) simulated +host_inst_rate 1378246 # Simulator instruction rate (inst/s) +host_op_rate 1677793 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26874016957 # Simulator tick rate (ticks/s) +host_mem_usage 553624 # Number of bytes of host memory used +host_seconds 103.59 # Real time elapsed on the host +sim_insts 142771179 # Number of instructions simulated +sim_ops 173800939 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory @@ -21,56 +21,56 @@ system.physmem.bytes_read::cpu.data 10345892 # Nu system.physmem.bytes_read::total 11558408 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1210980 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6521472 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6521536 # Number of bytes written to this memory system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8857332 # Number of bytes written to this memory +system.physmem.bytes_written::total 8857396 # Number of bytes written to this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 27375 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 162174 # Number of read requests responded to by this memory system.physmem.num_reads::total 189573 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 101898 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 101899 # Number of write requests responded to by this memory system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142503 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142504 # Number of write requests responded to by this memory system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 435001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3716392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4151946 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3716391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4151944 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 435001 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2342606 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2342628 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3181680 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2342606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3181703 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2342628 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 435001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3722687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7333626 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read::cpu.inst 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 24 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 74236 # Transaction distribution -system.membus.trans_dist::ReadResp 74236 # Transaction distribution +system.physmem.bw_total::cpu.data 3722686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7333647 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 74235 # Transaction distribution +system.membus.trans_dist::ReadResp 74235 # Transaction distribution system.membus.trans_dist::WriteReq 27560 # Transaction distribution system.membus.trans_dist::WriteResp 27560 # Transaction distribution -system.membus.trans_dist::Writeback 101898 # Transaction distribution +system.membus.trans_dist::Writeback 101899 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution @@ -79,33 +79,33 @@ system.membus.trans_dist::UpgradeResp 4509 # Tr system.membus.trans_dist::ReadExReq 146085 # Transaction distribution system.membus.trans_dist::ReadExResp 146085 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498794 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606198 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498795 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606197 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 679126 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 679125 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096444 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259463 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096508 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259523 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20593159 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20593219 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 322857 # Request fanout histogram +system.membus.snoop_fanout::samples 322858 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 322857 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 322858 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 322857 # Request fanout histogram +system.membus.snoop_fanout::total 322858 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -222,9 +222,9 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31525428 # DTB read hits +system.cpu.dtb.read_hits 31525864 # DTB read hits system.cpu.dtb.read_misses 8580 # DTB read misses -system.cpu.dtb.write_hits 23123837 # DTB write hits +system.cpu.dtb.write_hits 23124034 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -235,12 +235,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534008 # DTB read accesses -system.cpu.dtb.write_accesses 23125285 # DTB write accesses +system.cpu.dtb.read_accesses 31534444 # DTB read accesses +system.cpu.dtb.write_accesses 23125482 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54649265 # DTB hits +system.cpu.dtb.hits 54649898 # DTB hits system.cpu.dtb.misses 10028 # DTB misses -system.cpu.dtb.accesses 54659293 # DTB accesses +system.cpu.dtb.accesses 54659926 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -262,7 +262,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 147035651 # ITB inst hits +system.cpu.itb.inst_hits 147037671 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -279,38 +279,38 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 147040413 # ITB inst accesses -system.cpu.itb.hits 147035651 # DTB hits +system.cpu.itb.inst_accesses 147042433 # ITB inst accesses +system.cpu.itb.hits 147037671 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 147040413 # DTB accesses -system.cpu.numCycles 5567710004 # number of cpu cycles simulated +system.cpu.itb.accesses 147042433 # DTB accesses +system.cpu.numCycles 5567711435 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 142769281 # Number of instructions committed -system.cpu.committedOps 173798567 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 153158502 # Number of integer alu accesses +system.cpu.committedInsts 142771179 # Number of instructions committed +system.cpu.committedOps 173800939 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 153160639 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses -system.cpu.num_func_calls 16873305 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18730015 # number of instructions that are conditional controls -system.cpu.num_int_insts 153158502 # number of integer instructions +system.cpu.num_func_calls 16873782 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18730247 # number of instructions that are conditional controls +system.cpu.num_int_insts 153160639 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions -system.cpu.num_int_register_reads 285052059 # number of times the integer registers were read -system.cpu.num_int_register_writes 107176408 # number of times the integer registers were written +system.cpu.num_int_register_reads 285056343 # number of times the integer registers were read +system.cpu.num_int_register_writes 107177999 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 530840054 # number of times the CC registers were read -system.cpu.num_cc_register_writes 62363143 # number of times the CC registers were written -system.cpu.num_mem_refs 55937812 # number of memory refs -system.cpu.num_load_insts 31855061 # Number of load instructions -system.cpu.num_store_insts 24082751 # Number of store instructions -system.cpu.num_idle_cycles 5389631214.604722 # Number of idle cycles -system.cpu.num_busy_cycles 178078789.395278 # Number of busy cycles -system.cpu.not_idle_fraction 0.031984 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.968016 # Percentage of idle cycles -system.cpu.Branches 36396067 # Number of branches fetched +system.cpu.num_cc_register_reads 530847533 # number of times the CC registers were read +system.cpu.num_cc_register_writes 62363805 # number of times the CC registers were written +system.cpu.num_mem_refs 55938446 # number of memory refs +system.cpu.num_load_insts 31855497 # Number of load instructions +system.cpu.num_store_insts 24082949 # Number of store instructions +system.cpu.num_idle_cycles 5389630153.939368 # Number of idle cycles +system.cpu.num_busy_cycles 178081281.060631 # Number of busy cycles +system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.968015 # Percentage of idle cycles +system.cpu.Branches 36396779 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 121149664 68.36% 68.36% # Class of executed instruction -system.cpu.op_class::IntMult 116881 0.07% 68.43% # Class of executed instruction +system.cpu.op_class::IntAlu 121151526 68.36% 68.36% # Class of executed instruction +system.cpu.op_class::IntMult 116878 0.07% 68.43% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction @@ -338,19 +338,19 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::MemRead 31855061 17.98% 86.41% # Class of executed instruction -system.cpu.op_class::MemWrite 24082751 13.59% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 31855497 17.98% 86.41% # Class of executed instruction +system.cpu.op_class::MemWrite 24082949 13.59% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 177215263 # Class of executed instruction +system.cpu.op_class::total 177217756 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 1698994 # number of replacements +system.cpu.icache.tags.replacements 1699006 # number of replacements system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145339246 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1699506 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 85.518525 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 7831492000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.total_refs 145341254 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 85.519102 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy @@ -360,26 +360,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77 system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 148738270 # Number of tag accesses -system.cpu.icache.tags.data_accesses 148738270 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 145339246 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145339246 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145339246 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145339246 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145339246 # number of overall hits -system.cpu.icache.overall_hits::total 145339246 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1699512 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1699512 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1699512 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1699512 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1699512 # number of overall misses -system.cpu.icache.overall_misses::total 1699512 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 147038758 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 147038758 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 147038758 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 147038758 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 147038758 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 147038758 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 148740302 # Number of tag accesses +system.cpu.icache.tags.data_accesses 148740302 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 145341254 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145341254 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 145341254 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 145341254 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 145341254 # number of overall hits +system.cpu.icache.overall_hits::total 145341254 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1699524 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699524 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1699524 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699524 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1699524 # number of overall misses +system.cpu.icache.overall_misses::total 1699524 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 147040778 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 147040778 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 147040778 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 147040778 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 147040778 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 147040778 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses @@ -396,16 +396,16 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 110027 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65155.315266 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2727659 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 65155.315047 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2727658 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 175308 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 15.559239 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 15.559233 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 48893.414938 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 48893.414337 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.653997 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.309992 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654547 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.309824 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy @@ -422,29 +422,29 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26202376 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26202376 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 26202377 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 26202377 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1681137 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 505491 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2197846 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 682038 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 682038 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1681149 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 505480 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2197847 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 682036 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 682036 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 151041 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 151041 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 151042 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 151042 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1681137 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 656532 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2348887 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1681149 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 656522 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2348889 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1681137 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 656532 # number of overall hits -system.cpu.l2cache.overall_hits::total 2348887 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681149 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 656522 # number of overall hits +system.cpu.l2cache.overall_hits::total 2348889 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 18358 # number of ReadReq misses @@ -468,47 +468,47 @@ system.cpu.l2cache.overall_misses::cpu.data 163398 # system.cpu.l2cache.overall_misses::total 181765 # number of overall misses system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699495 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 521025 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2231747 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 682038 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 682038 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699507 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 521014 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2231748 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 682036 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 682036 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 298905 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 298905 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 298906 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 298906 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1699495 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2530652 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699507 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819920 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2530654 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1699495 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2530652 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699507 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819920 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2530654 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010802 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029814 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.015190 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494686 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.494686 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494684 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.494684 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010802 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.199285 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.071825 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010802 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.199285 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.071825 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -518,15 +518,15 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks -system.cpu.l2cache.writebacks::total 101898 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 101899 # number of writebacks +system.cpu.l2cache.writebacks::total 101899 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 819402 # number of replacements +system.cpu.dcache.tags.replacements 819392 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53783051 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.595966 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 23054000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.total_refs 53783694 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.597550 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy @@ -535,56 +535,56 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219231854 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219231854 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 30128262 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30128262 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22339512 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22339512 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 395063 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 395063 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 219234376 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219234376 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 30128707 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30128707 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22339708 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22339708 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52467774 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52467774 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52862837 # number of overall hits -system.cpu.dcache.overall_hits::total 52862837 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 396291 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 396291 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 301661 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 301661 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 116123 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 116123 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 52468415 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52468415 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52863480 # number of overall hits +system.cpu.dcache.overall_hits::total 52863480 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 396282 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 396282 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 301662 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 301662 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 697952 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 697952 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 814075 # number of overall misses -system.cpu.dcache.overall_misses::total 814075 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30524553 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30524553 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641173 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641173 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 697944 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses +system.cpu.dcache.overall_misses::total 814065 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 30524989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30524989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641370 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641370 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53165726 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53165726 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53676912 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53676912 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012983 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227164 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.227164 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 53166359 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53166359 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53677545 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53677545 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses @@ -601,29 +601,29 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 682038 # number of writebacks -system.cpu.dcache.writebacks::total 682038 # number of writebacks +system.cpu.dcache.writebacks::writebacks 682036 # number of writebacks +system.cpu.dcache.writebacks::total 682036 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 2288345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2288345 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 682038 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 682036 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 298905 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 298905 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417070 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444678 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 298906 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 298906 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417092 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444656 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 5917174 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108804860 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308747 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96307979 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205224459 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205224455 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 36632 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 3268415 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram @@ -641,12 +641,12 @@ system.cpu.toL2Bus.snoop_fanout::min_value 5 # system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 3268415 # Request fanout histogram system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909886 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909891 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 227409698009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909886 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.909891 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id |