tests: Regression stats updated for recent patches

1 files changed, 37 insertions, 21 deletions

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index d7e6fcfdf..8acd582b2 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
+boot_loader=/dist/m5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
 default_p_state=UNDEFINED
-dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
+dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -30,7 +30,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -49,7 +49,7 @@ panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
 power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
+readfile=/z/powerjg/gem5-upstream/tests/testing/../halt.sh
 reset_addr_64=0
 symbolfile=
 thermal_components=
@@ -99,7 +99,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
+image_file=/dist/m5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -157,10 +157,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=2
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=6
@@ -174,6 +174,7 @@ response_latency=2
 sequential_access=false
 size=32768
 system=system
+tag_latency=2
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=8
 write_buffers=16
@@ -186,15 +187,16 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=2
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=32768
+tag_latency=2
 
 [system.cpu0.dstage2_mmu]
 type=ArmStage2MMU
@@ -254,10 +256,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=1
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=1
 is_read_only=true
 max_miss_count=0
 mshrs=2
@@ -271,6 +273,7 @@ response_latency=1
 sequential_access=false
 size=32768
 system=system
+tag_latency=1
 tags=system.cpu0.icache.tags
 tgts_per_mshr=8
 write_buffers=8
@@ -283,15 +286,16 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=1
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=1
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=32768
+tag_latency=1
 
 [system.cpu0.interrupts]
 type=ArmInterrupts
@@ -386,10 +390,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
+data_latency=12
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=12
 is_read_only=false
 max_miss_count=0
 mshrs=16
@@ -403,6 +407,7 @@ response_latency=12
 sequential_access=false
 size=1048576
 system=system
+tag_latency=12
 tags=system.cpu0.l2cache.tags
 tgts_per_mshr=8
 write_buffers=8
@@ -445,15 +450,16 @@ type=RandomRepl
 assoc=16
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=12
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=12
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=1048576
+tag_latency=12
 
 [system.cpu0.toL2Bus]
 type=CoherentXBar
@@ -535,10 +541,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=2
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=2
 is_read_only=false
 max_miss_count=0
 mshrs=6
@@ -552,6 +558,7 @@ response_latency=2
 sequential_access=false
 size=32768
 system=system
+tag_latency=2
 tags=system.cpu1.dcache.tags
 tgts_per_mshr=8
 write_buffers=16
@@ -564,15 +571,16 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=2
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=2
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=32768
+tag_latency=2
 
 [system.cpu1.dstage2_mmu]
 type=ArmStage2MMU
@@ -632,10 +640,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=2
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=1
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=1
 is_read_only=true
 max_miss_count=0
 mshrs=2
@@ -649,6 +657,7 @@ response_latency=1
 sequential_access=false
 size=32768
 system=system
+tag_latency=1
 tags=system.cpu1.icache.tags
 tgts_per_mshr=8
 write_buffers=8
@@ -661,15 +670,16 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=1
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=1
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=32768
+tag_latency=1
 
 [system.cpu1.interrupts]
 type=ArmInterrupts
@@ -764,10 +774,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=16
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_excl
+data_latency=12
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=12
 is_read_only=false
 max_miss_count=0
 mshrs=16
@@ -781,6 +791,7 @@ response_latency=12
 sequential_access=false
 size=1048576
 system=system
+tag_latency=12
 tags=system.cpu1.l2cache.tags
 tgts_per_mshr=8
 write_buffers=8
@@ -823,15 +834,16 @@ type=RandomRepl
 assoc=16
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=12
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=12
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=1048576
+tag_latency=12
 
 [system.cpu1.toL2Bus]
 type=CoherentXBar
@@ -911,10 +923,10 @@ addr_ranges=2147483648:2415919103:0:0:0:0
 assoc=8
 clk_domain=system.clk_domain
 clusivity=mostly_incl
+data_latency=50
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=50
 is_read_only=false
 max_miss_count=0
 mshrs=20
@@ -928,6 +940,7 @@ response_latency=50
 sequential_access=false
 size=1024
 system=system
+tag_latency=50
 tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
@@ -940,15 +953,16 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.clk_domain
+data_latency=50
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=50
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=1024
+tag_latency=50
 
 [system.l2c]
 type=Cache
@@ -957,10 +971,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
 assoc=8
 clk_domain=system.cpu_clk_domain
 clusivity=mostly_incl
+data_latency=20
 default_p_state=UNDEFINED
 demand_mshr_reserve=1
 eventq_index=0
-hit_latency=20
 is_read_only=false
 max_miss_count=0
 mshrs=20
@@ -974,6 +988,7 @@ response_latency=20
 sequential_access=false
 size=4194304
 system=system
+tag_latency=20
 tags=system.l2c.tags
 tgts_per_mshr=12
 write_buffers=8
@@ -986,15 +1001,16 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+data_latency=20
 default_p_state=UNDEFINED
 eventq_index=0
-hit_latency=20
 p_state_clk_gate_bins=20
 p_state_clk_gate_max=1000000000000
 p_state_clk_gate_min=1000
 power_model=Null
 sequential_access=false
 size=4194304
+tag_latency=20
 
 [system.membus]
 type=CoherentXBar