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author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-02-16 11:40:34 -0600 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-02-16 11:40:34 -0600 |
commit | 5abbb84f02d4688956a6a042eca2fc0c02f60ae7 (patch) | |
tree | 7c3373d68f29cb80e6378e3f0c5b3a6513d73d71 /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt | |
parent | 0a44e16948fa7274a7890a2bb8710473122f5eca (diff) | |
download | gem5-5abbb84f02d4688956a6a042eca2fc0c02f60ae7.tar.xz |
stats: updates due to branch predictor warming
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt')
-rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt | 48 |
1 files changed, 25 insertions, 23 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 6ed9b7b45..dfe5d9e95 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -4,15 +4,33 @@ sim_seconds 1.196139 # Nu sim_ticks 1196139241000 # Number of ticks simulated final_tick 1196139241000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 553961 # Simulator instruction rate (inst/s) -host_op_rate 705843 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10781179789 # Simulator tick rate (ticks/s) -host_mem_usage 425360 # Number of bytes of host memory used -host_seconds 110.95 # Real time elapsed on the host +host_inst_rate 363491 # Simulator instruction rate (inst/s) +host_op_rate 463152 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7074263356 # Simulator tick rate (ticks/s) +host_mem_usage 480032 # Number of bytes of host memory used +host_seconds 169.08 # Real time elapsed on the host sim_insts 61460236 # Number of instructions simulated sim_ops 78311148 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory @@ -610,24 +628,6 @@ system.physmem.writeRowHitRate 83.49 # Ro system.physmem.avgGap 160007.15 # Average gap between requests system.physmem.pageHitRate 98.90 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 4.90 # Percentage of time for which DRAM has all the banks in precharge state -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) system.membus.throughput 59936382 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 7703367 # Transaction distribution system.membus.trans_dist::ReadResp 7703367 # Transaction distribution @@ -1396,6 +1396,7 @@ system.cpu0.num_idle_cycles 2246536230.490122 system.cpu0.num_busy_cycles 145742251.509878 # Number of busy cycles system.cpu0.not_idle_fraction 0.060922 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.939078 # Percentage of idle cycles +system.cpu0.Branches 5599941 # Number of branches fetched system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 46939 # number of quiesce instructions executed system.cpu0.icache.tags.replacements 424872 # number of replacements @@ -1758,6 +1759,7 @@ system.cpu1.num_idle_cycles 1874235342.195830 system.cpu1.num_busy_cycles 516568442.804169 # Number of busy cycles system.cpu1.not_idle_fraction 0.216065 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.783935 # Percentage of idle cycles +system.cpu1.Branches 4947677 # Number of branches fetched system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 44317 # number of quiesce instructions executed system.cpu1.icache.tags.replacements 469929 # number of replacements |