diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt | 4746 |
1 files changed, 2387 insertions, 2359 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index b27032bf8..dc9310742 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,158 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.869797 # Number of seconds simulated -sim_ticks 2869796829000 # Number of ticks simulated -final_tick 2869796829000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.870001 # Number of seconds simulated +sim_ticks 2870000710000 # Number of ticks simulated +final_tick 2870000710000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 478807 # Simulator instruction rate (inst/s) -host_op_rate 579136 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10450673539 # Simulator tick rate (ticks/s) -host_mem_usage 612484 # Number of bytes of host memory used -host_seconds 274.60 # Real time elapsed on the host -sim_insts 131482259 # Number of instructions simulated -sim_ops 159033076 # Number of ops (including micro ops) simulated +host_inst_rate 371570 # Simulator instruction rate (inst/s) +host_op_rate 449436 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8101953096 # Simulator tick rate (ticks/s) +host_mem_usage 621024 # Number of bytes of host memory used +host_seconds 354.24 # Real time elapsed on the host +sim_insts 131623434 # Number of instructions simulated +sim_ops 159206188 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1151908 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1242084 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8334784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147092 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 510612 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 354880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1182180 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1312420 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8596224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 150484 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 578772 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 396096 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11742896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1151908 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147092 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1299000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8345408 # Number of bytes written to this memory +system.physmem.bytes_read::total 12217776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1182180 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 150484 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1332664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8789056 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8362972 # Number of bytes written to this memory +system.physmem.bytes_written::total 8806620 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26452 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 19927 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 130231 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2453 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 7999 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 5545 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26925 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21026 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134316 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2506 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6189 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 192631 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 130397 # Number of write requests responded to by this memory +system.physmem.num_reads::total 200051 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 137329 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 134788 # Number of write requests responded to by this memory +system.physmem.num_writes::total 141720 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 401390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 432813 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2904312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 51255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 177926 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 123660 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4091891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 401390 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 51255 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 452645 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2908014 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 411909 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 457289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2995199 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52433 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 201663 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 138013 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4257064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 411909 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52433 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 464343 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3062388 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6106 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2914134 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2908014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3068508 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3062388 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 401390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 438919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2904312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 51255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 177940 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 123660 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7006025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 192631 # Number of read requests accepted -system.physmem.writeReqs 134788 # Number of write requests accepted -system.physmem.readBursts 192631 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 134788 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12319616 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue -system.physmem.bytesWritten 8376000 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11742896 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8362972 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 411909 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 463395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2995199 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 52433 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 201677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 138013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7325572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 200051 # Number of read requests accepted +system.physmem.writeReqs 141720 # Number of write requests accepted +system.physmem.readBursts 200051 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 141720 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12793920 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue +system.physmem.bytesWritten 8819520 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12217776 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8806620 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11574 # Per bank write bursts -system.physmem.perBankRdBursts::1 11705 # Per bank write bursts -system.physmem.perBankRdBursts::2 12139 # Per bank write bursts -system.physmem.perBankRdBursts::3 12297 # Per bank write bursts -system.physmem.perBankRdBursts::4 20811 # Per bank write bursts -system.physmem.perBankRdBursts::5 12493 # Per bank write bursts -system.physmem.perBankRdBursts::6 11636 # Per bank write bursts -system.physmem.perBankRdBursts::7 11627 # Per bank write bursts -system.physmem.perBankRdBursts::8 11518 # Per bank write bursts -system.physmem.perBankRdBursts::9 11803 # Per bank write bursts -system.physmem.perBankRdBursts::10 10854 # Per bank write bursts -system.physmem.perBankRdBursts::11 10225 # Per bank write bursts -system.physmem.perBankRdBursts::12 10900 # Per bank write bursts -system.physmem.perBankRdBursts::13 11460 # Per bank write bursts -system.physmem.perBankRdBursts::14 10649 # Per bank write bursts -system.physmem.perBankRdBursts::15 10803 # Per bank write bursts -system.physmem.perBankWrBursts::0 8359 # Per bank write bursts -system.physmem.perBankWrBursts::1 8644 # Per bank write bursts -system.physmem.perBankWrBursts::2 9057 # Per bank write bursts -system.physmem.perBankWrBursts::3 8858 # Per bank write bursts -system.physmem.perBankWrBursts::4 8408 # Per bank write bursts -system.physmem.perBankWrBursts::5 8900 # Per bank write bursts -system.physmem.perBankWrBursts::6 8435 # Per bank write bursts -system.physmem.perBankWrBursts::7 8166 # Per bank write bursts -system.physmem.perBankWrBursts::8 8021 # Per bank write bursts -system.physmem.perBankWrBursts::9 8475 # Per bank write bursts -system.physmem.perBankWrBursts::10 7798 # Per bank write bursts -system.physmem.perBankWrBursts::11 7415 # Per bank write bursts -system.physmem.perBankWrBursts::12 7820 # Per bank write bursts -system.physmem.perBankWrBursts::13 7815 # Per bank write bursts -system.physmem.perBankWrBursts::14 7421 # Per bank write bursts -system.physmem.perBankWrBursts::15 7283 # Per bank write bursts +system.physmem.perBankRdBursts::0 11709 # Per bank write bursts +system.physmem.perBankRdBursts::1 12160 # Per bank write bursts +system.physmem.perBankRdBursts::2 12038 # Per bank write bursts +system.physmem.perBankRdBursts::3 12178 # Per bank write bursts +system.physmem.perBankRdBursts::4 20671 # Per bank write bursts +system.physmem.perBankRdBursts::5 12806 # Per bank write bursts +system.physmem.perBankRdBursts::6 12086 # Per bank write bursts +system.physmem.perBankRdBursts::7 12477 # Per bank write bursts +system.physmem.perBankRdBursts::8 12638 # Per bank write bursts +system.physmem.perBankRdBursts::9 12504 # Per bank write bursts +system.physmem.perBankRdBursts::10 11795 # Per bank write bursts +system.physmem.perBankRdBursts::11 11324 # Per bank write bursts +system.physmem.perBankRdBursts::12 11594 # Per bank write bursts +system.physmem.perBankRdBursts::13 11843 # Per bank write bursts +system.physmem.perBankRdBursts::14 11003 # Per bank write bursts +system.physmem.perBankRdBursts::15 11079 # Per bank write bursts +system.physmem.perBankWrBursts::0 8559 # Per bank write bursts +system.physmem.perBankWrBursts::1 9022 # Per bank write bursts +system.physmem.perBankWrBursts::2 9017 # Per bank write bursts +system.physmem.perBankWrBursts::3 8844 # Per bank write bursts +system.physmem.perBankWrBursts::4 8437 # Per bank write bursts +system.physmem.perBankWrBursts::5 9230 # Per bank write bursts +system.physmem.perBankWrBursts::6 8825 # Per bank write bursts +system.physmem.perBankWrBursts::7 8866 # Per bank write bursts +system.physmem.perBankWrBursts::8 9056 # Per bank write bursts +system.physmem.perBankWrBursts::9 8974 # Per bank write bursts +system.physmem.perBankWrBursts::10 8482 # Per bank write bursts +system.physmem.perBankWrBursts::11 8329 # Per bank write bursts +system.physmem.perBankWrBursts::12 8472 # Per bank write bursts +system.physmem.perBankWrBursts::13 8225 # Per bank write bursts +system.physmem.perBankWrBursts::14 7833 # Per bank write bursts +system.physmem.perBankWrBursts::15 7634 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 25 # Number of times write queue was full causing retry -system.physmem.totGap 2869796310500 # Total gap between requests +system.physmem.numWrRetry 37 # Number of times write queue was full causing retry +system.physmem.totGap 2870000192000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9732 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 182871 # Read request sizes (log2) +system.physmem.readPktSize::6 190291 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 130397 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 135454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 15340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 9792 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6685 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5269 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4441 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3740 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 102 # What read queue length does an incoming req see +system.physmem.writePktSize::6 137329 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 139673 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 16007 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7050 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4708 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 97 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 43 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -181,165 +185,164 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6707 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 97 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 85101 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 243.188118 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 136.988063 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 305.573889 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45210 53.13% 53.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16886 19.84% 72.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5688 6.68% 79.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3460 4.07% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2293 2.69% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1445 1.70% 88.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 997 1.17% 89.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 929 1.09% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8193 9.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 85101 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6403 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.062939 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 590.633185 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6402 99.98% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6403 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6403 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.439638 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.792302 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.006159 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5407 84.44% 84.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 293 4.58% 89.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 63 0.98% 90.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 46 0.72% 90.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 252 3.94% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 29 0.45% 95.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 22 0.34% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 17 0.27% 95.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 14 0.22% 95.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.12% 96.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.08% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 12 0.19% 96.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 163 2.55% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.06% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 10 0.16% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 4 0.06% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 10 0.16% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 4 0.06% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.06% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.05% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 5 0.08% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 9 0.14% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6403 # Writes before turning the bus around for reads -system.physmem.totQLat 4388531068 # Total ticks spent queuing -system.physmem.totMemAccLat 7997793568 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 962470000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22798.27 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::44 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 128 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 85925 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 251.537690 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 143.363316 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 306.826134 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 42893 49.92% 49.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18336 21.34% 71.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6281 7.31% 78.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3896 4.53% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2533 2.95% 86.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1590 1.85% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1050 1.22% 89.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 985 1.15% 90.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8361 9.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 85925 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6834 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.251244 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 562.918265 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6833 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6834 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6834 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.164618 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.651361 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.320527 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5790 84.72% 84.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 323 4.73% 89.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 59 0.86% 90.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 46 0.67% 90.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 267 3.91% 94.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 35 0.51% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 21 0.31% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 28 0.41% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 23 0.34% 96.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 7 0.10% 96.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 12 0.18% 96.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 155 2.27% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.04% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.07% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 6 0.09% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 12 0.18% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.01% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 6 0.09% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.01% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.16% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6834 # Writes before turning the bus around for reads +system.physmem.totQLat 4674239132 # Total ticks spent queuing +system.physmem.totMemAccLat 8422457882 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 999525000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23382.30 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41548.27 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.29 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.09 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.91 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 42132.30 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.46 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.07 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.07 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.14 # Average write queue length when enqueuing -system.physmem.readRowHits 160943 # Number of row buffer hits during reads -system.physmem.writeRowHits 77324 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.07 # Row buffer hit rate for writes -system.physmem.avgGap 8764904.63 # Average gap between requests -system.physmem.pageHitRate 73.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 343133280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 187225500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 813391800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 445998960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187440976320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 84650934555 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1647621183000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1921502843415 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.561249 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2740835391788 # Time in different power states -system.physmem_0.memoryStateTime::REF 95828720000 # Time in different power states +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.74 # Average write queue length when enqueuing +system.physmem.readRowHits 166683 # Number of row buffer hits during reads +system.physmem.writeRowHits 85101 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 61.75 # Row buffer hit rate for writes +system.physmem.avgGap 8397436.27 # Average gap between requests +system.physmem.pageHitRate 74.55 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 335240640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 182919000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 827767200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 458784000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187454198880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 84698340030 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647701064750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1921658314500 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.568191 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2740964082488 # Time in different power states +system.physmem_0.memoryStateTime::REF 95835480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33132603712 # Time in different power states +system.physmem_0.memoryStateTime::ACT 33201034512 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 300230280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 163816125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 688053600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 402071040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187440976320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 83039782815 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1649034474000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1921069404180 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.410214 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2743194226190 # Time in different power states -system.physmem_1.memoryStateTime::REF 95828720000 # Time in different power states +system.physmem_1.actEnergy 314352360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 171521625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 731484000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 434192400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187454198880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 83981561895 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1648329817500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1921417128660 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.484154 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2742009812705 # Time in different power states +system.physmem_1.memoryStateTime::REF 95835480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30771048810 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32151144795 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -358,9 +361,9 @@ system.realview.nvmem.bw_inst_read::total 24 # I system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -368,7 +371,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -398,61 +401,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 7605 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 7605 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1343 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6262 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 7605 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 7605 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 7605 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6211 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12321.365320 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11473.330493 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5604.476225 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 5759 92.72% 92.72% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 412 6.63% 99.36% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 31 0.50% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.06% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 7878 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7878 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1506 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6372 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7878 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7878 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7878 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6484 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12295.265268 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11397.219739 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5676.180841 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 5980 92.23% 92.23% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 464 7.16% 99.38% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 34 0.52% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 1 0.02% 99.92% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.95% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6211 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6484 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 1125817500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 1125817500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 1125817500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 4907 79.00% 79.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1304 21.00% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6211 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7605 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5017 77.38% 77.38% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1467 22.62% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6484 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7878 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7605 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6211 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7878 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6484 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6211 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 13816 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6484 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 14362 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 22785353 # DTB read hits -system.cpu0.dtb.read_misses 6506 # DTB read misses -system.cpu0.dtb.write_hits 17536845 # DTB write hits -system.cpu0.dtb.write_misses 1099 # DTB write misses +system.cpu0.dtb.read_hits 25174501 # DTB read hits +system.cpu0.dtb.read_misses 6776 # DTB read misses +system.cpu0.dtb.write_hits 18763964 # DTB write hits +system.cpu0.dtb.write_misses 1102 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3343 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3391 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1756 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1765 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 22791859 # DTB read accesses -system.cpu0.dtb.write_accesses 17537944 # DTB write accesses +system.cpu0.dtb.read_accesses 25181277 # DTB read accesses +system.cpu0.dtb.write_accesses 18765066 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 40322198 # DTB hits -system.cpu0.dtb.misses 7605 # DTB misses -system.cpu0.dtb.accesses 40329803 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 43938465 # DTB hits +system.cpu0.dtb.misses 7878 # DTB misses +system.cpu0.dtb.accesses 43946343 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -482,7 +485,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.cpu0.itb.walker.walks 3349 # Table walker walks requested system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate @@ -491,16 +494,16 @@ system.cpu0.itb.walker.walkWaitTime::samples 3349 system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12840.762966 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 12002.591700 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5837.643760 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 347 14.87% 14.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1703 73.00% 87.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 210 9.00% 96.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 26 1.11% 97.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 42 1.80% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.09% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12613.587655 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11778.875659 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5637.639193 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 386 16.55% 16.55% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1666 71.41% 87.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 225 9.64% 97.60% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 26 1.11% 98.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 26 1.11% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.91% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::total 2333 # Table walker service (enqueue to completion) latency @@ -517,7 +520,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 5682 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 108479195 # ITB inst hits +system.cpu0.itb.inst_hits 119077538 # ITB inst hits system.cpu0.itb.inst_misses 3349 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -534,771 +537,780 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 108482544 # ITB inst accesses -system.cpu0.itb.hits 108479195 # DTB hits +system.cpu0.itb.inst_accesses 119080887 # ITB inst accesses +system.cpu0.itb.hits 119077538 # DTB hits system.cpu0.itb.misses 3349 # DTB misses -system.cpu0.itb.accesses 108482544 # DTB accesses -system.cpu0.numPwrStateTransitions 3748 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1874 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1464520585.209178 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23650117166.731750 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1082 57.74% 57.74% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 787 42.00% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.itb.accesses 119080887 # DTB accesses +system.cpu0.numPwrStateTransitions 3762 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1881 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1452265205.015417 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23608911235.366570 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1082 57.52% 57.52% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 794 42.21% 99.73% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499966342824 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1874 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 125285252318 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2744511576682 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 5739593658 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 499963656512 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1881 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 138289859366 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731710850634 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 5740001420 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1874 # number of quiesce instructions executed -system.cpu0.committedInsts 105397426 # Number of instructions committed -system.cpu0.committedOps 127063433 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 112192231 # Number of integer alu accesses +system.cpu0.kern.inst.quiesce 1881 # number of quiesce instructions executed +system.cpu0.committedInsts 115412619 # Number of instructions committed +system.cpu0.committedOps 139453859 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 123427491 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses -system.cpu0.num_func_calls 10407708 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14566669 # number of instructions that are conditional controls -system.cpu0.num_int_insts 112192231 # number of integer instructions +system.cpu0.num_func_calls 12678366 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 15706258 # number of instructions that are conditional controls +system.cpu0.num_int_insts 123427491 # number of integer instructions system.cpu0.num_fp_insts 9820 # number of float instructions -system.cpu0.num_int_register_reads 204833184 # number of times the integer registers were read -system.cpu0.num_int_register_writes 77435370 # number of times the integer registers were written +system.cpu0.num_int_register_reads 227200136 # number of times the integer registers were read +system.cpu0.num_int_register_writes 85767213 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 459130085 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 48875384 # number of times the CC registers were written -system.cpu0.num_mem_refs 41457196 # number of memory refs -system.cpu0.num_load_insts 23036367 # Number of load instructions -system.cpu0.num_store_insts 18420829 # Number of store instructions -system.cpu0.num_idle_cycles 5489023153.362087 # Number of idle cycles -system.cpu0.num_busy_cycles 250570504.637913 # Number of busy cycles -system.cpu0.not_idle_fraction 0.043656 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.956344 # Percentage of idle cycles -system.cpu0.Branches 25689353 # Number of branches fetched +system.cpu0.num_cc_register_reads 505219370 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 52317118 # number of times the CC registers were written +system.cpu0.num_mem_refs 45075192 # number of memory refs +system.cpu0.num_load_insts 25426401 # Number of load instructions +system.cpu0.num_store_insts 19648791 # Number of store instructions +system.cpu0.num_idle_cycles 5463421701.266096 # Number of idle cycles +system.cpu0.num_busy_cycles 276579718.733904 # Number of busy cycles +system.cpu0.not_idle_fraction 0.048185 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.951815 # Percentage of idle cycles +system.cpu0.Branches 29123439 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 88685820 68.09% 68.09% # Class of executed instruction -system.cpu0.op_class::IntMult 91693 0.07% 68.16% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8209 0.01% 68.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.17% # Class of executed instruction -system.cpu0.op_class::MemRead 23036367 17.69% 85.86% # Class of executed instruction -system.cpu0.op_class::MemWrite 18420829 14.14% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 98023875 68.44% 68.44% # Class of executed instruction +system.cpu0.op_class::IntMult 109907 0.08% 68.52% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8209 0.01% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::MemRead 25426401 17.75% 86.28% # Class of executed instruction +system.cpu0.op_class::MemWrite 19648791 13.72% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 130245191 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 690306 # number of replacements -system.cpu0.dcache.tags.tagsinuse 490.313655 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 39473136 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 690818 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 57.139704 # Average number of references to valid blocks. +system.cpu0.op_class::total 143219456 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 693439 # number of replacements +system.cpu0.dcache.tags.tagsinuse 491.449824 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43066582 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 693951 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 62.059975 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1151827000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 490.313655 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.957644 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.957644 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 491.449824 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.959863 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.959863 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 81317769 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 81317769 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 21536394 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 21536394 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 16814376 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 16814376 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319053 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 319053 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365550 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365550 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362389 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 362389 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 38350770 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 38350770 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 38669823 # number of overall hits -system.cpu0.dcache.overall_hits::total 38669823 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 394644 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 394644 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 324668 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 324668 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127577 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 127577 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21580 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21580 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19821 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19821 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 719312 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 719312 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 846889 # number of overall misses -system.cpu0.dcache.overall_misses::total 846889 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5059230000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5059230000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5720917500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5720917500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 328019500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 328019500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 473718500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 473718500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1421500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1421500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 10780147500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 10780147500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 10780147500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 10780147500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 21931038 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 21931038 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 17139044 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 17139044 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446630 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446630 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387130 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 387130 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382210 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 382210 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 39070082 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 39070082 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 39516712 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 39516712 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.017995 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.017995 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018943 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018943 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285644 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285644 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055744 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055744 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051859 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051859 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018411 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.018411 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021431 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.021431 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12819.731201 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12819.731201 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17620.823426 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17620.823426 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15200.162187 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15200.162187 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23899.828465 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23899.828465 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 88514427 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88514427 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 23911425 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23911425 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 18032865 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18032865 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319065 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 319065 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365782 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 365782 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362736 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 362736 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 41944290 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41944290 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 42263355 # number of overall hits +system.cpu0.dcache.overall_hits::total 42263355 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 397667 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 397667 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 324388 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 324388 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127754 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 127754 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21573 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21573 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19602 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 19602 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 722055 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 722055 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 849809 # number of overall misses +system.cpu0.dcache.overall_misses::total 849809 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5269907000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5269907000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5597938000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5597938000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 327322000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 327322000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 460475500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 460475500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1158000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1158000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 10867845000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 10867845000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 10867845000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 10867845000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 24309092 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 24309092 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 18357253 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 18357253 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446819 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446819 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387355 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 387355 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382338 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 382338 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 42666345 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42666345 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 43113164 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43113164 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016359 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.016359 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017671 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017671 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285919 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285919 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055693 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055693 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051269 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051269 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016923 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016923 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019711 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.019711 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13252.060141 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13252.060141 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17256.920725 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17256.920725 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15172.762249 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15172.762249 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23491.250893 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23491.250893 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14986.747753 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14986.747753 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12729.115032 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12729.115032 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15051.270333 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15051.270333 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12788.573668 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12788.573668 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 690306 # number of writebacks -system.cpu0.dcache.writebacks::total 690306 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25258 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25258 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14953 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14953 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 25258 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 25258 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25258 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 25258 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 369386 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 369386 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324668 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 324668 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100493 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 100493 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6627 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6627 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19821 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 19821 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 694054 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 694054 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 794547 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 794547 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 21106 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 21106 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19680 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19680 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 40786 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 40786 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4295278500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4295278500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5396249500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5396249500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1609240500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1609240500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 98443000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98443000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 453938500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 453938500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1380500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1380500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9691528000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9691528000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11300768500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11300768500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4679128000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4679128000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4679128000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4679128000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016843 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016843 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018943 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018943 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225003 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225003 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017118 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017118 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051859 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051859 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017764 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.017764 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020107 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.020107 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11628.157266 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11628.157266 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16620.823426 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16620.823426 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16013.458649 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16013.458649 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14854.836276 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14854.836276 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22901.896978 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22901.896978 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 693439 # number of writebacks +system.cpu0.dcache.writebacks::total 693439 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25271 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25271 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15260 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15260 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25271 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25271 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25271 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25271 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 372396 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 372396 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324388 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 324388 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100689 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 100689 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6313 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6313 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19602 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19602 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 696784 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 696784 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 797473 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 797473 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31786 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31786 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60249 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60249 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4503432000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4503432000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5273550000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5273550000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1615902000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1615902000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94571500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94571500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 440907500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 440907500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1124000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1124000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9776982000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9776982000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11392884000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11392884000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628627500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628627500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628627500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628627500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015319 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015319 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017671 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017671 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225346 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225346 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016298 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016298 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051269 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051269 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016331 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016331 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018497 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018497 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12093.126672 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12093.126672 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16256.920725 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16256.920725 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16048.446206 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16048.446206 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14980.437193 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14980.437193 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22492.985410 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22492.985410 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13963.651243 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13963.651243 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14222.907518 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14222.907518 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221696.579172 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221696.579172 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 114723.875840 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 114723.875840 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1101713 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.449165 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 107376961 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1102225 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 97.418368 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 14058108000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.449165 # Average occupied blocks per requestor +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14031.582241 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14031.582241 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14286.231634 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14286.231634 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208539.215378 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208539.215378 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110020.539760 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110020.539760 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1105141 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.449200 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 117971876 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1105653 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 106.698825 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 14058125000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.449200 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998924 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998924 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 218060624 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 218060624 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 107376961 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 107376961 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 107376961 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 107376961 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 107376961 # number of overall hits -system.cpu0.icache.overall_hits::total 107376961 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1102234 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1102234 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1102234 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1102234 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1102234 # number of overall misses -system.cpu0.icache.overall_misses::total 1102234 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10984481500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10984481500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10984481500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10984481500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10984481500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10984481500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 108479195 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 108479195 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 108479195 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 108479195 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 108479195 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 108479195 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010161 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.010161 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010161 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.010161 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010161 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.010161 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9965.652938 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9965.652938 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9965.652938 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9965.652938 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9965.652938 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9965.652938 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 239260738 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 239260738 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 117971876 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 117971876 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 117971876 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 117971876 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 117971876 # number of overall hits +system.cpu0.icache.overall_hits::total 117971876 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1105662 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1105662 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1105662 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1105662 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1105662 # number of overall misses +system.cpu0.icache.overall_misses::total 1105662 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11445416000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11445416000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11445416000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11445416000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11445416000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11445416000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 119077538 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 119077538 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 119077538 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 119077538 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 119077538 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 119077538 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009285 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.009285 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009285 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.009285 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009285 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.009285 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10351.640917 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10351.640917 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10351.640917 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10351.640917 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10351.640917 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10351.640917 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1101713 # number of writebacks -system.cpu0.icache.writebacks::total 1101713 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1102234 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1102234 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1102234 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1102234 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1102234 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1102234 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1105141 # number of writebacks +system.cpu0.icache.writebacks::total 1105141 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1105662 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1105662 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1105662 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1105662 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1105662 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1105662 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10433364500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10433364500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10433364500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10433364500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10433364500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10433364500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10892585000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10892585000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10892585000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10892585000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10892585000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10892585000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 811416500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 811416500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 811416500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 811416500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010161 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010161 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010161 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010161 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010161 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010161 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9465.652938 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9465.652938 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9465.652938 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9465.652938 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9465.652938 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9465.652938 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009285 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009285 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009285 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009285 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009285 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009285 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9851.640917 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9851.640917 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9851.640917 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9851.640917 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9851.640917 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9851.640917 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89937.541565 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89937.541565 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1850136 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1850170 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 29 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1836809 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1836835 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 22 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 236334 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 266149 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16069.328191 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2918942 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 282232 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 10.342350 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 235109 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 260353 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15640.705301 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1686155 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 275976 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.109789 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14514.612326 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.486543 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.157051 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1554.072270 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.885902 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000010 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.094853 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.980794 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1018 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15059 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 235 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 358 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 412 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 14471.492082 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.272651 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.132938 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1167.807630 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.883270 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000078 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.071277 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.954633 # 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number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2417355500 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4735500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2469500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2576180000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4089460000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 6672845000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4735500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2469500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2576180000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4089460000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13869294782 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 20542139782 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 743751500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4509867000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5253618500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6373927500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7117679000 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 743751500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4509867000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 5253618500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021722 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031270 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.024763 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6373927500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7117679000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.025468 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031119 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027201 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.162053 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.162053 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040563 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040563 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.197406 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.197406 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021722 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031270 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040563 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.184646 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.098120 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021722 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031270 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040563 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.184646 # mshr miss rate for overall accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.154909 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154909 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056407 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056407 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.211578 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.211578 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.025468 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031119 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056407 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191195 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110166 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.025468 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031119 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056407 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191195 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.237049 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18306.451613 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17883.561644 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 18136.363636 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51878.335607 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 51878.335607 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19224.479326 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19224.479326 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15414.434186 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15414.434186 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38444.841898 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38444.841898 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47350.469694 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47350.469694 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23634.157232 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23634.157232 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18306.451613 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17883.561644 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47350.469694 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28325.670415 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32959.895813 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18306.451613 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17883.561644 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47350.469694 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28325.670415 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51878.335607 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44047.596901 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.249260 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18143.678161 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17514.184397 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 17922.885572 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53346.929538 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53346.929538 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17108.334694 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17108.334694 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15005.995510 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15005.995510 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 216874.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 216874.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40084.971472 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40084.971472 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 41306.780830 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 41306.780830 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23832.746722 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23832.746722 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18143.678161 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17514.184397 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 41306.780830 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28568.853742 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32406.137544 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18143.678161 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17514.184397 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 41306.780830 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28568.853742 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53346.929538 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44091.685230 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 213677.011276 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174376.609798 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200526.253697 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174418.716918 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 110573.897906 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 105477.403228 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 3727432 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1879617 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 314429 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 310730 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3699 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 50409 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1677085 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19680 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19680 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 702838 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1316929 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 184068 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 307004 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 88013 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42167 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112831 # Transaction distribution +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105793.083703 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 102751.209020 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 3740310 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1886004 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27868 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 209163 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 207471 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1692 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 61471 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1694410 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28463 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28463 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 706729 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1319793 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 79890 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 307615 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 87684 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41751 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 111919 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 90 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 288284 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284624 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1102234 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 554693 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3303 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3324225 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2514874 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11068 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 23857 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5874024 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141088696 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96080240 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18676 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 39960 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 237227572 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 980964 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 18662568 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 2867653 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.124927 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.334515 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 288494 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284839 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1105662 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 565382 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3277 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3334509 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2561453 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10930 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24498 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5931390 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141527480 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96553100 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18124 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 40992 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 238139696 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 885320 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 18675332 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 2797680 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.089870 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.288103 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2513105 87.64% 87.64% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 350849 12.23% 99.87% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 3699 0.13% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2547944 91.07% 91.07% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 248044 8.87% 99.94% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1692 0.06% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2867653 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 3694518500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2797680 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 3721587498 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 114067456 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 113922479 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1662373000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1667515000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1187117482 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1206437474 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 13871990 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 14255489 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1328,68 +1340,62 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 3295 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 3295 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 621 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2674 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 3295 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 3295 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 3295 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2525 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11832.673267 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11118.852324 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 4722.323425 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-4095 1 0.04% 0.04% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-8191 600 23.76% 23.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1197 47.41% 71.21% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-16383 525 20.79% 92.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-20479 78 3.09% 95.09% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::20480-24575 55 2.18% 97.27% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-28671 34 1.35% 98.61% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::28672-32767 21 0.83% 99.45% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-36863 5 0.20% 99.64% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::36864-40959 3 0.12% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-45055 3 0.12% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::45056-49151 1 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-53247 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-61439 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2525 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -2078115828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -2078115828 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -2078115828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1912 75.72% 75.72% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 613 24.28% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2525 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3295 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 3379 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3379 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 683 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2696 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 3379 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3379 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3379 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2609 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12498.275201 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11540.409783 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5547.212388 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 616 23.61% 23.61% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1660 63.63% 87.24% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 255 9.77% 97.01% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 67 2.57% 99.58% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 5 0.19% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.11% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.08% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2609 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -2073200828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -2073200828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -2073200828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1934 74.13% 74.13% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 675 25.87% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2609 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3379 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3295 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2525 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3379 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2609 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2525 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 5820 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2609 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5988 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6294037 # DTB read hits -system.cpu1.dtb.read_misses 2780 # DTB read misses -system.cpu1.dtb.write_hits 4620410 # DTB write hits -system.cpu1.dtb.write_misses 515 # DTB write misses +system.cpu1.dtb.read_hits 3943912 # DTB read hits +system.cpu1.dtb.read_misses 2863 # DTB read misses +system.cpu1.dtb.write_hits 3421052 # DTB write hits +system.cpu1.dtb.write_misses 516 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1950 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1981 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 345 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 312 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6296817 # DTB read accesses -system.cpu1.dtb.write_accesses 4620925 # DTB write accesses +system.cpu1.dtb.read_accesses 3946775 # DTB read accesses +system.cpu1.dtb.write_accesses 3421568 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 10914447 # DTB hits -system.cpu1.dtb.misses 3295 # DTB misses -system.cpu1.dtb.accesses 10917742 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 7364964 # DTB hits +system.cpu1.dtb.misses 3379 # DTB misses +system.cpu1.dtb.accesses 7368343 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1419,7 +1425,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 1746 # Table walker walks requested system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate @@ -1428,25 +1434,24 @@ system.cpu1.itb.walker.walkWaitTime::samples 1746 system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12387.082204 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11535.325922 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5801.640137 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 173 15.63% 15.63% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 662 59.80% 75.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 167 15.09% 90.51% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 48 4.34% 94.85% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.18% 95.03% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 22 1.99% 97.02% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 9 0.81% 97.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.18% 98.01% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 17 1.54% 99.55% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 13079.042457 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 12148.751119 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5740.258970 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 165 14.91% 14.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 593 53.57% 68.47% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 181 16.35% 84.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 52 4.70% 89.52% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 63 5.69% 95.21% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 26 2.35% 97.56% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 1.54% 99.10% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 99.37% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 4 0.36% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.18% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -2078939828 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -2078939828 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -2078939828 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::samples -2073744828 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -2073744828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -2073744828 # Table walker pending requests distribution system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated @@ -1457,7 +1462,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 27022574 # ITB inst hits +system.cpu1.itb.inst_hits 16566340 # ITB inst hits system.cpu1.itb.inst_misses 1746 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1474,658 +1479,656 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 27024320 # ITB inst accesses -system.cpu1.itb.hits 27022574 # DTB hits +system.cpu1.itb.inst_accesses 16568086 # ITB inst accesses +system.cpu1.itb.hits 16566340 # DTB hits system.cpu1.itb.misses 1746 # DTB misses -system.cpu1.itb.accesses 27024320 # DTB accesses -system.cpu1.numPwrStateTransitions 5545 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2773 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1021169708.427335 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25639051633.019150 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1969 71.01% 71.01% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 798 28.78% 99.78% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.itb.accesses 16568086 # DTB accesses +system.cpu1.numPwrStateTransitions 5497 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2749 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1034540641.602037 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25769735768.471432 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1960 71.30% 71.30% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 783 28.48% 99.78% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 929980591792 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2773 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 38093227531 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2831703601469 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 5738665817 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 929980464320 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2749 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 26048486236 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2843952223764 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 5739069639 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2773 # number of quiesce instructions executed -system.cpu1.committedInsts 26084833 # Number of instructions committed -system.cpu1.committedOps 31969643 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 28891717 # Number of integer alu accesses +system.cpu1.kern.inst.quiesce 2749 # number of quiesce instructions executed +system.cpu1.committedInsts 16210815 # Number of instructions committed +system.cpu1.committedOps 19752329 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 17813732 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses -system.cpu1.num_func_calls 3291352 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2940246 # number of instructions that are conditional controls -system.cpu1.num_int_insts 28891717 # number of integer instructions +system.cpu1.num_func_calls 1029438 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1815045 # number of instructions that are conditional controls +system.cpu1.num_int_insts 17813732 # number of integer instructions system.cpu1.num_fp_insts 1857 # number of float instructions -system.cpu1.num_int_register_reads 54405566 # number of times the integer registers were read -system.cpu1.num_int_register_writes 20702345 # number of times the integer registers were written +system.cpu1.num_int_register_reads 32326512 # number of times the integer registers were read +system.cpu1.num_int_register_writes 12493939 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 117659728 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 9804030 # number of times the CC registers were written -system.cpu1.num_mem_refs 11150743 # number of memory refs -system.cpu1.num_load_insts 6405542 # Number of load instructions -system.cpu1.num_store_insts 4745201 # Number of store instructions -system.cpu1.num_idle_cycles 5662491677.952167 # Number of idle cycles -system.cpu1.num_busy_cycles 76174139.047833 # Number of busy cycles -system.cpu1.not_idle_fraction 0.013274 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.986726 # Percentage of idle cycles -system.cpu1.Branches 6334050 # Number of branches fetched +system.cpu1.num_cc_register_reads 72207765 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 6423893 # number of times the CC registers were written +system.cpu1.num_mem_refs 7598514 # number of memory refs +system.cpu1.num_load_insts 4055507 # Number of load instructions +system.cpu1.num_store_insts 3543007 # Number of store instructions +system.cpu1.num_idle_cycles 5686981123.489185 # Number of idle cycles +system.cpu1.num_busy_cycles 52088515.510815 # Number of busy cycles +system.cpu1.not_idle_fraction 0.009076 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.990924 # Percentage of idle cycles +system.cpu1.Branches 2922923 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 21707276 65.97% 65.97% # Class of executed instruction -system.cpu1.op_class::IntMult 42869 0.13% 66.10% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3317 0.01% 66.11% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 66.11% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 66.11% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 66.11% # Class of executed instruction -system.cpu1.op_class::MemRead 6405542 19.47% 85.58% # Class of executed instruction -system.cpu1.op_class::MemWrite 4745201 14.42% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 12474914 62.05% 62.05% # Class of executed instruction +system.cpu1.op_class::IntMult 26468 0.13% 62.19% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3329 0.02% 62.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.20% # Class of executed instruction +system.cpu1.op_class::MemRead 4055507 20.17% 82.38% # Class of executed instruction +system.cpu1.op_class::MemWrite 3543007 17.62% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 32904271 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 184968 # number of replacements -system.cpu1.dcache.tags.tagsinuse 463.748200 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 10628914 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 185317 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 57.355310 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 117456056000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 463.748200 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.905758 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.905758 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 279 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 70 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.681641 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 22007267 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 22007267 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 5972632 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 5972632 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4424329 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4424329 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48799 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 48799 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78725 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78725 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70549 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70549 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 10396961 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 10396961 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 10445760 # number of overall hits -system.cpu1.dcache.overall_hits::total 10445760 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 132851 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 132851 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 90720 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 90720 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30243 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30243 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17042 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17042 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23391 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23391 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 223571 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 223571 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 253814 # number of overall misses -system.cpu1.dcache.overall_misses::total 253814 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1953731000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1953731000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2328640500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2328640500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317134000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 317134000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 572176500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 572176500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2893000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2893000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4282371500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4282371500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4282371500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4282371500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 6105483 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 6105483 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4515049 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4515049 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79042 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79042 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95767 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 95767 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93940 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 93940 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 10620532 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 10620532 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 10699574 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 10699574 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.021759 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.021759 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.020093 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.020093 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382619 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382619 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177953 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177953 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248999 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248999 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.021051 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.021051 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.023722 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.023722 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14706.182114 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14706.182114 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25668.435847 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25668.435847 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18608.966084 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18608.966084 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24461.395408 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24461.395408 # average StoreCondReq miss latency +system.cpu1.op_class::total 20103291 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 186972 # number of replacements +system.cpu1.dcache.tags.tagsinuse 469.131643 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 7097155 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 187306 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 37.890698 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 127531940000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.131643 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916273 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.916273 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 334 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 255 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 79 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.652344 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 14948788 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14948788 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 3631994 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3631994 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3232351 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3232351 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48894 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 48894 # 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number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2373794500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317489000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 317489000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544203500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 544203500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1998500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1998500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4395161500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4395161500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4395161500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4395161500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3765671 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3765671 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3324299 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3324299 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79237 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79237 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95932 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 95932 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94101 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94101 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 7089970 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 7089970 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 7169207 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7169207 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035499 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035499 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027659 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027659 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382940 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382940 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.176927 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.176927 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246639 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246639 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031823 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031823 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035704 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035704 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15121.277407 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15121.277407 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25816.706182 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 25816.706182 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18705.532316 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18705.532316 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23447.951226 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23447.951226 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19154.414034 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19154.414034 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16872.085464 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16872.085464 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19479.940166 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19479.940166 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17170.745953 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17170.745953 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 184968 # number of writebacks -system.cpu1.dcache.writebacks::total 184968 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 261 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 261 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11955 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11955 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 261 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 261 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 261 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 261 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 132590 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 132590 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90720 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 90720 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29532 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29532 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5087 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5087 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23391 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23391 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 223310 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 223310 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 252842 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 252842 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 13772 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 13772 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11224 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11224 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 24996 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 24996 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1815324500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1815324500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2237920500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2237920500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 484982000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 484982000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 85050000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 85050000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 548834500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 548834500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2844000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2844000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4053245000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4053245000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4538227000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4538227000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2392670000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2392670000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2392670000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2392670000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.021717 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.021717 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.020093 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.020093 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.373624 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.373624 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053119 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053119 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248999 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248999 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.021026 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.021026 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.023631 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.023631 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13691.262539 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13691.262539 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24668.435847 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24668.435847 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16422.253826 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16422.253826 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16719.087871 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16719.087871 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23463.490231 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23463.490231 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 186972 # number of writebacks +system.cpu1.dcache.writebacks::total 186972 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 283 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 283 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12048 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12048 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 283 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 283 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 283 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 283 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133394 # 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number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2281846500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 500338500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 500338500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 85063000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 85063000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521039500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521039500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1953500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1953500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4163335000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4163335000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4663673500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4663673500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443787500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443787500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443787500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443787500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035424 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035424 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027659 # 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average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22449.890129 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18150.754556 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18150.754556 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17948.865299 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17948.865299 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173734.388615 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173734.388615 # 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Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 54549724 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 54549724 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 26517983 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 26517983 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 26517983 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 26517983 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 26517983 # 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number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4509196500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 27022569 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 27022569 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 27022569 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 27022569 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 27022569 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 27022569 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018673 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.018673 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018673 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.018673 # 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Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 16060167 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 16060167 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 16060167 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 16060167 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 16060167 # number of overall hits +system.cpu1.icache.overall_hits::total 16060167 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 506168 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 506168 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 506168 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 506168 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 506168 # number of overall misses +system.cpu1.icache.overall_misses::total 506168 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4710776500 # 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average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9306.744994 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 504074 # number of writebacks -system.cpu1.icache.writebacks::total 504074 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 504586 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 504586 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 504586 # 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number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4256903500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4256903500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4256903500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4256903500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4256903500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4256903500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15776500 # 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average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8436.428082 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8436.428082 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8436.428082 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8436.428082 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8436.428082 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89132.768362 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89132.768362 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 194200 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 194208 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4457692500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4457692500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4457692500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4457692500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4457692500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4457692500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15627500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15627500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15627500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 15627500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030554 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030554 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030554 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.030554 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030554 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.030554 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8806.744994 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8806.744994 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8806.744994 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8806.744994 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8806.744994 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8806.744994 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88290.960452 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 88290.960452 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88290.960452 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 88290.960452 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 198543 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 198543 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 58064 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 39025 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14524.719643 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1158959 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 53669 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 21.594570 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 58537 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 43670 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14604.323800 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 603874 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 58010 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 10.409826 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14059.725770 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 5.138677 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.073426 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 457.781770 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.858138 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000314 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.027941 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.886519 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1036 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13588 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 48 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 987 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14211.070638 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.100990 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.057181 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 388.094990 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.867375 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000189 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000126 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.023687 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.891377 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 327 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14000 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 23 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 304 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1629 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11648 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.063232 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001221 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.829346 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 23678541 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 23678541 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3677 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1997 # 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number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1997 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 491676 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 127209 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 624559 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3677 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1997 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 491676 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 127209 # number of overall hits -system.cpu1.l2cache.overall_hits::total 624559 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 321 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 267 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 588 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29273 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29273 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23388 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23388 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34332 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 34332 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 12910 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 12910 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 67115 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 67115 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 321 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 267 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 12910 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 101447 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 114945 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 321 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 267 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 12910 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 101447 # number of overall misses -system.cpu1.l2cache.overall_misses::total 114945 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6521000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5470500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 11991500 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 64762500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 64762500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 33901000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 33901000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2768998 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2768998 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1261050000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1261050000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 523740500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 523740500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1479063500 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1479063500 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6521000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5470500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 523740500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2740113500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3275845500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6521000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5470500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 523740500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 2740113500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3275845500 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3998 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2264 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 6262 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 113054 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 113054 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 564912 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 564912 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29273 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29273 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23388 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23388 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61447 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 61447 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 504586 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 504586 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 167209 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 167209 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3998 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2264 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 504586 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 228656 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 739504 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3998 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2264 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 504586 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 228656 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 739504 # 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mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454667 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186897 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14314.641745 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14488.764045 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14393.707483 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31391.319481 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31391.319481 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16609.144946 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16609.144946 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15966.841970 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15966.841970 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 824999.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 824999.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30540.488075 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30540.488075 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34568.590240 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34568.590240 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16037.748640 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16037.748640 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14314.641745 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14488.764045 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34568.590240 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 20938.710887 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22437.041873 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14314.641745 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14488.764045 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34568.590240 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 20938.710887 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31391.319481 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23949.235502 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81632.768362 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165709.083648 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164642.232418 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81632.768362 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91300.428068 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91232.451436 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 1481374 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 748184 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11076 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 177406 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 174791 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2615 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 23242 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 733434 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11224 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11224 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 142093 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 575988 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 98729 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 27772 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 72921 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41250 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85602 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 90 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 69150 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 66171 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 504586 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 246891 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 241 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1513600 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 873749 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5588 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9967 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2402904 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64554948 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29333690 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9056 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 15992 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 93913686 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 383897 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 4632988 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1125089 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.175565 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.386511 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.205250 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14476.190476 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14110.294118 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14316.901408 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31612.145031 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31612.145031 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15295.007590 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15295.007590 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14951.027707 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14951.027707 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 807750 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 807750 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32081.102476 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32081.102476 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30344.305341 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30344.305341 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16498.234529 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16498.234529 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14476.190476 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14110.294118 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30344.305341 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21669.056193 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23082.885782 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14476.190476 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14110.294118 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30344.305341 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21669.056193 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31612.145031 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24519.847717 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 80790.960452 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135091.642465 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132157.814408 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 80790.960452 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75445.846098 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75611.072302 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 1488311 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 751924 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11152 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 112911 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104591 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8320 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 12675 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 724258 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2450 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2450 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 148574 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 578366 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 28228 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 30717 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 71065 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40939 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85439 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 36 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 69452 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66978 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 506168 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 262948 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1518346 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 839098 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5647 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10280 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2373371 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64757444 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29422876 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9292 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16820 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 94206432 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 332481 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 4905948 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1059226 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.131024 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.359953 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 930178 82.68% 82.68% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 192296 17.09% 99.77% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 2615 0.23% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 928762 87.68% 87.68% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 122144 11.53% 99.21% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 8320 0.79% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1125089 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1449361998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1059226 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1442372000 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 81273182 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79594348 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 757056000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 759429000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 388749000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 376190500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 5969499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 6075998 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 31015 # Transaction distribution system.iobus.trans_dist::ReadResp 31015 # Transaction distribution -system.iobus.trans_dist::WriteReq 59421 # Transaction distribution -system.iobus.trans_dist::WriteResp 59421 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 59422 # Transaction distribution +system.iobus.trans_dist::WriteResp 59422 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -2269,11 +2272,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180872 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -2292,33 +2295,33 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484066 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48725500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48721500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 106000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 323500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 321000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 94500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 94000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 599000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 622500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 23000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 48000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) @@ -2330,32 +2333,32 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6153000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6160000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 32045500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 32045000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187736829 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187728827 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36445 # number of replacements -system.iocache.tags.tagsinuse 14.386581 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.386151 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 289188615000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.386581 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.899161 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.899161 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 289285136000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.386151 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.899134 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.899134 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328311 # Number of tag accesses system.iocache.tags.data_accesses 328311 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -2364,14 +2367,14 @@ system.iocache.demand_misses::realview.ide 36479 # system.iocache.demand_misses::total 36479 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36479 # number of overall misses system.iocache.overall_misses::total 36479 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 35445377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 35445377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4303608452 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4303608452 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4339053829 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4339053829 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4339053829 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4339053829 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 34821377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 34821377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4306604450 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4306604450 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4341425827 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4341425827 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4341425827 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4341425827 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2388,19 +2391,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 139001.478431 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 139001.478431 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118805.445340 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118805.445340 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118946.622139 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118946.622139 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118946.622139 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118946.622139 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 136554.419608 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 136554.419608 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118888.152882 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118888.152882 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 119011.645796 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119011.645796 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 119011.645796 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119011.645796 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 3.750000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks @@ -2412,14 +2415,14 @@ system.iocache.demand_mshr_misses::realview.ide 36479 system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 22695377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 22695377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2490051224 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2490051224 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2512746601 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2512746601 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2512746601 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2512746601 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 22071377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 22071377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2493082245 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2493082245 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2515153622 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2515153622 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2515153622 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2515153622 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2428,566 +2431,591 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 89001.478431 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 89001.478431 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68740.371687 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68740.371687 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68882.003372 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68882.003372 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68882.003372 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68882.003372 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 119266 # number of replacements -system.l2c.tags.tagsinuse 63150.928665 # Cycle average of tags in use -system.l2c.tags.total_refs 419498 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 183131 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.290699 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13441.811145 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.006326 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.055729 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7581.242495 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2905.326286 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35913.296254 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1514.615308 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 303.672578 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1486.902543 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.205106 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 86554.419608 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 86554.419608 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68824.046074 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68824.046074 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68947.987116 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68947.987116 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68947.987116 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68947.987116 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 137913 # number of replacements +system.l2c.tags.tagsinuse 65077.078827 # Cycle average of tags in use +system.l2c.tags.total_refs 526584 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 203352 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.589520 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 102405123000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 6467.156176 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.052663 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.040623 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7119.410088 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6998.473757 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37485.432069 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.004586 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1431.375532 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3211.021288 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2361.112045 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.098681 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000047 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.115681 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.044332 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.547993 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.023111 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.004634 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022688 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.963607 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 30886 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 32974 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 76 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4718 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 26088 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2232 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 30425 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.471283 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.503143 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5778594 # Number of tag accesses -system.l2c.tags.data_accesses 5778594 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 255647 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 255647 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 32152 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2169 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 34321 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2017 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 1011 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3028 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4187 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1790 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5977 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 77 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 85 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 27265 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 45372 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46765 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 37 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 32 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 10614 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 8420 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 4646 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 143313 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 77 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 85 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 27265 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 49559 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 46765 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 37 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 32 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 10614 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 10210 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 4646 # number of demand (read+write) hits -system.l2c.demand_hits::total 149290 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 77 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 85 # number of overall hits -system.l2c.overall_hits::cpu0.inst 27265 # number of overall hits -system.l2c.overall_hits::cpu0.data 49559 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 46765 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 37 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 32 # number of overall hits -system.l2c.overall_hits::cpu1.inst 10614 # number of overall hits -system.l2c.overall_hits::cpu1.data 10210 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 4646 # number of overall hits -system.l2c.overall_hits::total 149290 # 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mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.022989 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.390002 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.161377 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736039 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.177227 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078573 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.544108 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.535337 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.083333 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.022989 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.390002 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.283829 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736039 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.177227 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.439165 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.544108 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.551124 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.083333 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.022989 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.390002 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.283829 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736039 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.177227 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.439165 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.544108 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.551124 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23927.681504 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22790.310918 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23656.360500 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25802.491103 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24847.777778 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25128.399582 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85882.080660 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71280.816270 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 80039.808655 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 76500 # average ReadSharedReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.010828 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.049230 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.015284 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.054010 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.034305 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.044463 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.742352 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.853589 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.784375 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.060870 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.287171 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.146510 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748583 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.025641 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.109767 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078495 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.534456 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.489672 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.060870 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.287171 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.266723 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748583 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.025641 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.109767 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.419289 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.534456 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.509449 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.060870 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.287171 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.266723 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748583 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.025641 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.109767 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.419289 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.534456 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.509449 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 24301.822323 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22748.091603 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23721.112696 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26018.656716 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23475 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25067.757009 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 86044.396552 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72286.305384 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 80388.338968 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 77642.857143 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71668.291736 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77822.242584 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86486.964456 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72403.846154 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79518.105850 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102576.115419 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 84778.329155 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76500 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72362.730318 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78107.087657 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87168.014344 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73701.623238 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79024.236038 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102198.759897 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85450.721597 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77642.857143 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71668.291736 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82299.246474 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86486.964456 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72403.846154 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72020.575360 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102576.115419 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 84308.214858 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72362.730318 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82564.091393 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87168.014344 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73701.623238 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72993.091743 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102198.759897 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 84927.650416 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77642.857143 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71668.291736 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82299.246474 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86486.964456 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72403.846154 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72020.575360 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102576.115419 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 84308.214858 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72362.730318 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82564.091393 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87168.014344 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73701.623238 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72993.091743 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102198.759897 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 84927.650416 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 195676.347958 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 147741.048733 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 153306.019422 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182525.781822 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62788.135593 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117205.910853 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 153288.321522 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101258.887854 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81392.649942 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 90117.227720 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 502889 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 289010 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96296.444771 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62788.135593 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65429.047962 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 90101.908166 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 504508 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 283356 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 44074 # Transaction distribution -system.membus.trans_dist::ReadResp 209458 # Transaction distribution -system.membus.trans_dist::WriteReq 30904 # Transaction distribution -system.membus.trans_dist::WriteResp 30904 # Transaction distribution -system.membus.trans_dist::WritebackDirty 130397 # Transaction distribution -system.membus.trans_dist::CleanEvict 14501 # Transaction distribution -system.membus.trans_dist::UpgradeReq 77693 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40094 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 44081 # Transaction distribution +system.membus.trans_dist::ReadResp 215279 # Transaction distribution +system.membus.trans_dist::WriteReq 30913 # Transaction distribution +system.membus.trans_dist::WriteResp 30913 # Transaction distribution +system.membus.trans_dist::WritebackDirty 137329 # Transaction distribution +system.membus.trans_dist::CleanEvict 16651 # Transaction distribution +system.membus.trans_dist::UpgradeReq 64792 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38133 # Transaction distribution system.membus.trans_dist::UpgradeResp 16 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 38557 # Transaction distribution -system.membus.trans_dist::ReadExResp 18075 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 165384 # Transaction distribution +system.membus.trans_dist::ReadExReq 40131 # Transaction distribution +system.membus.trans_dist::ReadExResp 19681 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 171198 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13706 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 641086 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 762740 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13736 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 650114 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 771800 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 835679 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 844739 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27412 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17788748 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17979022 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18707276 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18897612 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20296142 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 125256 # Total snoops (count) +system.membus.pkt_size::total 21214732 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123049 # Total snoops (count) system.membus.snoopTraffic 37632 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 432932 # Request fanout histogram -system.membus.snoop_fanout::mean 0.012007 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.108915 # Request fanout histogram +system.membus.snoop_fanout::samples 425474 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012172 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.109655 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 427734 98.80% 98.80% # Request fanout histogram -system.membus.snoop_fanout::1 5198 1.20% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 420295 98.78% 98.78% # Request fanout histogram +system.membus.snoop_fanout::1 5179 1.22% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 432932 # Request fanout histogram -system.membus.reqLayer0.occupancy 88248500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 425474 # Request fanout histogram +system.membus.reqLayer0.occupancy 88273000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11302499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11470000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 949242954 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 976922430 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1079420372 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1118158241 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1341881 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1366131 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3019,77 +3047,77 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 971913 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 526665 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 151758 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 18562 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 17727 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 835 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 44077 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 473751 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30904 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30904 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 349854 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 105962 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 111902 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 43122 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 155024 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 90 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 90 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50816 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50816 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 429676 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4592 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1183270 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 322305 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1505575 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 33366812 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4544754 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 37911566 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 376245 # Total snoops (count) -system.toL2Bus.snoopTraffic 15498572 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 834461 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.383881 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.488383 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1015113 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 540228 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 174806 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 29447 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 28379 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1068 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 44084 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 511780 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 361959 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 119582 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 109939 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 42732 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 152671 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 79 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51282 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51282 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 467698 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4573 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1273273 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 316945 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1590218 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35272632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5631700 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 40904332 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 389588 # Total snoops (count) +system.toL2Bus.snoopTraffic 15743116 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 889230 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.395392 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.491385 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 514962 61.71% 61.71% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 318664 38.19% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 835 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 538704 60.58% 60.58% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 349458 39.30% 99.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1068 0.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 834461 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 867249813 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 889230 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 894701567 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 360619 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 626009420 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 677372101 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 234312270 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 239236747 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |