diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt | 4642 |
1 files changed, 2378 insertions, 2264 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index ede2b82db..391769400 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,164 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.867049 # Number of seconds simulated -sim_ticks 2867048515500 # Number of ticks simulated -final_tick 2867048515500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.868319 # Number of seconds simulated +sim_ticks 2868318696500 # Number of ticks simulated +final_tick 2868318696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 753572 # Simulator instruction rate (inst/s) -host_op_rate 911512 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16376301643 # Simulator tick rate (ticks/s) -host_mem_usage 607016 # Number of bytes of host memory used -host_seconds 175.07 # Real time elapsed on the host -sim_insts 131930165 # Number of instructions simulated -sim_ops 159581077 # Number of ops (including micro ops) simulated +host_inst_rate 534652 # Simulator instruction rate (inst/s) +host_op_rate 646675 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11631340017 # Simulator tick rate (ticks/s) +host_mem_usage 586476 # Number of bytes of host memory used +host_seconds 246.60 # Real time elapsed on the host +sim_insts 131846562 # Number of instructions simulated +sim_ops 159471778 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 233060 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 810048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 9243456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 53844 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 455584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 1704320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1173796 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1283584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8628800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 156308 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 605472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 378048 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12502168 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 233060 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 53844 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 286904 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8696768 # Number of bytes written to this memory +system.physmem.bytes_read::total 12227608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1173796 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 156308 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1330104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8654400 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8714512 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12095 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 13183 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 144429 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 996 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 7142 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 26630 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8672144 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26794 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20582 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134825 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2597 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9484 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5907 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 204504 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 135887 # Number of write requests responded to by this memory +system.physmem.num_reads::total 200214 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 135225 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 140323 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 81289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 282537 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3224032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 89 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 18780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 158903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 594451 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 139661 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 409228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 447504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3008313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54495 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 211090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 131801 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4360641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 81289 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 18780 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 100069 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3033352 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6175 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4262988 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 409228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54495 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 463723 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3017238 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6172 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3039541 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3033352 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 81289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 288712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3224032 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 89 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 18780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 158917 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 594451 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3023424 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3017238 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 409228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 453676 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3008313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 211103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 131801 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7400182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 204505 # Number of read requests accepted -system.physmem.writeReqs 176547 # Number of write requests accepted -system.physmem.readBursts 204505 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 176547 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 13079232 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9088 # Total number of bytes read from write queue -system.physmem.bytesWritten 10932800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12502232 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11032848 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 142 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5691 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 15171 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12666 # Per bank write bursts -system.physmem.perBankRdBursts::1 12263 # Per bank write bursts -system.physmem.perBankRdBursts::2 12897 # Per bank write bursts -system.physmem.perBankRdBursts::3 12449 # Per bank write bursts -system.physmem.perBankRdBursts::4 21010 # Per bank write bursts -system.physmem.perBankRdBursts::5 12626 # Per bank write bursts -system.physmem.perBankRdBursts::6 12991 # Per bank write bursts -system.physmem.perBankRdBursts::7 13024 # Per bank write bursts -system.physmem.perBankRdBursts::8 12039 # Per bank write bursts -system.physmem.perBankRdBursts::9 12109 # Per bank write bursts -system.physmem.perBankRdBursts::10 12276 # Per bank write bursts -system.physmem.perBankRdBursts::11 10996 # Per bank write bursts -system.physmem.perBankRdBursts::12 11725 # Per bank write bursts -system.physmem.perBankRdBursts::13 12231 # Per bank write bursts -system.physmem.perBankRdBursts::14 11672 # Per bank write bursts -system.physmem.perBankRdBursts::15 11389 # Per bank write bursts -system.physmem.perBankWrBursts::0 10702 # Per bank write bursts -system.physmem.perBankWrBursts::1 10814 # Per bank write bursts -system.physmem.perBankWrBursts::2 11122 # Per bank write bursts -system.physmem.perBankWrBursts::3 10684 # Per bank write bursts -system.physmem.perBankWrBursts::4 10817 # Per bank write bursts -system.physmem.perBankWrBursts::5 11014 # Per bank write bursts -system.physmem.perBankWrBursts::6 11094 # Per bank write bursts -system.physmem.perBankWrBursts::7 11085 # Per bank write bursts -system.physmem.perBankWrBursts::8 10650 # Per bank write bursts -system.physmem.perBankWrBursts::9 11040 # Per bank write bursts -system.physmem.perBankWrBursts::10 10845 # Per bank write bursts -system.physmem.perBankWrBursts::11 10150 # Per bank write bursts -system.physmem.perBankWrBursts::12 10760 # Per bank write bursts -system.physmem.perBankWrBursts::13 10359 # Per bank write bursts -system.physmem.perBankWrBursts::14 10115 # Per bank write bursts -system.physmem.perBankWrBursts::15 9574 # Per bank write bursts +system.physmem.bw_total::total 7286412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 200214 # Number of read requests accepted +system.physmem.writeReqs 175885 # Number of write requests accepted +system.physmem.readBursts 200214 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 175885 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12804096 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue +system.physmem.bytesWritten 10892544 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12227608 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10990480 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5671 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 13850 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12188 # Per bank write bursts +system.physmem.perBankRdBursts::1 12046 # Per bank write bursts +system.physmem.perBankRdBursts::2 12591 # Per bank write bursts +system.physmem.perBankRdBursts::3 12330 # Per bank write bursts +system.physmem.perBankRdBursts::4 20750 # Per bank write bursts +system.physmem.perBankRdBursts::5 12582 # Per bank write bursts +system.physmem.perBankRdBursts::6 12043 # Per bank write bursts +system.physmem.perBankRdBursts::7 12246 # Per bank write bursts +system.physmem.perBankRdBursts::8 12442 # Per bank write bursts +system.physmem.perBankRdBursts::9 12402 # Per bank write bursts +system.physmem.perBankRdBursts::10 11722 # Per bank write bursts +system.physmem.perBankRdBursts::11 11146 # Per bank write bursts +system.physmem.perBankRdBursts::12 11467 # Per bank write bursts +system.physmem.perBankRdBursts::13 11916 # Per bank write bursts +system.physmem.perBankRdBursts::14 10852 # Per bank write bursts +system.physmem.perBankRdBursts::15 11341 # Per bank write bursts +system.physmem.perBankWrBursts::0 10835 # Per bank write bursts +system.physmem.perBankWrBursts::1 11264 # Per bank write bursts +system.physmem.perBankWrBursts::2 11493 # Per bank write bursts +system.physmem.perBankWrBursts::3 10899 # Per bank write bursts +system.physmem.perBankWrBursts::4 10487 # Per bank write bursts +system.physmem.perBankWrBursts::5 11152 # Per bank write bursts +system.physmem.perBankWrBursts::6 11024 # Per bank write bursts +system.physmem.perBankWrBursts::7 10595 # Per bank write bursts +system.physmem.perBankWrBursts::8 10782 # Per bank write bursts +system.physmem.perBankWrBursts::9 10958 # Per bank write bursts +system.physmem.perBankWrBursts::10 10716 # Per bank write bursts +system.physmem.perBankWrBursts::11 10408 # Per bank write bursts +system.physmem.perBankWrBursts::12 10444 # Per bank write bursts +system.physmem.perBankWrBursts::13 9906 # Per bank write bursts +system.physmem.perBankWrBursts::14 9416 # Per bank write bursts +system.physmem.perBankWrBursts::15 9817 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2867048141000 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 2868318254500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9742 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 194735 # Read request sizes (log2) +system.physmem.readPktSize::6 190444 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 172111 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 120800 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21636 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9500 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 8185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6994 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 6210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 5370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 23 # What read queue length does an incoming req see +system.physmem.writePktSize::6 171449 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 16077 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4782 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4036 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -188,178 +184,179 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11783 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 11796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 10810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 83215 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 288.553362 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 159.296581 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 336.078048 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 39267 47.19% 47.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16171 19.43% 66.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6480 7.79% 74.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3347 4.02% 78.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3132 3.76% 82.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1913 2.30% 84.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1073 1.29% 85.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1034 1.24% 87.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10798 12.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 83215 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7042 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.019171 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 531.269210 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7040 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 90415 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 262.086778 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 144.561031 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.181928 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46335 51.25% 51.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17813 19.70% 70.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6067 6.71% 77.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3600 3.98% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2534 2.80% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1568 1.73% 86.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1031 1.14% 87.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 985 1.09% 88.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10482 11.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90415 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7120 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.098736 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 516.724228 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7117 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7042 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7042 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.258023 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.337274 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.786425 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5509 78.23% 78.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 384 5.45% 83.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 77 1.09% 84.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 222 3.15% 87.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 122 1.73% 89.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 57 0.81% 90.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 43 0.61% 91.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 37 0.53% 91.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 124 1.76% 93.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 15 0.21% 93.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 18 0.26% 93.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 16 0.23% 94.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 34 0.48% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 16 0.23% 94.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 7 0.10% 94.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 27 0.38% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 62 0.88% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 11 0.16% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 6 0.09% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 10 0.14% 96.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 88 1.25% 97.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 97.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 12 0.17% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 6 0.09% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 19 0.27% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 11 0.16% 98.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 4 0.06% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 36 0.51% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 11 0.16% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.06% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.10% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 5 0.07% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 7 0.10% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.06% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.06% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7042 # Writes before turning the bus around for reads -system.physmem.totQLat 5974898500 # Total ticks spent queuing -system.physmem.totMemAccLat 9806704750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1021815000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29236.69 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7120 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7120 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.903933 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.122109 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.073987 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5764 80.96% 80.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 237 3.33% 84.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 43 0.60% 84.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 234 3.29% 88.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 121 1.70% 89.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 62 0.87% 90.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 31 0.44% 91.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 36 0.51% 91.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 117 1.64% 93.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 18 0.25% 93.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 25 0.35% 93.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 16 0.22% 94.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 40 0.56% 94.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 10 0.14% 94.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 17 0.24% 95.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 28 0.39% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 58 0.81% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 14 0.20% 96.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 7 0.10% 96.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 6 0.08% 96.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 88 1.24% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 12 0.17% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 98.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 15 0.21% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 6 0.08% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 14 0.20% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 9 0.13% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 35 0.49% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 6 0.08% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.06% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 8 0.11% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.03% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.04% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 8 0.11% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.01% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.01% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.06% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 3 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 3 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7120 # Writes before turning the bus around for reads +system.physmem.totQLat 4855930250 # Total ticks spent queuing +system.physmem.totMemAccLat 8607130250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1000320000 # Total ticks spent in databus transfers +system.physmem.avgQLat 24271.88 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47986.69 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.56 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.81 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.36 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 43021.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.46 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.80 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.07 # Data bus utilization in percentage -system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing -system.physmem.readRowHits 174382 # Number of row buffer hits during reads -system.physmem.writeRowHits 117590 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.33 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 68.82 # Row buffer hit rate for writes -system.physmem.avgGap 7524033.84 # Average gap between requests -system.physmem.pageHitRate 77.81 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2731090191250 # Time in different power states -system.physmem.memoryStateTime::REF 95736940000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 40221363750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 330432480 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 298672920 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 180295500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 162966375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 857422800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 736600800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 565911360 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 541034640 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 187261454640 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 187261454640 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 82724898285 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 81530993385 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1647661560750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1648708845750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1919581975815 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1919240568510 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.533155 # Core power per rank (mW) -system.physmem.averagePower::1 669.414075 # Core power per rank (mW) +system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing +system.physmem.readRowHits 167229 # Number of row buffer hits during reads +system.physmem.writeRowHits 112615 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.16 # Row buffer hit rate for writes +system.physmem.avgGap 7626497.96 # Average gap between requests +system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 354707640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 193540875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 832845000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 568613520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 84727272375 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1646666587500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1920687916830 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.622475 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2739235632500 # Time in different power states +system.physmem_0.memoryStateTime::REF 95779320000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 33303656000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 328829760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 179421000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 727646400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 534256560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 83962556955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1647337390500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1920414451095 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.527135 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2740355751000 # Time in different power states +system.physmem_1.memoryStateTime::REF 95779320000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32179536500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -385,6 +382,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -406,27 +411,65 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 7749 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7749 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1459 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6290 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7749 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7749 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7749 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6355 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 8363.375452 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 7097.000757 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5454.838397 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6203 97.61% 97.61% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 142 2.23% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 3 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6355 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 987959000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 987959000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 987959000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 4935 77.66% 77.66% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1420 22.34% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6355 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7749 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7749 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6355 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6355 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 14104 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 22739909 # DTB read hits -system.cpu0.dtb.read_misses 4142 # DTB read misses -system.cpu0.dtb.write_hits 16676295 # DTB write hits -system.cpu0.dtb.write_misses 677 # DTB write misses +system.cpu0.dtb.read_hits 19044092 # DTB read hits +system.cpu0.dtb.read_misses 6608 # DTB read misses +system.cpu0.dtb.write_hits 15688894 # DTB write hits +system.cpu0.dtb.write_misses 1141 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2392 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3442 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1346 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1734 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 187 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 22744051 # DTB read accesses -system.cpu0.dtb.write_accesses 16676972 # DTB write accesses +system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 19050700 # DTB read accesses +system.cpu0.dtb.write_accesses 15690035 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 39416204 # DTB hits -system.cpu0.dtb.misses 4819 # DTB misses -system.cpu0.dtb.accesses 39421023 # DTB accesses +system.cpu0.dtb.hits 34732986 # DTB hits +system.cpu0.dtb.misses 7749 # DTB misses +system.cpu0.dtb.accesses 34740735 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -448,8 +491,40 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 107931670 # ITB inst hits -system.cpu0.itb.inst_misses 2300 # ITB inst misses +system.cpu0.itb.walker.walks 3348 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3348 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 298 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3348 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 8781.732419 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 7396.194245 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5559.104899 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 1469 62.99% 62.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 817 35.03% 98.03% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 4 0.17% 98.20% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 39 1.67% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 987617000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 987617000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 987617000 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2034 87.22% 87.22% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 298 12.78% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3348 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3348 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 91510827 # ITB inst hits +system.cpu0.itb.inst_misses 3348 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -458,178 +533,179 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1397 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2150 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 107933970 # ITB inst accesses -system.cpu0.itb.hits 107931670 # DTB hits -system.cpu0.itb.misses 2300 # DTB misses -system.cpu0.itb.accesses 107933970 # DTB accesses -system.cpu0.numCycles 5733190951 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 91514175 # ITB inst accesses +system.cpu0.itb.hits 91510827 # DTB hits +system.cpu0.itb.misses 3348 # DTB misses +system.cpu0.itb.accesses 91514175 # DTB accesses +system.cpu0.numCycles 5736637393 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 104697045 # Number of instructions committed -system.cpu0.committedOps 126437300 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 112138973 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4560 # Number of float alu accesses -system.cpu0.num_func_calls 12218983 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14112779 # number of instructions that are conditional controls -system.cpu0.num_int_insts 112138973 # number of integer instructions -system.cpu0.num_fp_insts 4560 # number of float instructions -system.cpu0.num_int_register_reads 207168140 # number of times the integer registers were read -system.cpu0.num_int_register_writes 78157614 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3646 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 458862041 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 46623468 # number of times the CC registers were written -system.cpu0.num_mem_refs 40473955 # number of memory refs -system.cpu0.num_load_insts 22968630 # Number of load instructions -system.cpu0.num_store_insts 17505325 # Number of store instructions -system.cpu0.num_idle_cycles 5494072814.437573 # Number of idle cycles -system.cpu0.num_busy_cycles 239118136.562427 # Number of busy cycles -system.cpu0.not_idle_fraction 0.041708 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.958292 # Percentage of idle cycles -system.cpu0.Branches 26957408 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2171 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 89486890 68.80% 68.80% # Class of executed instruction -system.cpu0.op_class::IntMult 99356 0.08% 68.88% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 6997 0.01% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::MemRead 22968630 17.66% 86.54% # Class of executed instruction -system.cpu0.op_class::MemWrite 17505325 13.46% 100.00% # Class of executed instruction +system.cpu0.committedInsts 89363678 # Number of instructions committed +system.cpu0.committedOps 107297883 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 94350928 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses +system.cpu0.num_func_calls 6606472 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 12627044 # number of instructions that are conditional controls +system.cpu0.num_int_insts 94350928 # number of integer instructions +system.cpu0.num_fp_insts 9820 # number of float instructions +system.cpu0.num_int_register_reads 169124164 # number of times the integer registers were read +system.cpu0.num_int_register_writes 64348180 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 385798415 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 43074064 # number of times the CC registers were written +system.cpu0.num_mem_refs 35866705 # number of memory refs +system.cpu0.num_load_insts 19295047 # Number of load instructions +system.cpu0.num_store_insts 16571658 # Number of store instructions +system.cpu0.num_idle_cycles 5512519658.266078 # Number of idle cycles +system.cpu0.num_busy_cycles 224117734.733922 # Number of busy cycles +system.cpu0.not_idle_fraction 0.039068 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.960932 # Percentage of idle cycles +system.cpu0.Branches 19970568 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 73557669 67.15% 67.15% # Class of executed instruction +system.cpu0.op_class::IntMult 108302 0.10% 67.25% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8177 0.01% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::MemRead 19295047 17.61% 84.87% # Class of executed instruction +system.cpu0.op_class::MemWrite 16571658 15.13% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 130069369 # Class of executed instruction +system.cpu0.op_class::total 109543126 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1990 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 555287 # number of replacements -system.cpu0.dcache.tags.tagsinuse 484.900335 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 38705991 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 555652 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 69.658691 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1015660000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.900335 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947071 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.947071 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 302 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 79342035 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 79342035 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 21654746 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 21654746 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 16040843 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 16040843 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 304713 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 304713 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 334336 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 334336 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 329300 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 329300 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 37695589 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 37695589 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 38000302 # number of overall hits -system.cpu0.dcache.overall_hits::total 38000302 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 304912 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 304912 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 263418 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 263418 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 92252 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 92252 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20070 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20070 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20705 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20705 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 568330 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 568330 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 660582 # number of overall misses -system.cpu0.dcache.overall_misses::total 660582 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3916535020 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3916535020 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4029841681 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4029841681 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 322461501 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 322461501 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 462579693 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 462579693 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1480500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1480500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 7946376701 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 7946376701 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 7946376701 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 7946376701 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 21959658 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 21959658 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 16304261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 16304261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 396965 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 396965 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 354406 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 354406 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 350005 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 350005 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 38263919 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 38263919 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 38660884 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 38660884 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013885 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.013885 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016156 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.016156 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.232393 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.232393 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056630 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056630 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.059156 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.059156 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.014853 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.014853 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.017087 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.017087 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12844.804468 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12844.804468 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15298.277570 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15298.277570 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16066.841106 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16066.841106 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22341.448587 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22341.448587 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 1879 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 690539 # number of replacements +system.cpu0.dcache.tags.tagsinuse 487.185772 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 33864824 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 691051 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 49.004812 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1015908000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 487.185772 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.951535 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.951535 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 70103571 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 70103571 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 17785791 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 17785791 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 14958877 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 14958877 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318525 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 318525 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364927 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 364927 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361705 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361705 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 32744668 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 32744668 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 33063193 # number of overall hits +system.cpu0.dcache.overall_hits::total 33063193 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 394905 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 394905 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 324481 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 324481 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127732 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 127732 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21710 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21710 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20007 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20007 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 719386 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 719386 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 847118 # number of overall misses +system.cpu0.dcache.overall_misses::total 847118 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4990872752 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4990872752 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4944330313 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4944330313 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 327573000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 327573000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 444426745 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 444426745 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1572500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1572500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 9935203065 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 9935203065 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 9935203065 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 9935203065 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 18180696 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 18180696 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 15283358 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 15283358 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446257 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446257 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386637 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386637 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381712 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381712 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 33464054 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 33464054 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 33910311 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 33910311 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.021721 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.021721 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.021231 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.021231 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.286230 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.286230 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056151 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056151 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052414 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052414 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.021497 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.021497 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.024981 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.024981 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12638.160449 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12638.160449 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15237.657407 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15237.657407 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15088.576693 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15088.576693 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22213.562503 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22213.562503 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13981.976494 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13981.976494 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12029.356993 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12029.356993 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13810.670579 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13810.670579 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11728.239826 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11728.239826 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -638,82 +714,82 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 420867 # number of writebacks -system.cpu0.dcache.writebacks::total 420867 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7211 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 7211 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14132 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14132 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 7211 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 7211 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 7211 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 7211 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 297701 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 297701 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 263418 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 263418 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 83423 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 83423 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5938 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5938 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20705 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20705 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 561119 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 561119 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 644542 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 644542 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3232031980 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3232031980 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3494328319 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3494328319 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1040331239 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1040331239 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 86260500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 86260500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 420440307 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 420440307 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1400500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1400500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6726360299 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6726360299 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7766691538 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7766691538 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5556589244 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5556589244 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4171949493 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4171949493 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9728538737 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9728538737 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.013557 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.013557 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016156 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016156 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.210152 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.210152 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016755 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016755 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.059156 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.059156 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.014664 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.014664 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.016672 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.016672 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10856.637969 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10856.637969 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13265.336154 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13265.336154 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12470.556549 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12470.556549 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14526.860896 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14526.860896 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20306.221058 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20306.221058 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 504116 # number of writebacks +system.cpu0.dcache.writebacks::total 504116 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25128 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25128 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15248 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15248 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25128 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25128 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25128 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25128 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 369777 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 369777 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324481 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 324481 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100470 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 100470 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6462 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6462 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20007 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20007 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 694258 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 694258 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 794728 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 794728 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3859056498 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3859056498 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4283066685 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4283066685 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1502769500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1502769500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 90797250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90797250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 403751255 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 403751255 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1480500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1480500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8142123183 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 8142123183 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9644892683 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9644892683 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5991645999 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5991645999 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4628507500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4628507500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10620153499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10620153499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.020339 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.020339 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.021231 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021231 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225139 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225139 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016713 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016713 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052414 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052414 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.020746 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.020746 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.023436 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.023436 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10436.172336 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10436.172336 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13199.745702 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13199.745702 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14957.395242 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14957.395242 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14050.951718 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14050.951718 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20180.499575 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20180.499575 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11987.404274 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11987.404274 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12049.938620 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12049.938620 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11727.806065 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11727.806065 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12136.092705 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12136.092705 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -721,58 +797,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 945322 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.483250 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 106985827 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 945834 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 113.112689 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 12806917500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483250 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998991 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998991 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1099798 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.479276 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 90410508 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1100310 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 82.168214 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 13323414750 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.479276 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998983 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998983 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 390 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 113 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::4 9 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 216809183 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 216809183 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 106985827 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 106985827 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 106985827 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 106985827 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 106985827 # number of overall hits -system.cpu0.icache.overall_hits::total 106985827 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 945843 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 945843 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 945843 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 945843 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 945843 # number of overall misses -system.cpu0.icache.overall_misses::total 945843 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8025066767 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 8025066767 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 8025066767 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 8025066767 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 8025066767 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 8025066767 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 107931670 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 107931670 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 107931670 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 107931670 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 107931670 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 107931670 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.008763 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.008763 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.008763 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.008763 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.008763 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.008763 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8484.565374 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8484.565374 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8484.565374 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8484.565374 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8484.565374 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8484.565374 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 184121973 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 184121973 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 90410508 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 90410508 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 90410508 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 90410508 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 90410508 # number of overall hits +system.cpu0.icache.overall_hits::total 90410508 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1100319 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1100319 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1100319 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1100319 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1100319 # number of overall misses +system.cpu0.icache.overall_misses::total 1100319 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10739818993 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10739818993 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10739818993 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10739818993 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10739818993 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10739818993 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 91510827 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 91510827 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 91510827 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 91510827 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 91510827 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 91510827 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012024 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.012024 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012024 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.012024 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012024 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.012024 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9760.641226 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9760.641226 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9760.641226 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9760.641226 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9760.641226 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9760.641226 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -781,356 +857,353 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 945843 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 945843 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 945843 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 945843 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 945843 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 945843 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6605629733 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6605629733 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6605629733 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6605629733 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6605629733 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6605629733 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1100319 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1100319 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1100319 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1100319 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1100319 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1100319 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9082830507 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9082830507 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9082830507 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9082830507 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9082830507 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9082830507 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719096500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719096500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719096500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 719096500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.008763 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.008763 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.008763 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.008763 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.008763 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.008763 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6983.854332 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6983.854332 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6983.854332 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 6983.854332 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6983.854332 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 6983.854332 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012024 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.012024 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.012024 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8254.724773 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8254.724773 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8254.724773 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 8798864 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 212139 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 8184021 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 360 # number of hwpf that were already in the prefetch queue -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 34 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 402310 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 695408 # number of hwpf spanning a virtual page -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 309925 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16107.929627 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1687462 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 325154 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.189732 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1853283 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1853292 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu0.l2cache.prefetcher.pfSpanPage 238164 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 268426 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16093.899190 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1968322 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 284663 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.914569 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6744.420736 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.207457 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.111326 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 773.977995 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1150.108298 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7436.103816 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.411647 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000196 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_blocks::writebacks 7921.036071 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.357121 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.109776 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4473.771805 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1953.197848 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1743.426570 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.483462 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000144 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.047240 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.070197 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.453864 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.983150 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 9588 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 5627 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 66 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 1190 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 8332 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 265 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 1207 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4155 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.585205 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.343445 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 33371196 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 33371196 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 4956 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 2411 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 933239 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 309750 # 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number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1859500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 1877090003 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3394275354 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13906201830 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 19182820937 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 647209500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5743013251 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6390222751 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4419325000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4419325000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 647209500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10162338251 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10809547751 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.199105 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.089632 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.753173 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.753173 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.920761 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.920761 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.483452 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.483452 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.914996 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.914996 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.179712 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.179712 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.065963 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.094630 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.011353 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.187997 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.080680 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.065963 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.094630 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.011353 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.187997 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150199 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150199 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181442 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.098416 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181442 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.337710 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20786.539028 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22948.970488 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41504.638547 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41504.638547 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16022.760491 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16022.760491 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13487.284200 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13487.284200 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 135061.875000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 135061.875000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 25088.846516 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 25088.846516 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22295.614310 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23632.150845 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22295.614310 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41504.638547 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37234.830640 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230973 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 21210.648570 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27355.831422 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56455.149661 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16861.304032 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16861.304032 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13443.888901 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13443.888901 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 139061.875000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 139061.875000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 34119.787657 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 34119.787657 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25069.984593 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28852.904128 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25069.984593 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44694.051386 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1140,58 +1213,66 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1585084 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1436635 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 26190 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26190 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 420867 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 537670 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 82377 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43315 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 100677 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 1737767 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1686227 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 27891 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 27891 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 504114 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 316054 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 89164 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42476 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112407 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 246727 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 235853 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1909730 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1979159 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 7030 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 14021 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 3909940 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 60570040 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 70330266 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10652 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21224 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 130932182 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 972661 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2913864 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.296127 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.456548 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 298764 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 285064 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2218682 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2366147 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10130 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22028 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4616987 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70456504 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84324454 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14928 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 31956 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 154827842 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 648932 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2984532 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.180419 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.384536 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2050990 70.39% 70.39% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 862874 29.61% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 2446067 81.96% 81.96% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 538465 18.04% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2913864 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1492069922 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2984532 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1775358935 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 116074499 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115165999 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1430234267 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 995136418 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1664866493 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 1209535062 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 4367000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 8715750 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 14039749 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1213,27 +1294,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 3332 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3332 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 642 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2690 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 3332 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3332 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3332 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2562 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 8324.355972 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 7260.502547 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 4990.324891 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 2067 80.68% 80.68% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 375 14.64% 95.32% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 62 2.42% 97.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 50 1.95% 99.69% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 4 0.16% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.12% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2562 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1455144968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1455144968 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1455144968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1928 75.25% 75.25% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 634 24.75% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2562 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3332 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3332 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2562 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2562 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5894 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6438534 # DTB read hits -system.cpu1.dtb.read_misses 5066 # DTB read misses -system.cpu1.dtb.write_hits 5578600 # DTB write hits -system.cpu1.dtb.write_misses 983 # DTB write misses +system.cpu1.dtb.read_hits 10115566 # DTB read hits +system.cpu1.dtb.read_misses 2828 # DTB read misses +system.cpu1.dtb.write_hits 6544640 # DTB write hits +system.cpu1.dtb.write_misses 504 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3048 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2029 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 541 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 346 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 258 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6443600 # DTB read accesses -system.cpu1.dtb.write_accesses 5579583 # DTB write accesses +system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10118394 # DTB read accesses +system.cpu1.dtb.write_accesses 6545144 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 12017134 # DTB hits -system.cpu1.dtb.misses 6049 # DTB misses -system.cpu1.dtb.accesses 12023183 # DTB accesses +system.cpu1.dtb.hits 16660206 # DTB hits +system.cpu1.dtb.misses 3332 # DTB misses +system.cpu1.dtb.accesses 16663538 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1255,8 +1376,42 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 28023624 # ITB inst hits -system.cpu1.itb.inst_misses 2794 # ITB inst misses +system.cpu1.itb.walker.walks 1746 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 8955.736224 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 7685.889357 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5645.921496 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 191 17.25% 17.25% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 643 58.08% 75.34% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 217 19.60% 94.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.03% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.27% 95.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 27 2.44% 97.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.72% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1454651968 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1454651968 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1454651968 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 44359905 # ITB inst hits +system.cpu1.itb.inst_misses 1746 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1265,179 +1420,178 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1901 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 28026418 # ITB inst accesses -system.cpu1.itb.hits 28023624 # DTB hits -system.cpu1.itb.misses 2794 # DTB misses -system.cpu1.itb.accesses 28026418 # DTB accesses -system.cpu1.numCycles 5734097031 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 44361651 # ITB inst accesses +system.cpu1.itb.hits 44359905 # DTB hits +system.cpu1.itb.misses 1746 # DTB misses +system.cpu1.itb.accesses 44361651 # DTB accesses +system.cpu1.numCycles 5735725430 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 27233120 # Number of instructions committed -system.cpu1.committedOps 33143777 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 29468029 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6988 # Number of float alu accesses -system.cpu1.num_func_calls 1518648 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3438745 # number of instructions that are conditional controls -system.cpu1.num_int_insts 29468029 # number of integer instructions -system.cpu1.num_fp_insts 6988 # number of float instructions -system.cpu1.num_int_register_reads 53045981 # number of times the integer registers were read -system.cpu1.num_int_register_writes 20334319 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 5190 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1800 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 119969216 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 12226644 # number of times the CC registers were written -system.cpu1.num_mem_refs 12358568 # number of memory refs -system.cpu1.num_load_insts 6575418 # Number of load instructions -system.cpu1.num_store_insts 5783150 # Number of store instructions -system.cpu1.num_idle_cycles 5655719559.150027 # Number of idle cycles -system.cpu1.num_busy_cycles 78377471.849973 # Number of busy cycles -system.cpu1.not_idle_fraction 0.013669 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.986331 # Percentage of idle cycles -system.cpu1.Branches 5151142 # Number of branches fetched -system.cpu1.op_class::No_OpClass 168 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 21257809 63.16% 63.16% # Class of executed instruction -system.cpu1.op_class::IntMult 38403 0.11% 63.27% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4420 0.01% 63.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 63.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.28% # Class of executed instruction -system.cpu1.op_class::MemRead 6575418 19.54% 82.82% # Class of executed instruction -system.cpu1.op_class::MemWrite 5783150 17.18% 100.00% # Class of executed instruction +system.cpu1.committedInsts 42482884 # Number of instructions committed +system.cpu1.committedOps 52173895 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 47161467 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses +system.cpu1.num_func_calls 7121857 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4915281 # number of instructions that are conditional controls +system.cpu1.num_int_insts 47161467 # number of integer instructions +system.cpu1.num_fp_insts 1857 # number of float instructions +system.cpu1.num_int_register_reads 90906541 # number of times the integer registers were read +system.cpu1.num_int_register_writes 34070734 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 192636366 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 15749934 # number of times the CC registers were written +system.cpu1.num_mem_refs 16924073 # number of memory refs +system.cpu1.num_load_insts 10229886 # Number of load instructions +system.cpu1.num_store_insts 6694187 # Number of store instructions +system.cpu1.num_idle_cycles 5637554126.704413 # Number of idle cycles +system.cpu1.num_busy_cycles 98171303.295587 # Number of busy cycles +system.cpu1.not_idle_fraction 0.017116 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.982884 # Percentage of idle cycles +system.cpu1.Branches 12116511 # Number of branches fetched +system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 37117349 68.64% 68.64% # Class of executed instruction +system.cpu1.op_class::IntMult 29132 0.05% 68.70% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3361 0.01% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::MemRead 10229886 18.92% 87.62% # Class of executed instruction +system.cpu1.op_class::MemWrite 6694187 12.38% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 33659368 # Class of executed instruction +system.cpu1.op_class::total 54073981 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2818 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 321673 # number of replacements -system.cpu1.dcache.tags.tagsinuse 481.284483 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11622088 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 322185 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 36.072716 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 104113347000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.284483 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940009 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.940009 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 24380907 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 24380907 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 5961630 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 5961630 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 5307193 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 5307193 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 82380 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 82380 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 110885 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 110885 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 104150 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 104150 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11268823 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11268823 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11351203 # number of overall hits -system.cpu1.dcache.overall_hits::total 11351203 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 210202 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 210202 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 138084 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 138084 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 48251 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 48251 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19527 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 19527 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23870 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23870 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 348286 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 348286 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 396537 # number of overall misses -system.cpu1.dcache.overall_misses::total 396537 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2787267513 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2787267513 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2672172287 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2672172287 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 339794001 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 339794001 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 550321118 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 550321118 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1627000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1627000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5459439800 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5459439800 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5459439800 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5459439800 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 6171832 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 6171832 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5445277 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5445277 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 130631 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 130631 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 130412 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 130412 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 128020 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 128020 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 11617109 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 11617109 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 11747740 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 11747740 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034058 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.034058 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025358 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.025358 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.369369 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.369369 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149733 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149733 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.186455 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.186455 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029980 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.029980 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033754 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.033754 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13259.947636 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13259.947636 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19351.787948 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19351.787948 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17401.239361 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17401.239361 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23054.927440 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23054.927440 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2789 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 191058 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.360308 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 16390617 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 191421 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 85.626013 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 104654883500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.360308 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922579 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.922579 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 363 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 312 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.708984 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 33541448 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 33541448 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 9797337 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9797337 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6353174 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6353174 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49731 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 49731 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79655 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 79655 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71640 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71640 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 16150511 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 16150511 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 16200242 # number of overall hits +system.cpu1.dcache.overall_hits::total 16200242 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 137366 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 137366 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 93147 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 93147 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30426 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30426 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17223 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17223 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23379 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23379 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 230513 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 230513 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 260939 # number of overall misses +system.cpu1.dcache.overall_misses::total 260939 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1997360003 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1997360003 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2352005341 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2352005341 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320800000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 320800000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 539390293 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 539390293 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1691000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1691000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4349365344 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4349365344 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4349365344 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4349365344 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9934703 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9934703 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6446321 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6446321 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80157 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 80157 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96878 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 96878 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95019 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 95019 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16381024 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16381024 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16461181 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16461181 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013827 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.013827 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.014450 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.014450 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.379580 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.379580 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177780 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177780 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246046 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246046 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.014072 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.014072 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.015852 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.015852 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14540.424872 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14540.424872 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25250.467981 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 25250.467981 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18626.255588 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18626.255588 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23071.572480 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23071.572480 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15675.162941 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15675.162941 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13767.794178 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 13767.794178 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18868.199815 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18868.199815 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16668.130651 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16668.130651 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1446,82 +1600,82 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 197265 # number of writebacks -system.cpu1.dcache.writebacks::total 197265 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 459 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 459 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13505 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13505 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 459 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 459 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 459 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 459 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 209743 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 209743 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 138084 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 138084 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 46648 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 46648 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6022 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6022 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23870 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23870 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 347827 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 347827 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 394475 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 394475 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2356483739 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2356483739 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2388185713 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2388185713 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 637646247 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 637646247 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87580250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87580250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 501268882 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 501268882 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1557000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1557000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4744669452 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4744669452 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5382315699 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5382315699 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 968585999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 968585999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 845308497 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 845308497 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1813894496 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1813894496 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033984 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033984 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025358 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025358 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.357097 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.357097 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.046177 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.046177 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.186455 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.186455 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029941 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029941 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033579 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033579 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11235.100761 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11235.100761 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17295.166080 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17295.166080 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13669.315876 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 13669.315876 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14543.382597 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14543.382597 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20999.953163 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20999.953163 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 118649 # number of writebacks +system.cpu1.dcache.writebacks::total 118649 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 239 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 239 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12076 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12076 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 239 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 239 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 239 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 239 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 137127 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 137127 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 93147 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 93147 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29658 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29658 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5147 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5147 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23379 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23379 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 230274 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 230274 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 259932 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 259932 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1715737747 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1715737747 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2159697659 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2159697659 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 467259500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 467259500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82226250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82226250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 491497707 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 491497707 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1621000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1621000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3875435406 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3875435406 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4342694906 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4342694906 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 525084500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 525084500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 379956000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 379956000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 905040500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 905040500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013803 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013803 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014450 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014450 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369999 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369999 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053129 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053129 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246046 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246046 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014057 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.014057 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015791 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.015791 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.034443 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.034443 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23185.906782 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23185.906782 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15754.922786 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15754.922786 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15975.568292 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15975.568292 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21023.042346 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21023.042346 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13640.888867 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13640.888867 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13644.250457 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13644.250457 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16829.669898 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16829.669898 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16707.042250 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16707.042250 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1529,58 +1683,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 680772 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.691095 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 27342334 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 681284 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.133533 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 115083689500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.691095 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974006 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974006 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 526723 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.608741 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 43832665 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 527235 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 83.136865 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 84507534000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.608741 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973845 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973845 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 56728523 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 56728523 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 27342334 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 27342334 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 27342334 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 27342334 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 27342334 # number of overall hits -system.cpu1.icache.overall_hits::total 27342334 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 681285 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 681285 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 681285 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 681285 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 681285 # number of overall misses -system.cpu1.icache.overall_misses::total 681285 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5656981010 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5656981010 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5656981010 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5656981010 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5656981010 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5656981010 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 28023619 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 28023619 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 28023619 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 28023619 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 28023619 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 28023619 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024311 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024311 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024311 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024311 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024311 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024311 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8303.398739 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8303.398739 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8303.398739 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8303.398739 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8303.398739 # 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average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8758.828151 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8758.828151 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8758.828151 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8758.828151 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1589,361 +1743,347 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 681285 # 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average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7257.197910 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7257.197910 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 5735095 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 38649 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 5537320 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 267 # number of hwpf that were already in the prefetch queue -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 19 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 158840 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 604377 # number of hwpf spanning a virtual page -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 130093 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15612.463834 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1076740 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 146334 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 7.358099 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.num_hwpf_issued 199846 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 199846 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu1.l2cache.prefetcher.pfSpanPage 59474 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 47689 # 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Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 90 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2030 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4783 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 963 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2875 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4662 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 602 # 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number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12590000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 851009999 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 863599999 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.402554 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.119093 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.936708 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.936708 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.949005 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.949005 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950208 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950208 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962911 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962911 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.336732 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.336732 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.047498 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.074252 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.010576 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.303847 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.113073 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.047498 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.074252 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.010576 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.303847 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554427 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554427 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443434 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.154991 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443434 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.263175 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 25817.836919 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15289.635066 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16190.977194 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27298.605103 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27298.605103 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15053.474378 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15053.474378 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13783.958363 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13783.958363 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 255400 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 255400 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24270.038064 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24270.038064 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 25817.836919 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18155.154600 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18603.385918 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 25817.836919 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18155.154600 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27298.605103 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23562.702529 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186269 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14329.890366 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16489.633445 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33922.593888 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14198.385511 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14198.385511 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13595.618508 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13595.618508 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 447000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 447000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29385.354164 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29385.354164 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19396.677396 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20293.588805 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19396.677396 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 22582.097681 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1953,69 +2093,69 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1351518 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1008638 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 4998 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 4998 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 197265 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 224398 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 84264 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42890 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 91097 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 123576 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 111434 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1362924 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1150758 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8243 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16496 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2538421 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 43602948 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 39320783 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11636 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 21980 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 82957347 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 826396 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2054321 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.357816 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.479358 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1051189 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 750269 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 3091 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 3091 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 118649 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 33325 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 74679 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41637 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85827 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 85544 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 68027 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1054824 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 784590 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5329 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9434 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 1854177 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33743748 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25394480 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8020 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13648 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 59159896 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 572639 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1437265 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.343414 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.474848 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1319253 64.22% 64.22% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 735068 35.78% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 943688 65.66% 65.66% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 493577 34.34% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2054321 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 864974439 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1437265 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 595732734 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 89802999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80038500 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1022245510 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 791497760 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 593726174 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 388635637 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 5334000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 11001001 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 6022000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31015 # Transaction distribution -system.iobus.trans_dist::ReadResp 31015 # Transaction distribution -system.iobus.trans_dist::WriteReq 59437 # Transaction distribution -system.iobus.trans_dist::WriteResp 23213 # Transaction distribution +system.iobus.trans_dist::ReadReq 31024 # Transaction distribution +system.iobus.trans_dist::ReadResp 31024 # Transaction distribution +system.iobus.trans_dist::WriteReq 59440 # Transaction distribution +system.iobus.trans_dist::WriteResp 23216 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56642 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2031,16 +2171,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107950 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71586 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180928 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2056,11 +2196,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162833 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484089 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40126000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484122 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2070,7 +2210,7 @@ system.iobus.reqLayer3.occupancy 12000 # La system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 503000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2100,52 +2240,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347096127 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347109131 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84737000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36842563 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36846525 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36459 # number of replacements -system.iocache.tags.tagsinuse 14.453181 # Cycle average of tags in use +system.iocache.tags.replacements 36445 # number of replacements +system.iocache.tags.tagsinuse 14.387294 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36475 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 277163175000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.453181 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.903324 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.903324 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 287959539000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.387294 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.899206 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.899206 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328293 # Number of tag accesses -system.iocache.tags.data_accesses 328293 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 253 # number of ReadReq misses -system.iocache.ReadReq_misses::total 253 # number of ReadReq misses +system.iocache.tags.tag_accesses 328311 # Number of tag accesses +system.iocache.tags.data_accesses 328311 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses +system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses -system.iocache.demand_misses::realview.ide 253 # number of demand (read+write) misses -system.iocache.demand_misses::total 253 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 253 # number of overall misses -system.iocache.overall_misses::total 253 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31619377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31619377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9617084187 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9617084187 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31619377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31619377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31619377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31619377 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 253 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 253 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses +system.iocache.demand_misses::total 255 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 255 # number of overall misses +system.iocache.overall_misses::total 255 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 31782377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31782377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9599974229 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9599974229 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31782377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31782377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31782377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31782377 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 253 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 253 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 253 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 253 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses @@ -2154,40 +2294,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124977.774704 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124977.774704 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265489.294032 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265489.294032 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124977.774704 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124977.774704 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124977.774704 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124977.774704 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56586 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124636.772549 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124636.772549 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265016.956410 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 265016.956410 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124636.772549 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124636.772549 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 55555 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7227 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7160 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.829805 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.759078 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36206 # number of writebacks -system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 253 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 253 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 253 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 253 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 253 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 253 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18462377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18462377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7733310313 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7733310313 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18462377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18462377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18462377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18462377 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18521377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18521377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7716276279 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7716276279 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18521377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18521377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18521377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18521377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -2196,517 +2336,491 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72973.822134 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72973.822134 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213485.819153 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213485.819153 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72973.822134 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72973.822134 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72973.822134 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72973.822134 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72632.850980 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72632.850980 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213015.577490 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213015.577490 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 132552 # number of replacements -system.l2c.tags.tagsinuse 64217.240538 # Cycle average of tags in use -system.l2c.tags.total_refs 486427 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 197317 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.465206 # Average number of references to valid blocks. +system.l2c.tags.replacements 130735 # number of replacements +system.l2c.tags.tagsinuse 63966.604731 # Cycle average of tags in use +system.l2c.tags.total_refs 343053 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 195063 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.758678 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12673.098262 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.830088 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.037001 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1135.719993 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1432.608438 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38719.774998 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.654088 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007784 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 545.091140 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 913.810052 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8789.608693 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.193376 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000074 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.017330 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.021860 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.590817 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000040 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008317 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.013944 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.134119 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.979877 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 45108 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 19652 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 175 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5031 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 39902 # 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average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 808.192553 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2202.571178 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1431.168638 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1145.435208 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1660.732950 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1470.089100 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 79364.001658 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72073.162959 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 75833.280865 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 87319.421565 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 81034.479627 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 99352.822977 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74875 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 91519.252708 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 74634.595409 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 111502.433801 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 98663.223350 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 87319.421565 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 81034.479627 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 99352.822977 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74875 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 91519.252708 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 74634.595409 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 111502.433801 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 98663.223350 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 6 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 12083.139597 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.938906 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.007553 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 6678.027236 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2760.487108 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38360.306045 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.955640 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1552.248405 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 535.801693 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1990.692549 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.184374 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.101899 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.042122 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.585332 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.023685 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008176 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030376 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.976053 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 32989 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 31331 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 170 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4524 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 28295 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 254 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1895 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 29170 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.503372 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.478073 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 4931105 # Number of tag accesses +system.l2c.tags.data_accesses 4931105 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 82 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 29372 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 45566 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 45492 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 34 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 41 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 11667 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 8537 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 5785 # number of ReadReq hits +system.l2c.ReadReq_hits::total 146639 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 227719 # number of Writeback hits +system.l2c.Writeback_hits::total 227719 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 2362 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 770 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3132 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 164 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 164 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 328 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 3862 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1497 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5359 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 82 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 29372 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 49428 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 45492 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 34 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 41 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 11667 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 10034 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 5785 # number of demand (read+write) hits +system.l2c.demand_hits::total 151998 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 82 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits +system.l2c.overall_hits::cpu0.inst 29372 # number of overall hits +system.l2c.overall_hits::cpu0.data 49428 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 45492 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 34 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 41 # number of overall hits +system.l2c.overall_hits::cpu1.inst 11667 # number of overall hits +system.l2c.overall_hits::cpu1.data 10034 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 5785 # number of overall hits +system.l2c.overall_hits::total 151998 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 17779 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 8894 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 134996 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2435 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 924 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 5907 # number of ReadReq misses +system.l2c.ReadReq_misses::total 170945 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 8889 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2898 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11787 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 758 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1209 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1967 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11387 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8562 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 19949 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 17779 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 20281 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 134996 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2435 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 9486 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 5907 # number of demand (read+write) misses +system.l2c.demand_misses::total 190894 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu0.inst 17779 # number of overall misses +system.l2c.overall_misses::cpu0.data 20281 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 134996 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2435 # number of overall misses +system.l2c.overall_misses::cpu1.data 9486 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 5907 # 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number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 2108409 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 7531728 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 679977 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 605974 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1285951 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 888864663 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 627516972 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1516381635 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 494750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1299838245 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1597496411 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13069199153 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 75000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 182647247 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 706193472 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 680911899 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 17537005677 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 494750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1299838245 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1597496411 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13069199153 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 75000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 182647247 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 706193472 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 680911899 # number of overall miss cycles +system.l2c.overall_miss_latency::total 17537005677 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 89 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 65 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 47151 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 54460 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 180488 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 35 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 41 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 14102 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 9461 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 11692 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 317584 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 227719 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 227719 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 11251 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3668 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 14919 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 922 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1373 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2295 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 15249 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 10059 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 25308 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 89 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 65 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 47151 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 69709 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 180488 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 35 # 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average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10028.996411 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10078.564450 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66867.098475 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59414.478284 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63258.032062 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72782.231853 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 81259.023827 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10136.837890 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10036.709800 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10112.219988 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10172.500000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.720430 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10069.375699 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65540.206815 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60643.193880 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63438.436062 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74894.283534 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68574.540280 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86919.130959 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 66273.437355 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 79081.226233 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62016.054204 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 86246.639722 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61824.462414 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 79396.679517 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74894.283534 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68574.540280 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86919.130959 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 66273.437355 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 79081.226233 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62016.054204 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 86246.639722 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61824.462414 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 79396.679517 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2721,58 +2835,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 228161 # Transaction distribution -system.membus.trans_dist::ReadResp 228160 # Transaction distribution -system.membus.trans_dist::WriteReq 31188 # Transaction distribution -system.membus.trans_dist::WriteResp 31188 # Transaction distribution -system.membus.trans_dist::Writeback 135887 # Transaction distribution +system.membus.trans_dist::ReadReq 215303 # Transaction distribution +system.membus.trans_dist::ReadResp 215303 # Transaction distribution +system.membus.trans_dist::WriteReq 30982 # Transaction distribution +system.membus.trans_dist::WriteResp 30982 # Transaction distribution +system.membus.trans_dist::Writeback 135225 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 85485 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41282 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15173 # Transaction distribution +system.membus.trans_dist::UpgradeReq 76008 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40410 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13867 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 28446 # Transaction distribution -system.membus.trans_dist::ReadExResp 11501 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107950 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 40350 # Transaction distribution +system.membus.trans_dist::ReadExResp 19836 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14612 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 676793 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 799389 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108922 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108922 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 908311 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162833 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 659440 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 781206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 890114 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18898536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19090661 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23727141 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 129157 # Total snoops (count) -system.membus.snoop_fanout::samples 511174 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27524 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18582632 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18773074 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23408530 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123675 # Total snoops (count) +system.membus.snoop_fanout::samples 499419 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 511174 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 499419 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 511174 # Request fanout histogram -system.membus.reqLayer0.occupancy 88144997 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 499419 # Request fanout histogram +system.membus.reqLayer0.occupancy 88165000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12118496 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11453500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1838586997 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1828859499 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1967573382 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1931425684 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38564437 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38544475 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2805,44 +2919,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 630354 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 630338 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31188 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31188 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 239712 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 95586 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41643 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 137229 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 39856 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 39856 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1145062 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 504022 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1649084 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 33792786 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 11864019 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45656805 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 304478 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1039135 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.035103 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.184041 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 482729 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 482714 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30982 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30982 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 227719 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 79027 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40738 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 119765 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 81 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51496 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51496 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1065854 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 282098 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1347952 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31837086 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4944756 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 36781842 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 286323 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 873908 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.041744 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.200003 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1002658 96.49% 96.49% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36477 3.51% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 837428 95.83% 95.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36480 4.17% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1039135 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1515175521 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 873908 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1446151615 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1080000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1922628953 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1735034184 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1047459467 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 618323353 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |