diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-02 06:08:25 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-02 06:08:25 -0500 |
| commit | 6489598fb449531c34bfb25a52189196ee2b1086 (patch) | |
| tree | 5f8bb88862ffd187cb7b182f4a0d20599b4409bf /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt | |
| parent | 966c3f4bc5581347a411c25db1440afb97f12dab (diff) | |
| download | gem5-6489598fb449531c34bfb25a52189196ee2b1086.tar.xz | |
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt | 4287 |
1 files changed, 2160 insertions, 2127 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 23357c831..ede2b82db 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,169 +1,166 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.866913 # Number of seconds simulated -sim_ticks 2866913114000 # Number of ticks simulated -final_tick 2866913114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.867049 # Number of seconds simulated +sim_ticks 2867048515500 # Number of ticks simulated +final_tick 2867048515500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 786450 # Simulator instruction rate (inst/s) -host_op_rate 951292 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17090693254 # Simulator tick rate (ticks/s) -host_mem_usage 609256 # Number of bytes of host memory used -host_seconds 167.75 # Real time elapsed on the host -sim_insts 131924636 # Number of instructions simulated -sim_ops 159576421 # Number of ops (including micro ops) simulated +host_inst_rate 753572 # Simulator instruction rate (inst/s) +host_op_rate 911512 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16376301643 # Simulator tick rate (ticks/s) +host_mem_usage 607016 # Number of bytes of host memory used +host_seconds 175.07 # Real time elapsed on the host +sim_insts 131930165 # Number of instructions simulated +sim_ops 159581077 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 236004 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 838784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 9619456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 233060 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 810048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 9243456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 50964 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 440736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 1362944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 53844 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 455584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 1704320 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12550680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 236004 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 50964 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 286968 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6395008 # Number of bytes written to this memory +system.physmem.bytes_read::total 12502168 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 233060 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 53844 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 286904 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8696768 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory -system.physmem.bytes_written::total 8731088 # Number of bytes written to this memory +system.physmem.bytes_written::total 8714512 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12141 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 13632 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 150304 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12095 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 13183 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 144429 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 951 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6910 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 21296 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 996 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 7142 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 26630 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 205262 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 99922 # Number of write requests responded to by this memory +system.physmem.num_reads::total 204504 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 135887 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory -system.physmem.num_writes::total 140582 # Number of write requests responded to by this memory +system.physmem.num_writes::total 140323 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 179 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 82320 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 292574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3355336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 67 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 81289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 282537 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3224032 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 89 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 17777 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 153732 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 475405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 18780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 158903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 594451 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4377768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 82320 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 17777 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 100097 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2230625 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4360641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 81289 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 18780 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 100069 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3033352 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6175 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 808652 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3045467 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2230625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3039541 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3033352 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 179 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 82320 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 298749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3355336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 67 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 81289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 288712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3224032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 89 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 17777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 153746 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 475405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 808987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7423234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 205263 # Number of read requests accepted -system.physmem.writeReqs 140582 # Number of write requests accepted -system.physmem.readBursts 205263 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 140582 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 13120768 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 16064 # Total number of bytes read from write queue -system.physmem.bytesWritten 8744768 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12550744 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8731088 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 251 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3914 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 15112 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12846 # Per bank write bursts -system.physmem.perBankRdBursts::1 12299 # Per bank write bursts -system.physmem.perBankRdBursts::2 13037 # Per bank write bursts -system.physmem.perBankRdBursts::3 12736 # Per bank write bursts -system.physmem.perBankRdBursts::4 21227 # Per bank write bursts -system.physmem.perBankRdBursts::5 12513 # Per bank write bursts -system.physmem.perBankRdBursts::6 12853 # Per bank write bursts -system.physmem.perBankRdBursts::7 12957 # Per bank write bursts -system.physmem.perBankRdBursts::8 12050 # Per bank write bursts -system.physmem.perBankRdBursts::9 12106 # Per bank write bursts -system.physmem.perBankRdBursts::10 12270 # Per bank write bursts -system.physmem.perBankRdBursts::11 11010 # Per bank write bursts -system.physmem.perBankRdBursts::12 11804 # Per bank write bursts -system.physmem.perBankRdBursts::13 12158 # Per bank write bursts -system.physmem.perBankRdBursts::14 11709 # Per bank write bursts -system.physmem.perBankRdBursts::15 11437 # Per bank write bursts -system.physmem.perBankWrBursts::0 8735 # Per bank write bursts -system.physmem.perBankWrBursts::1 8638 # Per bank write bursts -system.physmem.perBankWrBursts::2 9213 # Per bank write bursts -system.physmem.perBankWrBursts::3 8824 # Per bank write bursts -system.physmem.perBankWrBursts::4 8594 # Per bank write bursts -system.physmem.perBankWrBursts::5 8713 # Per bank write bursts -system.physmem.perBankWrBursts::6 8840 # Per bank write bursts -system.physmem.perBankWrBursts::7 8875 # Per bank write bursts -system.physmem.perBankWrBursts::8 8399 # Per bank write bursts -system.physmem.perBankWrBursts::9 8546 # Per bank write bursts -system.physmem.perBankWrBursts::10 8611 # Per bank write bursts -system.physmem.perBankWrBursts::11 8118 # Per bank write bursts -system.physmem.perBankWrBursts::12 8409 # Per bank write bursts -system.physmem.perBankWrBursts::13 8327 # Per bank write bursts -system.physmem.perBankWrBursts::14 8185 # Per bank write bursts -system.physmem.perBankWrBursts::15 7610 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 18780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 158917 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 594451 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7400182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 204505 # Number of read requests accepted +system.physmem.writeReqs 176547 # Number of write requests accepted +system.physmem.readBursts 204505 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 176547 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 13079232 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9088 # Total number of bytes read from write queue +system.physmem.bytesWritten 10932800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12502232 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11032848 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 142 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5691 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 15171 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12666 # Per bank write bursts +system.physmem.perBankRdBursts::1 12263 # Per bank write bursts +system.physmem.perBankRdBursts::2 12897 # Per bank write bursts +system.physmem.perBankRdBursts::3 12449 # Per bank write bursts +system.physmem.perBankRdBursts::4 21010 # Per bank write bursts +system.physmem.perBankRdBursts::5 12626 # Per bank write bursts +system.physmem.perBankRdBursts::6 12991 # Per bank write bursts +system.physmem.perBankRdBursts::7 13024 # Per bank write bursts +system.physmem.perBankRdBursts::8 12039 # Per bank write bursts +system.physmem.perBankRdBursts::9 12109 # Per bank write bursts +system.physmem.perBankRdBursts::10 12276 # Per bank write bursts +system.physmem.perBankRdBursts::11 10996 # Per bank write bursts +system.physmem.perBankRdBursts::12 11725 # Per bank write bursts +system.physmem.perBankRdBursts::13 12231 # Per bank write bursts +system.physmem.perBankRdBursts::14 11672 # Per bank write bursts +system.physmem.perBankRdBursts::15 11389 # Per bank write bursts +system.physmem.perBankWrBursts::0 10702 # Per bank write bursts +system.physmem.perBankWrBursts::1 10814 # Per bank write bursts +system.physmem.perBankWrBursts::2 11122 # Per bank write bursts +system.physmem.perBankWrBursts::3 10684 # Per bank write bursts +system.physmem.perBankWrBursts::4 10817 # Per bank write bursts +system.physmem.perBankWrBursts::5 11014 # Per bank write bursts +system.physmem.perBankWrBursts::6 11094 # Per bank write bursts +system.physmem.perBankWrBursts::7 11085 # Per bank write bursts +system.physmem.perBankWrBursts::8 10650 # Per bank write bursts +system.physmem.perBankWrBursts::9 11040 # Per bank write bursts +system.physmem.perBankWrBursts::10 10845 # Per bank write bursts +system.physmem.perBankWrBursts::11 10150 # Per bank write bursts +system.physmem.perBankWrBursts::12 10760 # Per bank write bursts +system.physmem.perBankWrBursts::13 10359 # Per bank write bursts +system.physmem.perBankWrBursts::14 10115 # Per bank write bursts +system.physmem.perBankWrBursts::15 9574 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 7 # Number of times write queue was full causing retry -system.physmem.totGap 2866912757000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2867048141000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9742 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 195493 # Read request sizes (log2) +system.physmem.readPktSize::6 194735 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 136146 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 121382 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21626 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9518 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 8180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 7045 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 6231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 5373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 545 # What read queue length does an incoming req see +system.physmem.writePktSize::6 172111 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 120800 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21636 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13302 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 11154 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9500 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 8185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6994 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 6210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 5370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 523 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 166 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 75 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 70 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -191,154 +188,178 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 80938 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 270.150881 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 152.124225 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 319.049708 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 39103 48.31% 48.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16130 19.93% 68.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6485 8.01% 76.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3355 4.15% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3128 3.86% 84.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1920 2.37% 86.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1075 1.33% 87.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1014 1.25% 89.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8728 10.78% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 80938 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6722 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.497025 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 543.729847 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6720 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 11783 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 10823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 83215 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 288.553362 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 159.296581 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 336.078048 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 39267 47.19% 47.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16171 19.43% 66.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6480 7.79% 74.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3347 4.02% 78.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3132 3.76% 82.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1913 2.30% 84.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1073 1.29% 85.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1034 1.24% 87.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10798 12.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 83215 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7042 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.019171 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 531.269210 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7040 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6722 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6722 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.326837 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.830242 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.742760 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5511 81.98% 81.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 381 5.67% 87.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 92 1.37% 89.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 211 3.14% 92.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 209 3.11% 95.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.31% 95.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 13 0.19% 95.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 14 0.21% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 24 0.36% 96.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.12% 96.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.07% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.06% 96.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 163 2.42% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 8 0.12% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.04% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 17 0.25% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 7 0.10% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.04% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 7 0.10% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.12% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6722 # Writes before turning the bus around for reads -system.physmem.totQLat 5976562250 # Total ticks spent queuing -system.physmem.totMemAccLat 9820537250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1025060000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29152.26 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7042 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7042 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.258023 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.337274 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.786425 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5509 78.23% 78.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 384 5.45% 83.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 77 1.09% 84.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 222 3.15% 87.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 122 1.73% 89.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 57 0.81% 90.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 43 0.61% 91.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 37 0.53% 91.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 124 1.76% 93.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 15 0.21% 93.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 18 0.26% 93.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 16 0.23% 94.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 34 0.48% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 16 0.23% 94.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 7 0.10% 94.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 27 0.38% 95.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 62 0.88% 96.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 11 0.16% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 6 0.09% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 10 0.14% 96.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 88 1.25% 97.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 97.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 12 0.17% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 6 0.09% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 19 0.27% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 11 0.16% 98.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 4 0.06% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 36 0.51% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 11 0.16% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.06% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 7 0.10% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 5 0.07% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.03% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 7 0.10% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 4 0.06% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.06% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 2 0.03% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 2 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7042 # Writes before turning the bus around for reads +system.physmem.totQLat 5974898500 # Total ticks spent queuing +system.physmem.totMemAccLat 9806704750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1021815000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29236.69 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47902.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.58 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.05 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47986.69 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.56 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.81 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.36 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtil 0.07 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.80 # Average write queue length when enqueuing -system.physmem.readRowHits 175010 # Number of row buffer hits during reads -system.physmem.writeRowHits 85700 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.71 # Row buffer hit rate for writes -system.physmem.avgGap 8289588.56 # Average gap between requests -system.physmem.pageHitRate 76.30 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2731202883250 # Time in different power states -system.physmem.memoryStateTime::REF 95732520000 # Time in different power states +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 2.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing +system.physmem.readRowHits 174382 # Number of row buffer hits during reads +system.physmem.writeRowHits 117590 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.33 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 68.82 # Row buffer hit rate for writes +system.physmem.avgGap 7524033.84 # Average gap between requests +system.physmem.pageHitRate 77.81 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2731090191250 # Time in different power states +system.physmem.memoryStateTime::REF 95736940000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 39977707750 # Time in different power states +system.physmem.memoryStateTime::ACT 40221363750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 322237440 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 289653840 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 175824000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 158045250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 861650400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 737435400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 456399360 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 429008400 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 187252809120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 187252809120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 82565899920 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 81397166220 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1647721613250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1648746818250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1919356433490 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1919010936480 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.485397 # Core power per rank (mW) -system.physmem.averagePower::1 669.364885 # Core power per rank (mW) +system.physmem.actEnergy::0 330432480 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 298672920 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 180295500 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 162966375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 857422800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 736600800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 565911360 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 541034640 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 187261454640 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 187261454640 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 82724898285 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 81530993385 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1647661560750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1648708845750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1919581975815 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1919240568510 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.533155 # Core power per rank (mW) +system.physmem.averagePower::1 669.414075 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -387,25 +408,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 24351477 # DTB read hits -system.cpu0.dtb.read_misses 6408 # DTB read misses -system.cpu0.dtb.write_hits 18124986 # DTB write hits -system.cpu0.dtb.write_misses 1114 # DTB write misses +system.cpu0.dtb.read_hits 22739909 # DTB read hits +system.cpu0.dtb.read_misses 4142 # DTB read misses +system.cpu0.dtb.write_hits 16676295 # DTB write hits +system.cpu0.dtb.write_misses 677 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3406 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2392 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1440 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1346 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 24357885 # DTB read accesses -system.cpu0.dtb.write_accesses 18126100 # DTB write accesses +system.cpu0.dtb.perms_faults 187 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 22744051 # DTB read accesses +system.cpu0.dtb.write_accesses 16676972 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 42476463 # DTB hits -system.cpu0.dtb.misses 7522 # DTB misses -system.cpu0.dtb.accesses 42483985 # DTB accesses +system.cpu0.dtb.hits 39416204 # DTB hits +system.cpu0.dtb.misses 4819 # DTB misses +system.cpu0.dtb.accesses 39421023 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -427,8 +448,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 115065570 # ITB inst hits -system.cpu0.itb.inst_misses 3350 # ITB inst misses +system.cpu0.itb.inst_hits 107931670 # ITB inst hits +system.cpu0.itb.inst_misses 2300 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -437,179 +458,178 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2152 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1397 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 115068920 # ITB inst accesses -system.cpu0.itb.hits 115065570 # DTB hits -system.cpu0.itb.misses 3350 # DTB misses -system.cpu0.itb.accesses 115068920 # DTB accesses -system.cpu0.numCycles 5733826228 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 107933970 # ITB inst accesses +system.cpu0.itb.hits 107931670 # DTB hits +system.cpu0.itb.misses 2300 # DTB misses +system.cpu0.itb.accesses 107933970 # DTB accesses +system.cpu0.numCycles 5733190951 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 111421445 # Number of instructions committed -system.cpu0.committedOps 134708041 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 119418221 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses -system.cpu0.num_func_calls 12527454 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14979151 # number of instructions that are conditional controls -system.cpu0.num_int_insts 119418221 # number of integer instructions -system.cpu0.num_fp_insts 9755 # number of float instructions -system.cpu0.num_int_register_reads 220362058 # number of times the integer registers were read -system.cpu0.num_int_register_writes 83043778 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 488373650 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 49988627 # number of times the CC registers were written -system.cpu0.num_mem_refs 43585923 # number of memory refs -system.cpu0.num_load_insts 24597873 # Number of load instructions -system.cpu0.num_store_insts 18988050 # Number of store instructions -system.cpu0.num_idle_cycles 5477680330.504089 # Number of idle cycles -system.cpu0.num_busy_cycles 256145897.495911 # Number of busy cycles -system.cpu0.not_idle_fraction 0.044673 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.955327 # Percentage of idle cycles -system.cpu0.Branches 28215151 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2272 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 94727035 68.43% 68.43% # Class of executed instruction -system.cpu0.op_class::IntMult 104174 0.08% 68.51% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 7381 0.01% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::MemRead 24597873 17.77% 86.28% # Class of executed instruction -system.cpu0.op_class::MemWrite 18988050 13.72% 100.00% # Class of executed instruction +system.cpu0.committedInsts 104697045 # Number of instructions committed +system.cpu0.committedOps 126437300 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 112138973 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4560 # Number of float alu accesses +system.cpu0.num_func_calls 12218983 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14112779 # number of instructions that are conditional controls +system.cpu0.num_int_insts 112138973 # number of integer instructions +system.cpu0.num_fp_insts 4560 # number of float instructions +system.cpu0.num_int_register_reads 207168140 # number of times the integer registers were read +system.cpu0.num_int_register_writes 78157614 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3646 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 458862041 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 46623468 # number of times the CC registers were written +system.cpu0.num_mem_refs 40473955 # number of memory refs +system.cpu0.num_load_insts 22968630 # Number of load instructions +system.cpu0.num_store_insts 17505325 # Number of store instructions +system.cpu0.num_idle_cycles 5494072814.437573 # Number of idle cycles +system.cpu0.num_busy_cycles 239118136.562427 # Number of busy cycles +system.cpu0.not_idle_fraction 0.041708 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.958292 # Percentage of idle cycles +system.cpu0.Branches 26957408 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2171 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 89486890 68.80% 68.80% # Class of executed instruction +system.cpu0.op_class::IntMult 99356 0.08% 68.88% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 6997 0.01% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::MemRead 22968630 17.66% 86.54% # Class of executed instruction +system.cpu0.op_class::MemWrite 17505325 13.46% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 138426785 # Class of executed instruction +system.cpu0.op_class::total 130069369 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 2075 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 658574 # number of replacements -system.cpu0.dcache.tags.tagsinuse 484.573597 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 41679745 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 659086 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 63.238705 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 1990 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 555287 # number of replacements +system.cpu0.dcache.tags.tagsinuse 484.900335 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 38705991 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 555652 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 69.658691 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1015660000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.573597 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946433 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.946433 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 85564578 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 85564578 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 23153254 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23153254 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 17430094 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 17430094 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 323112 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 323112 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 358254 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 358254 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 353760 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 353760 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 40583348 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 40583348 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 40906460 # number of overall hits -system.cpu0.dcache.overall_hits::total 40906460 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 360294 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 360294 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 297575 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 297575 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 106237 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 106237 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21398 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21398 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21370 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 21370 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 657869 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 657869 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 764106 # number of overall misses -system.cpu0.dcache.overall_misses::total 764106 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4477052020 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4477052020 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4450265428 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4450265428 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 335153501 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 335153501 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 473430117 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 473430117 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1336000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1336000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8927317448 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 8927317448 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8927317448 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 8927317448 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 23513548 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23513548 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 17727669 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 17727669 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 429349 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 429349 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379652 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 379652 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 375130 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 375130 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 41241217 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 41241217 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 41670566 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 41670566 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015323 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.015323 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016786 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.016786 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.247437 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.247437 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056362 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056362 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056967 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056967 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015952 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.015952 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018337 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.018337 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12426.107623 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12426.107623 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14955.105194 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 14955.105194 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15662.842368 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15662.842368 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22153.959616 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22153.959616 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.900335 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947071 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.947071 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 302 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 79342035 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 79342035 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 21654746 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 21654746 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 16040843 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 16040843 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 304713 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 304713 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 334336 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 334336 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 329300 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 329300 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 37695589 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 37695589 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 38000302 # number of overall hits +system.cpu0.dcache.overall_hits::total 38000302 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 304912 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 304912 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 263418 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 263418 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 92252 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 92252 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20070 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20070 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20705 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20705 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 568330 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 568330 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 660582 # number of overall misses +system.cpu0.dcache.overall_misses::total 660582 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3916535020 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3916535020 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4029841681 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4029841681 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 322461501 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 322461501 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 462579693 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 462579693 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1480500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1480500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 7946376701 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 7946376701 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 7946376701 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 7946376701 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 21959658 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 21959658 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 16304261 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 16304261 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 396965 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 396965 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 354406 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 354406 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 350005 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 350005 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 38263919 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 38263919 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 38660884 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 38660884 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013885 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.013885 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016156 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.016156 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.232393 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.232393 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056630 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056630 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.059156 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.059156 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.014853 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.014853 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.017087 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.017087 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12844.804468 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12844.804468 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15298.277570 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15298.277570 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16066.841106 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16066.841106 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22341.448587 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22341.448587 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13570.053381 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13570.053381 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11683.349493 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 11683.349493 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13981.976494 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13981.976494 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12029.356993 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12029.356993 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -618,82 +638,82 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 483361 # number of writebacks -system.cpu0.dcache.writebacks::total 483361 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7378 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 7378 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15071 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15071 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 7378 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 7378 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 7378 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 7378 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 352916 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 352916 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297575 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 297575 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 96924 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 96924 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6327 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6327 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21370 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 21370 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 650491 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 650491 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 747415 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 747415 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3678269480 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3678269480 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3844865572 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3844865572 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1196073992 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1196073992 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 89532500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89532500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 429878883 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 429878883 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1262000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1262000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7523135052 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7523135052 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8719209044 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 8719209044 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5564453750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5564453750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4183862994 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4183862994 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9748316744 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9748316744 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015009 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015009 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016786 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016786 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225746 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225746 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016665 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016665 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056967 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056967 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015773 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015773 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017936 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.017936 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10422.506999 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10422.506999 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12920.660580 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12920.660580 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12340.328422 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12340.328422 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14150.861388 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14150.861388 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20115.998269 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20115.998269 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 420867 # number of writebacks +system.cpu0.dcache.writebacks::total 420867 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7211 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 7211 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14132 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14132 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 7211 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 7211 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 7211 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 7211 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 297701 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 297701 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 263418 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 263418 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 83423 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 83423 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5938 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5938 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20705 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20705 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 561119 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 561119 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 644542 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 644542 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3232031980 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3232031980 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3494328319 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3494328319 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1040331239 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1040331239 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 86260500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 86260500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 420440307 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 420440307 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1400500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1400500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6726360299 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6726360299 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7766691538 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7766691538 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5556589244 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5556589244 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4171949493 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4171949493 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9728538737 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9728538737 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.013557 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.013557 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016156 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016156 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.210152 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.210152 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016755 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016755 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.059156 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.059156 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.014664 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.014664 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.016672 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.016672 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10856.637969 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10856.637969 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13265.336154 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13265.336154 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12470.556549 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12470.556549 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14526.860896 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14526.860896 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20306.221058 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20306.221058 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11565.317663 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11565.317663 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11665.820252 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11665.820252 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11987.404274 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11987.404274 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12049.938620 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12049.938620 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -701,58 +721,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1061124 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.483230 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 114003925 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1061636 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 107.385135 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 945322 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.483250 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 106985827 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 945834 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 113.112689 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 12806917500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483230 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483250 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998991 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998991 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 390 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 113 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::4 9 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 231192785 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 231192785 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 114003925 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 114003925 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 114003925 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 114003925 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 114003925 # number of overall hits -system.cpu0.icache.overall_hits::total 114003925 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1061645 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1061645 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1061645 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1061645 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1061645 # number of overall misses -system.cpu0.icache.overall_misses::total 1061645 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9000982497 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9000982497 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9000982497 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9000982497 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9000982497 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9000982497 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 115065570 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 115065570 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 115065570 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 115065570 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 115065570 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 115065570 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009226 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.009226 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009226 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.009226 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009226 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.009226 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8478.335505 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8478.335505 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8478.335505 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8478.335505 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8478.335505 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8478.335505 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 216809183 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 216809183 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 106985827 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 106985827 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 106985827 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 106985827 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 106985827 # number of overall hits +system.cpu0.icache.overall_hits::total 106985827 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 945843 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 945843 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 945843 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 945843 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 945843 # number of overall misses +system.cpu0.icache.overall_misses::total 945843 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8025066767 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 8025066767 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 8025066767 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 8025066767 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 8025066767 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 8025066767 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 107931670 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 107931670 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 107931670 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 107931670 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 107931670 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 107931670 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.008763 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.008763 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.008763 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.008763 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.008763 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.008763 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8484.565374 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8484.565374 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8484.565374 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8484.565374 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8484.565374 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8484.565374 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -761,359 +781,356 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1061645 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1061645 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1061645 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1061645 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1061645 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1061645 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7407816003 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 7407816003 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7407816003 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 7407816003 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7407816003 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 7407816003 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 945843 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 945843 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 945843 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 945843 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 945843 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 945843 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6605629733 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6605629733 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6605629733 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6605629733 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6605629733 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6605629733 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719096500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719096500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719096500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 719096500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009226 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009226 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009226 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6977.677098 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6977.677098 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6977.677098 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 6977.677098 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6977.677098 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 6977.677098 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.008763 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.008763 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.008763 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.008763 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.008763 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.008763 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6983.854332 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6983.854332 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6983.854332 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 6983.854332 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6983.854332 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 6983.854332 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 9923384 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 228338 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9249316 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 376 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 8798864 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 212139 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 8184021 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 360 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 35 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 445319 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 778112 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 34 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 402310 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 695408 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 357554 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16100.801595 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1935390 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 373791 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.177733 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 309925 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16107.929627 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1687462 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 325154 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.189732 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6719.608952 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.125628 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.135893 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 793.879272 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1140.668616 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7443.383233 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.410132 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000191 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.048455 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.069621 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.454308 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.982715 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7987 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8246 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 35 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 107 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1881 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4986 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 978 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2886 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4666 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 532 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.487488 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.503296 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 38013369 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 38013369 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7065 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3186 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1046032 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 372434 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1428717 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 483361 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 483361 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 10097 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 10097 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2054 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 2054 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 212764 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 212764 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7065 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3186 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1046032 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 585198 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1641481 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7065 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3186 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1046032 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 585198 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1641481 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 284 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 213 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 15613 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 83733 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 99843 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 29803 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 29803 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19308 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 19308 # number of SCUpgradeReq misses +system.cpu0.l2cache.tags.occ_blocks::writebacks 6744.420736 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.207457 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.111326 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 773.977995 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1150.108298 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7436.103816 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.411647 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000196 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.047240 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.070197 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.453864 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.983150 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 9588 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 5627 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 66 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 1190 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 8332 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 265 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 1207 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4155 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.585205 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.343445 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 33371196 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 33371196 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 4956 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 2411 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 933239 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 309750 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 1250356 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 420867 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 420867 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 9645 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 9645 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1640 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 1640 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 182991 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 182991 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 4956 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 2411 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 933239 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 492741 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1433347 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 4956 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 2411 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 933239 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 492741 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1433347 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 350 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 252 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 12604 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 77312 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 90518 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 29431 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 29431 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19057 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 19057 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44911 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 44911 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 284 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 213 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 15613 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 128644 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 144754 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 284 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 213 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 15613 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 128644 # number of overall misses -system.cpu0.l2cache.overall_misses::total 144754 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 6608000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4758500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 598124482 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2271341908 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 2880832890 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 522877259 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 522877259 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 377985887 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 377985887 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1224995 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1224995 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1513514605 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 1513514605 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 6608000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4758500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 598124482 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 3784856513 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 4394347495 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 6608000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4758500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 598124482 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 3784856513 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 4394347495 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7349 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3399 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1061645 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 456167 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 1528560 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 483361 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 483361 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 39900 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 39900 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21362 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 21362 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 41351 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 41351 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 350 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 252 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 12604 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 118663 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 131869 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 350 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 252 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 12604 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 118663 # number of overall misses +system.cpu0.l2cache.overall_misses::total 131869 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 7623500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 5202000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 531081224 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2111775663 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 2655682387 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 520147939 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 520147939 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 371818814 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 371818814 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1360495 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1360495 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1399039190 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 1399039190 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 7623500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 5202000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 531081224 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 3510814853 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 4054721577 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 7623500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 5202000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 531081224 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 3510814853 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 4054721577 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 5306 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 2663 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 945843 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 387062 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 1340874 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 420867 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 420867 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 39076 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 39076 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20697 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 20697 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 257675 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 257675 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7349 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3399 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1061645 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 713842 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1786235 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7349 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3399 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1061645 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 713842 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1786235 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.038645 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.062665 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.014706 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.183558 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.065318 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.746942 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.746942 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.903848 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.903848 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 224342 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 224342 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 5306 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 2663 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 945843 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 611404 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1565216 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 5306 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 2663 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 945843 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 611404 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1565216 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.065963 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.094630 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.013326 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.199741 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.067507 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.753173 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.753173 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.920761 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.920761 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.174293 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.174293 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.038645 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.062665 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.014706 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.180214 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.081039 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.038645 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.062665 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.014706 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.180214 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.081039 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23267.605634 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22340.375587 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 38309.388458 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 27126.006568 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28853.629098 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17544.450525 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17544.450525 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19576.646312 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19576.646312 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 153124.375000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 153124.375000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33700.309612 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 33700.309612 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23267.605634 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22340.375587 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38309.388458 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29421.166265 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 30357.347604 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23267.605634 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22340.375587 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38309.388458 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29421.166265 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 30357.347604 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 6544 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.184321 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.184321 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.065963 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.094630 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.013326 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.194083 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.084250 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.065963 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.094630 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.013326 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.194083 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.084250 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21781.428571 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 20642.857143 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 42135.927007 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 27314.979085 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 29338.721437 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17673.471476 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17673.471476 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19510.878627 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19510.878627 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 170061.875000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 170061.875000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33833.261348 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 33833.261348 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21781.428571 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 20642.857143 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 42135.927007 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29586.432612 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 30748.102867 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21781.428571 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 20642.857143 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 42135.927007 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29586.432612 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 30748.102867 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 6541 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 99 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 102 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 66.101010 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 64.127451 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 205226 # number of writebacks -system.cpu0.l2cache.writebacks::total 205226 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2290 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 2728 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 5018 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1210 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 1210 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2290 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3938 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 6228 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2290 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3938 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 6228 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 284 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 213 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 13323 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 81005 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 94825 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 445317 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 445317 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 29803 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 29803 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19308 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19308 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.writebacks::writebacks 191905 # number of writebacks +system.cpu0.l2cache.writebacks::total 191905 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 1866 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 2687 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 4553 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1034 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 1034 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 1866 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3721 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 5587 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 1866 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3721 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 5587 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 350 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 252 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 10738 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 74625 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 85965 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 402307 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 402307 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 29431 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 29431 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19057 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19057 # number of SCUpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43701 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 43701 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 284 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 213 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 13323 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 124706 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 138526 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 284 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 213 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 13323 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 124706 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 445317 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 583843 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4618500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3267500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 457593766 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1665461966 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2130941732 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17831693567 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17831693567 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 489548028 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 489548028 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 261537598 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 261537598 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 965995 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 965995 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1080387358 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1080387358 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4618500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3267500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 457593766 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 2745849324 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 3211329090 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4618500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3267500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 457593766 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 2745849324 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17831693567 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 21043022657 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40317 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 40317 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 350 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 252 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 10738 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 114942 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 126282 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 350 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 252 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 10738 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 114942 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 402307 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 528589 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5172000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3438000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 413002773 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1551195475 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1972808248 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16697606620 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16697606620 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 471565864 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 471565864 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 257027175 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 257027175 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1080495 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1080495 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1011507025 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1011507025 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 5172000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3438000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 413002773 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 2562702500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 2984315273 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 5172000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3438000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 413002773 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 2562702500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16697606620 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 19681921893 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 647208500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5328411497 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5975619997 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3986952006 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3986952006 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5320901002 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5968109502 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3975516507 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3975516507 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 647208500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9315363503 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9962572003 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.038645 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.062665 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012549 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.177578 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062036 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9296417509 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9943626009 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.065963 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.094630 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.011353 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.192799 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.064111 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.746942 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.746942 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.903848 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.903848 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.753173 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.753173 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.920761 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.920761 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.169597 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.169597 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.038645 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.062665 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012549 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.174697 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.077552 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.038645 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.062665 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012549 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.174697 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.179712 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.179712 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.065963 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.094630 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.011353 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.187997 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.080680 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.065963 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.094630 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.011353 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.187997 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.326857 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20559.989704 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22472.362056 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40042.696701 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40042.696701 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16426.132537 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16426.132537 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13545.556143 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13545.556143 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 120749.375000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 120749.375000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24722.257111 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24722.257111 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22018.582298 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23182.139743 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22018.582298 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40042.696701 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36042.262487 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.337710 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20786.539028 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22948.970488 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41504.638547 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41504.638547 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16022.760491 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16022.760491 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13487.284200 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13487.284200 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 135061.875000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 135061.875000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 25088.846516 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 25088.846516 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22295.614310 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23632.150845 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22295.614310 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41504.638547 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37234.830640 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1123,57 +1140,57 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1734345 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1628634 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 26254 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26254 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 483361 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 595652 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 80946 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43669 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 101586 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 279437 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 269063 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2141334 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2249028 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9800 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21070 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4421232 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 67981368 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80878536 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13596 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 29396 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 148902896 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 988296 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3215199 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.272128 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.445055 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 1585084 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1436635 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 26190 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 26190 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 420867 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 537670 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 82377 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43315 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 100677 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 246727 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 235853 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1909730 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1979159 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 7030 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 14021 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 3909940 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 60570040 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 70330266 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10652 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21224 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 130932182 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 972661 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2913864 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.296127 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.456548 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2340254 72.79% 72.79% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 874945 27.21% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 2050990 70.39% 70.39% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 862874 29.61% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3215199 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1699304627 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2913864 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1492069922 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115610498 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 116074499 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1603950497 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1150471329 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1430234267 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 995136418 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 6401000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 4367000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 13721750 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 8715750 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -1198,25 +1215,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4826061 # DTB read hits -system.cpu1.dtb.read_misses 2744 # DTB read misses -system.cpu1.dtb.write_hits 4130169 # DTB write hits -system.cpu1.dtb.write_misses 524 # DTB write misses +system.cpu1.dtb.read_hits 6438534 # DTB read hits +system.cpu1.dtb.read_misses 5066 # DTB read misses +system.cpu1.dtb.write_hits 5578600 # DTB write hits +system.cpu1.dtb.write_misses 983 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2012 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 3048 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 437 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 541 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4828805 # DTB read accesses -system.cpu1.dtb.write_accesses 4130693 # DTB write accesses +system.cpu1.dtb.perms_faults 258 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 6443600 # DTB read accesses +system.cpu1.dtb.write_accesses 5579583 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 8956230 # DTB hits -system.cpu1.dtb.misses 3268 # DTB misses -system.cpu1.dtb.accesses 8959498 # DTB accesses +system.cpu1.dtb.hits 12017134 # DTB hits +system.cpu1.dtb.misses 6049 # DTB misses +system.cpu1.dtb.accesses 12023183 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1238,8 +1255,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 20883965 # ITB inst hits -system.cpu1.itb.inst_misses 1747 # ITB inst misses +system.cpu1.itb.inst_hits 28023624 # ITB inst hits +system.cpu1.itb.inst_misses 2794 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1248,178 +1265,179 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1149 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1901 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20885712 # ITB inst accesses -system.cpu1.itb.hits 20883965 # DTB hits -system.cpu1.itb.misses 1747 # DTB misses -system.cpu1.itb.accesses 20885712 # DTB accesses -system.cpu1.numCycles 5732918807 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 28026418 # ITB inst accesses +system.cpu1.itb.hits 28023624 # DTB hits +system.cpu1.itb.misses 2794 # DTB misses +system.cpu1.itb.accesses 28026418 # DTB accesses +system.cpu1.numCycles 5734097031 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 20503191 # Number of instructions committed -system.cpu1.committedOps 24868380 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22184707 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 1209330 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2571856 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22184707 # number of integer instructions -system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 39845208 # number of times the integer registers were read -system.cpu1.num_int_register_writes 15444901 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 90439564 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 8859928 # number of times the CC registers were written -system.cpu1.num_mem_refs 9245671 # number of memory refs -system.cpu1.num_load_insts 4945342 # Number of load instructions -system.cpu1.num_store_insts 4300329 # Number of store instructions -system.cpu1.num_idle_cycles 5671530100.732908 # Number of idle cycles -system.cpu1.num_busy_cycles 61388706.267092 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010708 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989292 # Percentage of idle cycles -system.cpu1.Branches 3891928 # Number of branches fetched -system.cpu1.op_class::No_OpClass 67 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 16013514 63.30% 63.30% # Class of executed instruction -system.cpu1.op_class::IntMult 33536 0.13% 63.44% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4037 0.02% 63.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 63.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.45% # Class of executed instruction -system.cpu1.op_class::MemRead 4945342 19.55% 83.00% # Class of executed instruction -system.cpu1.op_class::MemWrite 4300329 17.00% 100.00% # Class of executed instruction +system.cpu1.committedInsts 27233120 # Number of instructions committed +system.cpu1.committedOps 33143777 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 29468029 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6988 # Number of float alu accesses +system.cpu1.num_func_calls 1518648 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3438745 # number of instructions that are conditional controls +system.cpu1.num_int_insts 29468029 # number of integer instructions +system.cpu1.num_fp_insts 6988 # number of float instructions +system.cpu1.num_int_register_reads 53045981 # number of times the integer registers were read +system.cpu1.num_int_register_writes 20334319 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 5190 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1800 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 119969216 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 12226644 # number of times the CC registers were written +system.cpu1.num_mem_refs 12358568 # number of memory refs +system.cpu1.num_load_insts 6575418 # Number of load instructions +system.cpu1.num_store_insts 5783150 # Number of store instructions +system.cpu1.num_idle_cycles 5655719559.150027 # Number of idle cycles +system.cpu1.num_busy_cycles 78377471.849973 # Number of busy cycles +system.cpu1.not_idle_fraction 0.013669 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.986331 # Percentage of idle cycles +system.cpu1.Branches 5151142 # Number of branches fetched +system.cpu1.op_class::No_OpClass 168 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 21257809 63.16% 63.16% # Class of executed instruction +system.cpu1.op_class::IntMult 38403 0.11% 63.27% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4420 0.01% 63.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 63.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.28% # Class of executed instruction +system.cpu1.op_class::MemRead 6575418 19.54% 82.82% # Class of executed instruction +system.cpu1.op_class::MemWrite 5783150 17.18% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 25296825 # Class of executed instruction +system.cpu1.op_class::total 33659368 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2733 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 218952 # number of replacements -system.cpu1.dcache.tags.tagsinuse 479.963069 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 8650768 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 219309 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 39.445568 # Average number of references to valid blocks. +system.cpu1.kern.inst.quiesce 2818 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 321673 # number of replacements +system.cpu1.dcache.tags.tagsinuse 481.284483 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 11622088 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 322185 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 36.072716 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 104113347000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.963069 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.937428 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.937428 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 357 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 48 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.697266 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 18157371 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 18157371 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 4461777 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 4461777 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3918409 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3918409 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 64134 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 64134 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87180 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 87180 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79638 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 79638 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 8380186 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 8380186 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 8444320 # number of overall hits -system.cpu1.dcache.overall_hits::total 8444320 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 155208 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 155208 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 103786 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 103786 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34227 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 34227 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17933 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17933 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23205 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23205 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 258994 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 258994 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 293221 # number of overall misses -system.cpu1.dcache.overall_misses::total 293221 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2219053526 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2219053526 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2269605832 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2269605832 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325236501 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 325236501 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 538183221 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 538183221 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1673500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1673500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4488659358 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4488659358 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4488659358 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4488659358 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 4616985 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 4616985 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4022195 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4022195 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 98361 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 98361 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105113 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 105113 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102843 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 102843 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 8639180 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 8639180 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 8737541 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 8737541 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033617 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.033617 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025803 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.025803 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.347973 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.347973 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.170607 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.170607 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225635 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225635 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029979 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.029979 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033559 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.033559 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14297.288323 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14297.288323 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21868.130885 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21868.130885 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18136.201472 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18136.201472 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23192.554234 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23192.554234 # average StoreCondReq miss latency +system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.284483 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940009 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.940009 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 24380907 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 24380907 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 5961630 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 5961630 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 5307193 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 5307193 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 82380 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 82380 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 110885 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 110885 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 104150 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 104150 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 11268823 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11268823 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 11351203 # number of overall hits +system.cpu1.dcache.overall_hits::total 11351203 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 210202 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 210202 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 138084 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 138084 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 48251 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 48251 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19527 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 19527 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23870 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23870 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 348286 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 348286 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 396537 # number of overall misses +system.cpu1.dcache.overall_misses::total 396537 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2787267513 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2787267513 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2672172287 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2672172287 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 339794001 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 339794001 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 550321118 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 550321118 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1627000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1627000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 5459439800 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5459439800 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5459439800 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5459439800 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 6171832 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 6171832 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5445277 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5445277 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 130631 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 130631 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 130412 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 130412 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 128020 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 128020 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 11617109 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 11617109 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 11747740 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 11747740 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034058 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.034058 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025358 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.025358 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.369369 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.369369 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149733 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149733 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.186455 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.186455 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029980 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.029980 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033754 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.033754 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13259.947636 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13259.947636 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19351.787948 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 19351.787948 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17401.239361 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17401.239361 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23054.927440 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23054.927440 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17331.132605 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17331.132605 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15308.110122 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15308.110122 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15675.162941 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15675.162941 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13767.794178 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 13767.794178 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1428,84 +1446,82 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 135060 # number of writebacks -system.cpu1.dcache.writebacks::total 135060 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 314 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 314 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12325 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12325 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 315 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 315 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 315 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 315 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154894 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 154894 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103785 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 103785 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33053 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 33053 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5608 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5608 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23205 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23205 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 258679 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 258679 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 291732 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 291732 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1899677974 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1899677974 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2055753168 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2055753168 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 496489496 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 496489496 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84032750 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84032750 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 490566779 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 490566779 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1599500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1599500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3955431142 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3955431142 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4451920638 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4451920638 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 961065499 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 961065499 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 833382997 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 833382997 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1794448496 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1794448496 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033549 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033549 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025803 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025803 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.336038 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.336038 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053352 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053352 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225635 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225635 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029943 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029943 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033388 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033388 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12264.374178 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12264.374178 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19807.806215 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19807.806215 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15021.011587 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15021.011587 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14984.441869 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14984.441869 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21140.563629 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21140.563629 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 197265 # number of writebacks +system.cpu1.dcache.writebacks::total 197265 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 459 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 459 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13505 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13505 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 459 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 459 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 459 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 459 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 209743 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 209743 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 138084 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 138084 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 46648 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 46648 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6022 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6022 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23870 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23870 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 347827 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 347827 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 394475 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394475 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2356483739 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2356483739 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2388185713 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2388185713 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 637646247 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 637646247 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87580250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87580250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 501268882 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 501268882 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1557000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1557000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4744669452 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4744669452 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5382315699 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5382315699 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 968585999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 968585999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 845308497 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 845308497 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1813894496 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1813894496 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033984 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033984 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025358 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025358 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.357097 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.357097 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.046177 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.046177 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.186455 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.186455 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029941 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029941 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033579 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033579 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11235.100761 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11235.100761 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17295.166080 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17295.166080 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13669.315876 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 13669.315876 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14543.382597 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14543.382597 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20999.953163 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20999.953163 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15290.886164 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15290.886164 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15260.309592 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15260.309592 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13640.888867 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13640.888867 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13644.250457 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13644.250457 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1513,58 +1529,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 565004 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.690467 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 20318443 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 565516 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 35.929033 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 680772 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.691095 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 27342334 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 681284 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.133533 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 115083689500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.690467 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974005 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974005 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.691095 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974006 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974006 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 110 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 5 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 42333437 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 42333437 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 20318443 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 20318443 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 20318443 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 20318443 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 20318443 # number of overall hits -system.cpu1.icache.overall_hits::total 20318443 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 565517 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 565517 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 565517 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 565517 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 565517 # number of overall misses -system.cpu1.icache.overall_misses::total 565517 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4683990281 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4683990281 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4683990281 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4683990281 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4683990281 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4683990281 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 20883960 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 20883960 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 20883960 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 20883960 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 20883960 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 20883960 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027079 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.027079 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027079 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.027079 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027079 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.027079 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8282.669276 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8282.669276 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8282.669276 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8282.669276 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8282.669276 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8282.669276 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 56728523 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 56728523 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 27342334 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 27342334 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 27342334 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 27342334 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 27342334 # number of overall hits +system.cpu1.icache.overall_hits::total 27342334 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 681285 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 681285 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 681285 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 681285 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 681285 # number of overall misses +system.cpu1.icache.overall_misses::total 681285 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5656981010 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5656981010 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5656981010 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5656981010 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5656981010 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5656981010 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 28023619 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 28023619 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 28023619 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 28023619 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 28023619 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 28023619 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024311 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024311 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024311 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024311 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024311 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024311 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8303.398739 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8303.398739 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8303.398739 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8303.398739 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8303.398739 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8303.398739 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1573,356 +1589,361 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 565517 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 565517 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 565517 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 565517 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 565517 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 565517 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3835548219 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3835548219 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3835548219 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3835548219 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3835548219 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3835548219 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 681285 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 681285 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 681285 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 681285 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 681285 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 681285 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4634848490 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4634848490 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4634848490 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4634848490 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4634848490 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4634848490 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13880000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13880000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13880000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 13880000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027079 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027079 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027079 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.027079 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027079 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.027079 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6782.374746 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6782.374746 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6782.374746 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6782.374746 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6782.374746 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6782.374746 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024311 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024311 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024311 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024311 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024311 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024311 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6803.097808 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6803.097808 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6803.097808 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6803.097808 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6803.097808 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6803.097808 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4611088 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 22954 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4468812 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 204 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 5735095 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 38649 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 5537320 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 267 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 20 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 119098 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 522488 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 19 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 158840 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 604377 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 85089 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15598.515375 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 830428 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 100250 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 8.283571 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 2855976531500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4729.771122 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.150877 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.487977 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 867.406317 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1520.802657 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8476.896425 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.288682 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000030 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.052942 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.092822 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.517389 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.952058 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9282 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5865 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 69 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1139 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 8074 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 273 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1132 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4460 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.566528 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.357971 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 16688806 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 16688806 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2996 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1704 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 559876 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 123244 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 687820 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 135060 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 135060 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1609 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1609 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 861 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 861 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 39179 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 39179 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2996 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1704 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 559876 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 162423 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 726999 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2996 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1704 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 559876 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 162423 # number of overall hits -system.cpu1.l2cache.overall_hits::total 726999 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 338 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 277 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5641 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 70311 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 76567 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29399 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29399 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22337 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22337 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33598 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 33598 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 338 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 277 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 5641 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 103909 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 110165 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 338 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 277 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 5641 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 103909 # number of overall misses -system.cpu1.l2cache.overall_misses::total 110165 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6952000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5546000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 192723218 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1546712890 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1751934108 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 537154147 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 537154147 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 436854563 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 436854563 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1562500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1562500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1072389357 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1072389357 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6952000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5546000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 192723218 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2619102247 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 2824323465 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6952000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5546000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 192723218 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 2619102247 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 2824323465 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3334 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1981 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 565517 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 193555 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 764387 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 135060 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 135060 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31008 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 31008 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23198 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23198 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 72777 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 72777 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3334 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1981 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 565517 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 266332 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 837164 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3334 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1981 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 565517 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 266332 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 837164 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.101380 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.139828 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009975 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.363261 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.100168 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.948110 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.948110 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.962885 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.962885 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.replacements 130093 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15612.463834 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1076740 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 146334 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 7.358099 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 4806.943324 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.120223 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.343631 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 874.835505 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1500.703163 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8425.517990 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.293393 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000190 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000082 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.053396 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.091596 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.514253 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.952909 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 7913 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 8324 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 47 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 90 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2030 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4783 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 963 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2875 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4662 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 602 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.482971 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.508057 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 21325891 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 21325891 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 5234 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2693 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 672894 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 186024 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 866845 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 197265 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 197265 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2024 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 2024 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1217 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 1217 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 69989 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 69989 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 5234 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2693 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 672894 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 256013 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 936834 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 5234 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2693 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 672894 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 256013 # number of overall hits +system.cpu1.l2cache.overall_hits::total 936834 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 261 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 216 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 8391 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 76389 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 85257 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29955 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 29955 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22648 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22648 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 36116 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 36116 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 261 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 216 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 8391 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 112505 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 121373 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 261 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 216 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 8391 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 112505 # number of overall misses +system.cpu1.l2cache.overall_misses::total 121373 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 5754999 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4668500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 255474477 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1702549656 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 1968447632 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 542491459 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 542491459 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 444517157 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 444517157 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1522000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1522000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1159011538 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1159011538 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 5754999 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4668500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 255474477 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 2861561194 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 3127459170 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 5754999 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4668500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 255474477 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 2861561194 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 3127459170 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 5495 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2909 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 681285 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 262413 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 952102 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 197265 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 197265 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31979 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 31979 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23865 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23865 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 106105 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 106105 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 5495 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2909 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 681285 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 368518 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 1058207 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 5495 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2909 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 681285 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 368518 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 1058207 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.047498 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.074252 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.012316 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.291102 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.089546 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.936708 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.936708 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.949005 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.949005 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.461657 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.461657 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.101380 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.139828 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009975 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.390148 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.131593 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.101380 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.139828 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009975 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.390148 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.131593 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20568.047337 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20021.660650 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34164.725758 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21998.163730 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22881.059830 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18271.170686 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18271.170686 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19557.441151 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19557.441151 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 223214.285714 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 223214.285714 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 31918.249807 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 31918.249807 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20568.047337 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20021.660650 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34164.725758 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25205.730466 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 25637.212046 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20568.047337 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20021.660650 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34164.725758 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25205.730466 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 25637.212046 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 1642 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.340380 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.340380 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.047498 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.074252 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.012316 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.305290 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.114697 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.047498 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.074252 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.012316 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.305290 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.114697 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22049.804598 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21613.425926 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30446.249196 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22287.890351 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23088.398982 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18110.213954 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18110.213954 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19627.214633 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19627.214633 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 304400 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 304400 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 32091.359453 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 32091.359453 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22049.804598 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21613.425926 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30446.249196 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25434.969059 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 25767.338453 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22049.804598 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21613.425926 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30446.249196 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25434.969059 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 25767.338453 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 1081 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 35 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 34 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 46.914286 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 31.794118 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 35198 # number of writebacks -system.cpu1.l2cache.writebacks::total 35198 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 739 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 100 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 839 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 193 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 193 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 739 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 293 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 1032 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 739 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 293 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 1032 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 338 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 277 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4902 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 70211 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 75728 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 119097 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 119097 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29399 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29399 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22337 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22337 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 7 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33405 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 33405 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 338 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 277 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4902 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103616 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 109133 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 338 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 277 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4902 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103616 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 119097 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 228230 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4586000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3607000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 143902025 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1053014200 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1205109225 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3247389638 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3247389638 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 430450689 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 430450689 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306453691 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306453691 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1303500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1303500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 820460623 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 820460623 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4586000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3607000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 143902025 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1873474823 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2025569848 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4586000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3607000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 143902025 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1873474823 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3247389638 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 5272959486 # number of overall MSHR miss cycles +system.cpu1.l2cache.writebacks::writebacks 47807 # number of writebacks +system.cpu1.l2cache.writebacks::total 47807 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1186 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 145 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 1331 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 387 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 387 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1186 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 532 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 1718 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1186 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 532 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 1718 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 261 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 216 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 7205 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 76244 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 83926 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 158839 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 158839 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29955 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29955 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22648 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22648 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35729 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 35729 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 261 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 216 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 7205 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 111973 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 119655 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 261 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 216 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 7205 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 111973 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 158839 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 278494 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 3927001 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3156500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 186017515 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1165742936 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1358843952 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 4336083136 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 4336083136 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 450926825 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 450926825 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 312179089 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 312179089 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1277000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1277000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 867144190 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 867144190 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 3927001 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3156500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 186017515 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2032887126 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2225988142 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 3927001 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3156500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 186017515 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2032887126 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 4336083136 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 6562071278 # number of overall MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12475500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 916023500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 928499000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 796472502 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 796472502 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 923111999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 935587499 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 807820502 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 807820502 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12475500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1712496002 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1724971502 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.101380 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.139828 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.008668 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.362744 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.099070 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1730932501 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1743408001 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.047498 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.074252 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.010576 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.290550 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.088148 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.948110 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.948110 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962885 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962885 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.936708 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.936708 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.949005 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.949005 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.459005 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.459005 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.101380 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.139828 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.008668 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.389048 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130360 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.101380 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.139828 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.008668 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.389048 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.336732 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.336732 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.047498 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.074252 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.010576 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.303847 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.113073 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.047498 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.074252 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.010576 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.303847 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.272623 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14997.852188 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15913.654461 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27266.762706 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27266.762706 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14641.677914 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14641.677914 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13719.554596 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13719.554596 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 186214.285714 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 186214.285714 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24561.012513 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24561.012513 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18080.941389 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18560.562323 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18080.941389 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27266.762706 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23103.708916 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.263175 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 25817.836919 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15289.635066 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16190.977194 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27298.605103 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27298.605103 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15053.474378 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15053.474378 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13783.958363 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13783.958363 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 255400 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 255400 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24270.038064 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24270.038064 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 25817.836919 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18155.154600 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18603.385918 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 25817.836919 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18155.154600 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27298.605103 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23562.702529 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1932,64 +1953,64 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1205511 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 816520 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 4921 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 4921 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 135060 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 171236 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 86319 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42477 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 89729 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 90979 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 78176 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1131388 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 880635 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5306 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9255 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2026584 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 36193796 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 28781627 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7924 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13336 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 64996683 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 818999 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1762052 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.415245 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.492764 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1351518 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1008638 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 4998 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 4998 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 197265 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 224398 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 84264 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42890 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 91097 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 123576 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 111434 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1362924 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1150758 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8243 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16496 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2538421 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 43602948 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 39320783 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11636 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 21980 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 82957347 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 826396 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2054321 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.357816 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.479358 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1030369 58.48% 58.48% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 731683 41.52% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1319253 64.22% 64.22% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 735068 35.78% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1762052 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 658210715 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 2054321 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 864974439 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 89516500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 89802999 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 848574281 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1022245510 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 438678337 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 593726174 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 3325000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 5334000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 5921000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 11001001 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31019 # Transaction distribution -system.iobus.trans_dist::ReadResp 31019 # Transaction distribution -system.iobus.trans_dist::WriteReq 59407 # Transaction distribution -system.iobus.trans_dist::WriteResp 59440 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 33 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 31015 # Transaction distribution +system.iobus.trans_dist::ReadResp 31015 # Transaction distribution +system.iobus.trans_dist::WriteReq 59437 # Transaction distribution +system.iobus.trans_dist::WriteResp 23213 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56642 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -2010,11 +2031,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107964 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107950 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72954 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180918 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71586 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -2035,11 +2056,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162847 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162833 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321256 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484103 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2484089 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40126000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2079,601 +2100,613 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326671825 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347096127 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84748000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84737000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36845580 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36842563 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36443 # number of replacements -system.iocache.tags.tagsinuse 14.446794 # Cycle average of tags in use +system.iocache.tags.replacements 36459 # number of replacements +system.iocache.tags.tagsinuse 14.453181 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36459 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36475 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 277163106000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.446794 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.902925 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.902925 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 277163175000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.453181 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.903324 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.903324 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328557 # Number of tag accesses -system.iocache.tags.data_accesses 328557 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 328293 # Number of tag accesses +system.iocache.tags.data_accesses 328293 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 253 # number of ReadReq misses system.iocache.ReadReq_misses::total 253 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 33 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 33 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 253 # number of demand (read+write) misses system.iocache.demand_misses::total 253 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 253 # number of overall misses system.iocache.overall_misses::total 253 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31609377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31609377 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31609377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31609377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31609377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31609377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 31619377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31619377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9617084187 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9617084187 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31619377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31619377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31619377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31619377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 253 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 253 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36257 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36257 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 253 # number of demand (read+write) accesses system.iocache.demand_accesses::total 253 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 253 # number of overall (read+write) accesses system.iocache.overall_accesses::total 253 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000910 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000910 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124938.249012 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124938.249012 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124938.249012 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124938.249012 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124977.774704 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124977.774704 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265489.294032 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 265489.294032 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124977.774704 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124977.774704 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124977.774704 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124977.774704 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 56586 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7227 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.829805 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 36224 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 36206 # number of writebacks +system.iocache.writebacks::total 36206 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 253 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 253 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 253 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 253 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 253 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 253 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18452377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18452377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2250014028 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2250014028 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18452377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18452377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18452377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18452377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18462377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18462377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7733310313 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7733310313 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18462377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18462377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18462377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18462377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72934.296443 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72934.296443 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72973.822134 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72973.822134 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213485.819153 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213485.819153 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72973.822134 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72973.822134 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72973.822134 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72973.822134 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 132935 # number of replacements -system.l2c.tags.tagsinuse 64217.518730 # Cycle average of tags in use -system.l2c.tags.total_refs 488817 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 197475 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.475336 # Average number of references to valid blocks. +system.l2c.tags.replacements 132552 # number of replacements +system.l2c.tags.tagsinuse 64217.240538 # Cycle average of tags in use +system.l2c.tags.total_refs 486427 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 197317 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.465206 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12771.193603 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.858844 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.037003 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1138.507599 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1415.888274 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38649.791796 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.641656 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007796 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 536.042723 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 904.271560 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8794.277876 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.194873 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 12673.098262 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.830088 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.037001 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1135.719993 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1432.608438 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38719.774998 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.654088 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007784 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 545.091140 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 913.810052 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8789.608693 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.193376 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000074 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.017372 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.021605 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.589749 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.017330 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.021860 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.590817 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000040 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008179 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.013798 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.134190 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.979882 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 44757 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 19776 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 193 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5076 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 39488 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1542 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 18030 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.682938 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.301758 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6143442 # Number of tag accesses -system.l2c.tags.data_accesses 6143442 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 146 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 155 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 10201 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 29439 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 168037 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 53 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 44 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 4112 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 10373 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47653 # number of ReadReq hits -system.l2c.ReadReq_hits::total 270213 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 240423 # number of Writeback hits -system.l2c.Writeback_hits::total 240423 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 9633 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1000 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 10633 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 247 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 137 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 384 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4104 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 2566 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 6670 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 146 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 155 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 10201 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 33543 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 168037 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 53 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 44 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 4112 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 12939 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 47653 # number of demand (read+write) hits -system.l2c.demand_hits::total 276883 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 146 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 155 # number of overall hits -system.l2c.overall_hits::cpu0.inst 10201 # number of overall hits -system.l2c.overall_hits::cpu0.data 33543 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 168037 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 53 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 44 # number of overall hits -system.l2c.overall_hits::cpu1.inst 4112 # number of overall hits -system.l2c.overall_hits::cpu1.data 12939 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 47653 # number of overall hits -system.l2c.overall_hits::total 276883 # number of overall hits +system.l2c.tags.occ_percent::cpu1.inst 0.008317 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.013944 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.134119 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.979877 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 45108 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 19652 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 175 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5031 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 39902 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1352 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 18116 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.688293 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.299866 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6110572 # Number of tag accesses +system.l2c.tags.data_accesses 6110572 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 83 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 80 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 7661 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 21794 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 138574 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 103 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 107 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 6377 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 17292 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 75612 # number of ReadReq hits +system.l2c.ReadReq_hits::total 267683 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 239712 # number of Writeback hits +system.l2c.Writeback_hits::total 239712 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 8881 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1415 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 10296 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 213 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 148 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 361 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 3683 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 2891 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 6574 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 83 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 80 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 7661 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 25477 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 138574 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 103 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 107 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 6377 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 20183 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 75612 # number of demand (read+write) hits +system.l2c.demand_hits::total 274257 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 83 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 80 # number of overall hits +system.l2c.overall_hits::cpu0.inst 7661 # number of overall hits +system.l2c.overall_hits::cpu0.data 25477 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 138574 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 103 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 107 # number of overall hits +system.l2c.overall_hits::cpu1.inst 6377 # number of overall hits +system.l2c.overall_hits::cpu1.data 20183 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 75612 # number of overall hits +system.l2c.overall_hits::total 274257 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 3124 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6991 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 150306 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 3079 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6828 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 144642 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 786 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1400 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21296 # number of ReadReq misses -system.l2c.ReadReq_misses::total 183916 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 8554 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4191 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12745 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 893 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1293 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2186 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 6191 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 5553 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 11744 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 831 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1568 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 26632 # number of ReadReq misses +system.l2c.ReadReq_misses::total 183594 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 7063 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 5704 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 12767 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 818 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1393 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2211 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 6032 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 5664 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 11696 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 3124 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 13182 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 150306 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 3079 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 12860 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 144642 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 786 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6953 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 21296 # number of demand (read+write) misses -system.l2c.demand_misses::total 195660 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 831 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 7232 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 26632 # number of demand (read+write) misses +system.l2c.demand_misses::total 195290 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 3124 # number of overall misses -system.l2c.overall_misses::cpu0.data 13182 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 150306 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu0.inst 3079 # number of overall misses +system.l2c.overall_misses::cpu0.data 12860 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 144642 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 786 # number of overall misses -system.l2c.overall_misses::cpu1.data 6953 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 21296 # number of overall misses -system.l2c.overall_misses::total 195660 # number of overall misses +system.l2c.overall_misses::cpu1.inst 831 # number of overall misses +system.l2c.overall_misses::cpu1.data 7232 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 26632 # number of overall misses +system.l2c.overall_misses::total 195290 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 598250 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 271876998 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 570375499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 15077807020 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 223500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 268856499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 563379750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 14370591021 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 299500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 71055248 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 119227499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2276558323 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18387871837 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 9302615 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 9559091 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 18861706 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1287445 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2175907 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3463352 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 491575637 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 403495431 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 895071068 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 76052499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 131534999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2969532817 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 18380994835 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 5708264 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 12563466 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 18271730 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 936966 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2313401 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 3250367 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 478723658 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 408222395 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 886946053 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 598250 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 271876998 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1061951136 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15077807020 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 223500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 268856499 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1042103408 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14370591021 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 299500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 71055248 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 522722930 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2276558323 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 19282942905 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 76052499 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 539757394 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2969532817 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 19267940888 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 598250 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 271876998 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1061951136 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15077807020 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 223500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 268856499 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1042103408 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14370591021 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 299500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 71055248 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 522722930 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2276558323 # number of overall miss cycles -system.l2c.overall_miss_latency::total 19282942905 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 154 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 156 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 13325 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 36430 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 318343 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 56 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 45 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 4898 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 11773 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 68949 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 454129 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 240423 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 240423 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 18187 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5191 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 23378 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1140 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1430 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2570 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 10295 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 8119 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 18414 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 154 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 156 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 13325 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 46725 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 318343 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 56 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 45 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 4898 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 19892 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 68949 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 472543 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 154 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 156 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 13325 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 46725 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 318343 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 56 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 45 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 4898 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 19892 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 68949 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 472543 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.051948 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.006410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.234447 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.191902 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.472151 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.053571 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.022222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.160474 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.118916 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.308866 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.404986 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.470336 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.807359 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.545171 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.783333 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.904196 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.850584 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.601360 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.683951 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.637776 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.051948 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.006410 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.234447 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.282119 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.472151 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.053571 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.022222 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.160474 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.349538 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.308866 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.414058 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.051948 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.006410 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.234447 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.282119 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.472151 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.053571 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.022222 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.160474 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.349538 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.308866 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.414058 # miss rate for overall accesses +system.l2c.overall_miss_latency::cpu1.inst 76052499 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 539757394 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2969532817 # number of overall miss cycles +system.l2c.overall_miss_latency::total 19267940888 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 91 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 81 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 10740 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 28622 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 283216 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 107 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 108 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 7208 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 18860 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 102244 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 451277 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 239712 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 239712 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 15944 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 7119 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 23063 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 1031 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1541 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2572 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 9715 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 8555 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 18270 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 91 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 81 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 10740 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 38337 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 283216 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 107 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 108 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 7208 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 27415 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 102244 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 469547 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 91 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 81 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 10740 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 38337 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 283216 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 107 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 108 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 7208 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 27415 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 102244 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 469547 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.087912 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.012346 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.286685 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.238558 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.510713 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.037383 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.009259 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.115289 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.083139 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.260475 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.406832 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.442988 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.801236 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.553571 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.793404 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.903958 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.859642 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.620896 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.662069 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.640175 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.087912 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.012346 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.286685 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.335446 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.510713 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.037383 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.009259 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.115289 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.263797 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.260475 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.415912 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.087912 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.012346 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.286685 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.335446 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.510713 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.037383 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.009259 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.115289 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.263797 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.260475 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.415912 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 87028.488476 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 81587.111858 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 100314.072758 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 87319.421565 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 82510.215290 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 99352.822977 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74875 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 90401.078880 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 85162.499286 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 106900.747699 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 99979.728990 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1087.516367 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2280.861608 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1479.929855 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1441.707727 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1682.836040 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1584.333028 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 79401.653529 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72662.602377 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 76215.179496 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 91519.252708 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 83887.116709 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 111502.433801 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 100117.622771 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 808.192553 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2202.571178 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1431.168638 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1145.435208 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1660.732950 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1470.089100 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 79364.001658 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72073.162959 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 75833.280865 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 87028.488476 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 80560.699135 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 100314.072758 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 87319.421565 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 81034.479627 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 99352.822977 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74875 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 90401.078880 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 75179.480800 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 106900.747699 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 98553.321604 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 91519.252708 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 74634.595409 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 111502.433801 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 98663.223350 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 87028.488476 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 80560.699135 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 100314.072758 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 87319.421565 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 81034.479627 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 99352.822977 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74875 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 90401.078880 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 75179.480800 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 106900.747699 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 98553.321604 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 370 # number of cycles access was blocked +system.l2c.overall_avg_miss_latency::cpu1.inst 91519.252708 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 74634.595409 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 111502.433801 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 98663.223350 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 6 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 46.250000 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 99922 # number of writebacks -system.l2c.writebacks::total 99922 # number of writebacks +system.l2c.writebacks::writebacks 99681 # number of writebacks +system.l2c.writebacks::total 99681 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 8 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 3124 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6991 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 150305 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 3079 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6828 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 144641 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 786 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1400 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 21296 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 183915 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 8554 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 4191 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 12745 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 893 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1293 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2186 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 6191 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 5553 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 11744 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 831 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1568 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 26631 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 183592 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 7063 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 5704 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 12767 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 818 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1393 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2211 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 6032 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 5664 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 11696 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 8 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 3124 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 13182 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 150305 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 3079 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 12860 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 144641 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 786 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 6953 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 21296 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 195659 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 831 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 7232 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 26631 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 195288 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 8 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 3124 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 13182 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 150305 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 3079 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 12860 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 144641 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 786 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 6953 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 21296 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 195659 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 831 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 7232 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 26631 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 195288 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 498750 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 233055498 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 483422499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13209375020 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 187500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 230599499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 478526250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12572070021 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 250000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 61295748 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 101745999 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2016216323 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 16105922337 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 86281499 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 42154679 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 128436178 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8967891 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12981791 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 21949682 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 414199861 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 333199069 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 747398930 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 65716499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 111976499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2643305317 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 16103067835 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 71591014 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 57261691 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 128852705 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8313314 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 13970392 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 22283706 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 403342338 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 336523605 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 739865943 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 498750 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 233055498 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 897622360 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13209375020 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 187500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 230599499 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 881868588 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12572070021 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 250000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 61295748 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 434945068 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2016216323 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16853321267 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 65716499 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 448500104 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2643305317 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16842933778 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 498750 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 233055498 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 897622360 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13209375020 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 187500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 230599499 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 881868588 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12572070021 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 250000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 61295748 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 434945068 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2016216323 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16853321267 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 65716499 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 448500104 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2643305317 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16842933778 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 476661000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4796922003 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4790227503 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9143000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 814310000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6097036003 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3540062000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 712612000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4252674000 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 820437000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6096468503 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3529697001 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 722659000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4252356001 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 476661000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8336984003 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8319924504 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9143000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1526922000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 10349710003 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.051948 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.006410 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.234447 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.191902 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.472148 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.053571 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.022222 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.160474 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.118916 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308866 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.404984 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.470336 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.807359 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.545171 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.783333 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.904196 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.850584 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.601360 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.683951 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.637776 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.051948 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.006410 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.234447 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.282119 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.472148 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.053571 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.022222 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.160474 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.349538 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308866 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.414055 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.051948 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.006410 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.234447 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.282119 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.472148 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.053571 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.022222 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.160474 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.349538 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308866 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.414055 # mshr miss rate for overall accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1543096000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10348824504 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.087912 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012346 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.286685 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.238558 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.510709 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.037383 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.009259 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.115289 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083139 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.260465 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.406828 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.442988 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.801236 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.553571 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.793404 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.903958 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.859642 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.620896 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.662069 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.640175 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.087912 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.012346 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.286685 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.335446 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.510709 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.037383 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.009259 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.115289 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.263797 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.260465 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.415907 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.087912 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.012346 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.286685 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.335446 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.510709 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.037383 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.009259 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.115289 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.263797 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.260465 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.415907 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 69149.263196 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74894.283534 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70082.930580 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86919.130959 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72675.713571 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 87572.641367 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10086.684475 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10058.382009 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10077.377638 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.431131 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10040.054911 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10041.025618 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66903.547246 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60003.434000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63640.917064 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 79081.226233 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71413.583546 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 87711.162986 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10136.063146 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10038.865884 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10092.637660 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10162.975550 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10028.996411 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10078.564450 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66867.098475 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59414.478284 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63258.032062 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68094.550144 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74894.283534 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68574.540280 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86919.130959 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62555.022005 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 86136.192391 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 79081.226233 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62016.054204 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 86246.639722 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68094.550144 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74894.283534 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68574.540280 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86919.130959 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62555.022005 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 86136.192391 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 79081.226233 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62016.054204 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 86246.639722 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2688,58 +2721,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 228475 # Transaction distribution -system.membus.trans_dist::ReadResp 228474 # Transaction distribution -system.membus.trans_dist::WriteReq 31175 # Transaction distribution -system.membus.trans_dist::WriteResp 31175 # Transaction distribution -system.membus.trans_dist::Writeback 99922 # Transaction distribution +system.membus.trans_dist::ReadReq 228161 # Transaction distribution +system.membus.trans_dist::ReadResp 228160 # Transaction distribution +system.membus.trans_dist::WriteReq 31188 # Transaction distribution +system.membus.trans_dist::WriteResp 31188 # Transaction distribution +system.membus.trans_dist::Writeback 135887 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 85905 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41202 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15112 # Transaction distribution +system.membus.trans_dist::UpgradeReq 85485 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 41282 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15173 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 28459 # Transaction distribution -system.membus.trans_dist::ReadExResp 11563 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107964 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 28446 # Transaction distribution +system.membus.trans_dist::ReadExResp 11501 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107950 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14554 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 678409 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 800961 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72716 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72716 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 873677 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162847 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14612 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 676793 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 799389 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108922 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108922 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 908311 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162833 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29108 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18962472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19154495 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21473791 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 129134 # Total snoops (count) -system.membus.snoop_fanout::samples 475892 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18898536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19090661 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23727141 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 129157 # Total snoops (count) +system.membus.snoop_fanout::samples 511174 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 475892 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 511174 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 475892 # Request fanout histogram -system.membus.reqLayer0.occupancy 88166996 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 511174 # Request fanout histogram +system.membus.reqLayer0.occupancy 88144997 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12082997 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12118496 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1515063497 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1838586997 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1971064197 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1967573382 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38584420 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38564437 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2772,44 +2805,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 633379 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 633359 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31175 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 240423 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 96357 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41586 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 137943 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 39964 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 39964 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1256968 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 399943 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1656911 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 37604672 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8289023 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45893695 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 305031 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1043713 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.034956 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.183668 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 630354 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 630338 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31188 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31188 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 239712 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 95586 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41643 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 137229 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 39856 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 39856 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1145062 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 504022 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1649084 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 33792786 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 11864019 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45656805 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 304478 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1039135 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.035103 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.184041 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1007229 96.50% 96.50% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36484 3.50% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1002658 96.49% 96.49% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36477 3.51% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1043713 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1520313197 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 1039135 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1515175521 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2134327544 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1922628953 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 850356790 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1047459467 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |