diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-05-10 18:04:29 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-05-10 18:04:29 -0500 |
| commit | e62beaaa8ff9a87bf7523ebb18c5a7559f369eb0 (patch) | |
| tree | c00509eb4c382ab464584ec958f1122bed9bf45c /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual | |
| parent | 0b2d5e20d1ae2373e86786333c8f434583e265d1 (diff) | |
| download | gem5-e62beaaa8ff9a87bf7523ebb18c5a7559f369eb0.tar.xz | |
ARM: update stats for clock frequency fix.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual')
3 files changed, 821 insertions, 827 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index ae01846e4..d6c8fa18c 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:20:58 -gem5 executing on piton +gem5 compiled May 10 2012 12:36:36 +gem5 started May 10 2012 12:36:42 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2669611225000 because m5_exit instruction encountered +Exiting @ tick 1169707043000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 0ac70eccc..4dc707863 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,268 +1,268 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.669611 # Number of seconds simulated -sim_ticks 2669611225000 # Number of ticks simulated -final_tick 2669611225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.169707 # Number of seconds simulated +sim_ticks 1169707043000 # Number of ticks simulated +final_tick 1169707043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 280373 # Simulator instruction rate (inst/s) -host_op_rate 358676 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12211141498 # Simulator tick rate (ticks/s) -host_mem_usage 385748 # Number of bytes of host memory used -host_seconds 218.62 # Real time elapsed on the host -sim_insts 61295282 # Number of instructions simulated -sim_ops 78413979 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 134334820 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1003520 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10194256 # Number of bytes written to this memory -system.physmem.num_reads 15523876 # Number of read requests responded to by this memory -system.physmem.num_writes 869239 # Number of write requests responded to by this memory +host_inst_rate 754175 # Simulator instruction rate (inst/s) +host_op_rate 964493 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14598169556 # Simulator tick rate (ticks/s) +host_mem_usage 379804 # Number of bytes of host memory used +host_seconds 80.13 # Real time elapsed on the host +sim_insts 60429704 # Number of instructions simulated +sim_ops 77281862 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 61898788 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1004992 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10078928 # Number of bytes written to this memory +system.physmem.num_reads 6478591 # Number of read requests responded to by this memory +system.physmem.num_writes 867017 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 50319994 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 375905 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3818629 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 54138623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 52918197 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 859183 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 8616626 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 61534823 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory system.realview.nvmem.num_reads 17 # Number of read requests responded to by this memory system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 127749 # number of replacements -system.l2c.tagsinuse 26172.513447 # Cycle average of tags in use -system.l2c.total_refs 1540413 # Total number of references to valid blocks. -system.l2c.sampled_refs 157158 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.801684 # Average number of references to valid blocks. +system.realview.nvmem.bw_read 58 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read 58 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total 58 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 125934 # number of replacements +system.l2c.tagsinuse 27532.100282 # Cycle average of tags in use +system.l2c.total_refs 1500548 # Total number of references to valid blocks. +system.l2c.sampled_refs 155551 # Sample count of references to valid blocks. +system.l2c.avg_refs 9.646663 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 15197.869082 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 8.069070 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.114155 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2680.486070 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3670.979881 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 0.091092 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.000002 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2441.904061 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2173.000034 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.231901 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000123 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 17789.012398 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 1.363432 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.117594 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 2294.743571 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2778.537805 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 5.252408 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.023319 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2406.434925 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2256.614830 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.271439 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000021 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.040901 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.056015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.035015 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.042397 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000080 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.037260 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.033157 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.399361 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4237 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1502 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 371107 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 191753 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4185 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1874 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 499097 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 157046 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1230801 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 589400 # number of Writeback hits -system.l2c.Writeback_hits::total 589400 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1143 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 692 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1835 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 168 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 186 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 354 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 42506 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58554 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 101060 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4237 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1502 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 371107 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 234259 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4185 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1874 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 499097 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 215600 # number of demand (read+write) hits -system.l2c.demand_hits::total 1331861 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4237 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1502 # number of overall hits -system.l2c.overall_hits::cpu0.inst 371107 # number of overall hits -system.l2c.overall_hits::cpu0.data 234259 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4185 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1874 # number of overall hits -system.l2c.overall_hits::cpu1.inst 499097 # number of overall hits -system.l2c.overall_hits::cpu1.data 215600 # number of overall hits -system.l2c.overall_hits::total 1331861 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 24 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 14 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7728 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 10927 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 8 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 7533 # 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number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1265540 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 589400 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 589400 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 4658 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5915 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10573 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 714 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 800 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1514 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 139830 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 110078 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 249908 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4261 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 1516 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 378835 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 342510 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 4193 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1878 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 506630 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 275625 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1515448 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4261 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 1516 # 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mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.217778 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.005632 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.009235 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.020397 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.316029 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001908 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.002130 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014869 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.217778 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40083.333333 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152864341000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 163150116500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.052112 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.055681 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.797203 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.868377 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.717722 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.700775 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569136 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.605340 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.240912 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.240912 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40067.296493 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40034.893305 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40082.081640 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40266.958715 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40375.955770 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40076.671408 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40153.934520 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40086.080586 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40161.237785 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.479142 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40160.818259 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40083.333333 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40145.524636 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.506205 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40064.881281 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40010.582011 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40075.221239 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40045.653366 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40117.289052 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40067.296493 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40032.722670 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40266.958715 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40191.286964 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40083.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40067.296493 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40032.722670 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40266.958715 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40191.286964 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -446,27 +443,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7857580 # DTB read hits -system.cpu0.dtb.read_misses 1898 # DTB read misses -system.cpu0.dtb.write_hits 6224259 # DTB write hits -system.cpu0.dtb.write_misses 1143 # DTB write misses +system.cpu0.dtb.read_hits 7070142 # DTB read hits +system.cpu0.dtb.read_misses 3739 # DTB read misses +system.cpu0.dtb.write_hits 5655287 # DTB write hits +system.cpu0.dtb.write_misses 802 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1404 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 79 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 191 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7859478 # DTB read accesses -system.cpu0.dtb.write_accesses 6225402 # DTB write accesses +system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7073881 # DTB read accesses +system.cpu0.dtb.write_accesses 5656089 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14081839 # DTB hits -system.cpu0.dtb.misses 3041 # DTB misses -system.cpu0.dtb.accesses 14084880 # DTB accesses -system.cpu0.itb.inst_hits 35747911 # ITB inst hits -system.cpu0.itb.inst_misses 1204 # ITB inst misses +system.cpu0.dtb.hits 12725429 # DTB hits +system.cpu0.dtb.misses 4541 # DTB misses +system.cpu0.dtb.accesses 12729970 # DTB accesses +system.cpu0.itb.inst_hits 29439632 # ITB inst hits +system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -475,80 +472,80 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1262 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 35749115 # ITB inst accesses -system.cpu0.itb.hits 35747911 # DTB hits -system.cpu0.itb.misses 1204 # DTB misses -system.cpu0.itb.accesses 35749115 # DTB accesses -system.cpu0.numCycles 5337805216 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 29441837 # ITB inst accesses +system.cpu0.itb.hits 29439632 # DTB hits +system.cpu0.itb.misses 2205 # DTB misses +system.cpu0.itb.accesses 29441837 # DTB accesses +system.cpu0.numCycles 2339414086 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 35373502 # Number of instructions committed -system.cpu0.committedOps 43969024 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 39881498 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4107 # Number of float alu accesses -system.cpu0.num_func_calls 977479 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4455595 # number of instructions that are conditional controls -system.cpu0.num_int_insts 39881498 # number of integer instructions -system.cpu0.num_fp_insts 4107 # number of float instructions -system.cpu0.num_int_register_reads 225043856 # number of times the integer registers were read -system.cpu0.num_int_register_writes 43158045 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3851 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 256 # number of times the floating registers were written -system.cpu0.num_mem_refs 14677999 # number of memory refs -system.cpu0.num_load_insts 8148547 # Number of load instructions -system.cpu0.num_store_insts 6529452 # Number of store instructions -system.cpu0.num_idle_cycles 5107410767.568501 # Number of idle cycles -system.cpu0.num_busy_cycles 230394448.431500 # Number of busy cycles -system.cpu0.not_idle_fraction 0.043163 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.956837 # Percentage of idle cycles +system.cpu0.committedInsts 28747266 # Number of instructions committed +system.cpu0.committedOps 37085213 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33031535 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses +system.cpu0.num_func_calls 1116936 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4321526 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33031535 # number of integer instructions +system.cpu0.num_fp_insts 3860 # number of float instructions +system.cpu0.num_int_register_reads 189616194 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36089294 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written +system.cpu0.num_mem_refs 13393398 # number of memory refs +system.cpu0.num_load_insts 7407664 # Number of load instructions +system.cpu0.num_store_insts 5985734 # Number of store instructions +system.cpu0.num_idle_cycles 2203122575.338117 # Number of idle cycles +system.cpu0.num_busy_cycles 136291510.661883 # Number of busy cycles +system.cpu0.not_idle_fraction 0.058259 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.941741 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 38525 # number of quiesce instructions executed -system.cpu0.icache.replacements 380070 # number of replacements -system.cpu0.icache.tagsinuse 510.849663 # Cycle average of tags in use -system.cpu0.icache.total_refs 35367310 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 380582 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 92.929539 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 74921716000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.849663 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.997753 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.997753 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 35367310 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 35367310 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 35367310 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 35367310 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 35367310 # number of overall hits -system.cpu0.icache.overall_hits::total 35367310 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 380584 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 380584 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 380584 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 380584 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 380584 # number of overall misses -system.cpu0.icache.overall_misses::total 380584 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5651447000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5651447000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5651447000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5651447000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5651447000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5651447000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 35747894 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 35747894 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 35747894 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 35747894 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 35747894 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 35747894 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010646 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010646 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010646 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14849.407752 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14849.407752 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14849.407752 # average overall miss latency +system.cpu0.kern.inst.quiesce 46688 # number of quiesce instructions executed +system.cpu0.icache.replacements 408172 # number of replacements +system.cpu0.icache.tagsinuse 509.512645 # Cycle average of tags in use +system.cpu0.icache.total_refs 29030930 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 408684 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157159 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157159 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12319714 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12319714 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12319714 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12319714 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033860 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025969 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060456 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047493 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030342 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030342 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15320.382890 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35592.072418 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11039.558127 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9145.766345 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -661,80 +658,77 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 294891 # number of writebacks -system.cpu0.dcache.writebacks::total 294891 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 217330 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 217330 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 155538 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 155538 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9456 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9456 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 8184 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 8184 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 372868 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 372868 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 372868 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 372868 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2678673500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2678673500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5851029000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5851029000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71881000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 71881000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45691000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45691000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8529702500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 8529702500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8529702500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 8529702500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9171180500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9171180500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 40129379500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 40129379500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 49300560000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 49300560000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028424 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029192 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.069410 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.060095 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028739 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028739 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12325.373855 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37618.003318 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7601.628596 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5582.966764 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22875.930624 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22875.930624 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 287163 # number of writebacks +system.cpu0.dcache.writebacks::total 287163 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 231189 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 231189 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 142616 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 142616 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9505 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9505 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7461 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7461 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 373805 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 373805 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 373805 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 373805 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2848236000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2848236000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4648049500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4648049500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 76416000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76416000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45881000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45881000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7496285500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7496285500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7496285500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7496285500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10423748000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10423748000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 822757000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822757000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11246505000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11246505000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033860 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025969 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060456 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047474 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.946018 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32591.360717 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.558127 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6149.443774 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7762498 # DTB read hits -system.cpu1.dtb.read_misses 5432 # DTB read misses -system.cpu1.dtb.write_hits 5411649 # DTB write hits -system.cpu1.dtb.write_misses 1096 # DTB write misses +system.cpu1.dtb.read_hits 8313009 # DTB read hits +system.cpu1.dtb.read_misses 3663 # DTB read misses +system.cpu1.dtb.write_hits 5829499 # DTB write hits +system.cpu1.dtb.write_misses 1439 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2346 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1967 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 166 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 136 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 261 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7767930 # DTB read accesses -system.cpu1.dtb.write_accesses 5412745 # DTB write accesses +system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 8316672 # DTB read accesses +system.cpu1.dtb.write_accesses 5830938 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13174147 # DTB hits -system.cpu1.dtb.misses 6528 # DTB misses -system.cpu1.dtb.accesses 13180675 # DTB accesses -system.cpu1.itb.inst_hits 26848300 # ITB inst hits -system.cpu1.itb.inst_misses 3154 # ITB inst misses +system.cpu1.dtb.hits 14142508 # DTB hits +system.cpu1.dtb.misses 5102 # DTB misses +system.cpu1.dtb.accesses 14147610 # DTB accesses +system.cpu1.itb.inst_hits 32286240 # ITB inst hits +system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -743,80 +737,80 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1544 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 26851454 # ITB inst accesses -system.cpu1.itb.hits 26848300 # DTB hits -system.cpu1.itb.misses 3154 # DTB misses -system.cpu1.itb.accesses 26851454 # DTB accesses -system.cpu1.numCycles 5339222450 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 32288411 # ITB inst accesses +system.cpu1.itb.hits 32286240 # DTB hits +system.cpu1.itb.misses 2171 # DTB misses +system.cpu1.itb.accesses 32288411 # DTB accesses +system.cpu1.numCycles 2338003468 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 25921780 # Number of instructions committed -system.cpu1.committedOps 34444955 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 31033271 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5714 # Number of float alu accesses -system.cpu1.num_func_calls 1093852 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3472619 # number of instructions that are conditional controls -system.cpu1.num_int_insts 31033271 # number of integer instructions -system.cpu1.num_fp_insts 5714 # number of float instructions -system.cpu1.num_int_register_reads 181157292 # number of times the integer registers were read -system.cpu1.num_int_register_writes 32585326 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3770 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1948 # number of times the floating registers were written -system.cpu1.num_mem_refs 13796846 # number of memory refs -system.cpu1.num_load_insts 8139021 # Number of load instructions -system.cpu1.num_store_insts 5657825 # Number of store instructions -system.cpu1.num_idle_cycles 4950307196.068146 # Number of idle cycles -system.cpu1.num_busy_cycles 388915253.931854 # Number of busy cycles -system.cpu1.not_idle_fraction 0.072841 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.927159 # Percentage of idle cycles +system.cpu1.committedInsts 31682438 # Number of instructions committed +system.cpu1.committedOps 40196649 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 36868206 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses +system.cpu1.num_func_calls 909270 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3487065 # number of instructions that are conditional controls +system.cpu1.num_int_insts 36868206 # number of integer instructions +system.cpu1.num_fp_insts 6793 # number of float instructions +system.cpu1.num_int_register_reads 210764243 # number of times the integer registers were read +system.cpu1.num_int_register_writes 38547083 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written +system.cpu1.num_mem_refs 14680299 # number of memory refs +system.cpu1.num_load_insts 8634860 # Number of load instructions +system.cpu1.num_store_insts 6045439 # Number of store instructions +system.cpu1.num_idle_cycles 1858954745.472398 # Number of idle cycles +system.cpu1.num_busy_cycles 479048722.527602 # Number of busy cycles +system.cpu1.not_idle_fraction 0.204896 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.795104 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 53838 # number of quiesce instructions executed -system.cpu1.icache.replacements 508221 # number of replacements -system.cpu1.icache.tagsinuse 497.375159 # Cycle average of tags in use -system.cpu1.icache.total_refs 26339563 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 508733 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 51.774827 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 191336880000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 497.375159 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.971436 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.971436 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 26339563 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 26339563 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 26339563 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 26339563 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 26339563 # number of overall hits -system.cpu1.icache.overall_hits::total 26339563 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 508733 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 508733 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 508733 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 508733 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 508733 # number of overall misses -system.cpu1.icache.overall_misses::total 508733 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7436443000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7436443000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7436443000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7436443000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7436443000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7436443000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 26848296 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 26848296 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 26848296 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 26848296 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 26848296 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 26848296 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018948 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018948 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018948 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14617.575428 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14617.575428 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14617.575428 # average overall miss latency +system.cpu1.kern.inst.quiesce 43911 # number of quiesce instructions executed +system.cpu1.icache.replacements 454317 # number of replacements +system.cpu1.icache.tagsinuse 478.423780 # Cycle average of tags in use +system.cpu1.icache.total_refs 31831407 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 454829 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 69.985438 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 91926225000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 478.423780 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.934421 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.934421 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 31831407 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 31831407 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 31831407 # 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average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -929,50 +923,50 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 253551 # number of writebacks -system.cpu1.dcache.writebacks::total 253551 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 188245 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 188245 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 137493 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 137493 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11557 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11557 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9900 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 9900 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 325738 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 325738 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 325738 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 325738 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2164155000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2164155000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3711466500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3711466500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 97049000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 97049000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 52793000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 52793000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5875621500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5875621500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5875621500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5875621500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137931976000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137931976000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 470527000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 470527000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 138402503000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 138402503000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028812 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025991 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.099328 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085118 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027550 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027550 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11496.480650 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26993.857869 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8397.421476 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5332.626263 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18037.875532 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18037.875532 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 254584 # number of writebacks +system.cpu1.dcache.writebacks::total 254584 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172105 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 172105 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150416 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 150416 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11123 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11123 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9710 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 9710 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 322521 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 322521 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 322521 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 322521 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1979754000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1979754000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4836439500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4836439500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91205500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91205500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44502000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 44502000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6816193500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6816193500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6816193500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6816193500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136553272000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136553272000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39714562000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714562000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176267834000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176267834000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024175 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030209 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119732 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104604 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11503.175387 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32153.756914 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8199.721298 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4583.110196 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency @@ -991,10 +985,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342252853622 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1342252853622 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342252853622 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1342252853622 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550616164273 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 550616164273 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550616164273 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 550616164273 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal Binary files differindex 7e7f32a27..4f02e6414 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal |