stats: updates due to changes to x86, stale configs.

1 files changed, 222 insertions, 48 deletions

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index bfa4aa6e3..a2ee5f35a 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -37,7 +37,7 @@ load_offset=0
 machine_type=RealView_PBX
 mem_mode=timing
 mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
@@ -99,7 +99,7 @@ voltage_domain=system.voltage_domain
 
 [system.cpu0]
 type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
 branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
@@ -136,14 +136,14 @@ icache_port=system.cpu0.icache.cpu_side
 type=BaseCache
 children=tags
 addr_ranges=0:18446744073709551615
-assoc=4
+assoc=2
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
 max_miss_count=0
-mshrs=4
+mshrs=6
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -151,15 +151,15 @@ sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
 two_queue=false
-write_buffers=8
+write_buffers=16
 cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.slave[1]
+mem_side=system.cpu0.toL2Bus.slave[1]
 
 [system.cpu0.dcache.tags]
 type=LRU
-assoc=4
+assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
@@ -189,7 +189,7 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.toL2Bus.slave[5]
+port=system.cpu0.toL2Bus.slave[5]
 
 [system.cpu0.dtb]
 type=ArmTLB
@@ -206,40 +206,40 @@ eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
 sys=system
-port=system.toL2Bus.slave[3]
+port=system.cpu0.toL2Bus.slave[3]
 
 [system.cpu0.icache]
 type=BaseCache
 children=tags
 addr_ranges=0:18446744073709551615
-assoc=1
+assoc=2
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 forward_snoops=true
-hit_latency=2
+hit_latency=1
 is_top_level=true
 max_miss_count=0
-mshrs=4
+mshrs=2
 prefetch_on_access=false
 prefetcher=Null
-response_latency=2
+response_latency=1
 sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.slave[0]
+mem_side=system.cpu0.toL2Bus.slave[0]
 
 [system.cpu0.icache.tags]
 type=LRU
-assoc=1
+assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-hit_latency=2
+hit_latency=1
 sequential_access=false
 size=32768
 
@@ -298,7 +298,7 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.toL2Bus.slave[4]
+port=system.cpu0.toL2Bus.slave[4]
 
 [system.cpu0.itb]
 type=ArmTLB
@@ -315,7 +315,71 @@ eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
 sys=system
-port=system.toL2Bus.slave[2]
+port=system.cpu0.toL2Bus.slave[2]
+
+[system.cpu0.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu0.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu0.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
+[system.cpu0.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu0.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu0.l2cache.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
 
 [system.cpu0.tracer]
 type=ExeTracer
@@ -323,7 +387,7 @@ eventq_index=0
 
 [system.cpu1]
 type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
 branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
@@ -360,14 +424,14 @@ icache_port=system.cpu1.icache.cpu_side
 type=BaseCache
 children=tags
 addr_ranges=0:18446744073709551615
-assoc=4
+assoc=2
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
 max_miss_count=0
-mshrs=4
+mshrs=6
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
@@ -375,15 +439,15 @@ sequential_access=false
 size=32768
 system=system
 tags=system.cpu1.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
 two_queue=false
-write_buffers=8
+write_buffers=16
 cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.slave[7]
+mem_side=system.cpu1.toL2Bus.slave[1]
 
 [system.cpu1.dcache.tags]
 type=LRU
-assoc=4
+assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
@@ -413,7 +477,7 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.toL2Bus.slave[11]
+port=system.cpu1.toL2Bus.slave[5]
 
 [system.cpu1.dtb]
 type=ArmTLB
@@ -430,40 +494,40 @@ eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
 sys=system
-port=system.toL2Bus.slave[9]
+port=system.cpu1.toL2Bus.slave[3]
 
 [system.cpu1.icache]
 type=BaseCache
 children=tags
 addr_ranges=0:18446744073709551615
-assoc=1
+assoc=2
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 forward_snoops=true
-hit_latency=2
+hit_latency=1
 is_top_level=true
 max_miss_count=0
-mshrs=4
+mshrs=2
 prefetch_on_access=false
 prefetcher=Null
-response_latency=2
+response_latency=1
 sequential_access=false
 size=32768
 system=system
 tags=system.cpu1.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.slave[6]
+mem_side=system.cpu1.toL2Bus.slave[0]
 
 [system.cpu1.icache.tags]
 type=LRU
-assoc=1
+assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-hit_latency=2
+hit_latency=1
 sequential_access=false
 size=32768
 
@@ -522,7 +586,7 @@ eventq_index=0
 is_stage2=true
 num_squash_per_cycle=2
 sys=system
-port=system.toL2Bus.slave[10]
+port=system.cpu1.toL2Bus.slave[4]
 
 [system.cpu1.itb]
 type=ArmTLB
@@ -539,7 +603,71 @@ eventq_index=0
 is_stage2=false
 num_squash_per_cycle=2
 sys=system
-port=system.toL2Bus.slave[8]
+port=system.cpu1.toL2Bus.slave[2]
+
+[system.cpu1.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu1.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu1.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu1.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
+[system.cpu1.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu1.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu1.l2cache.cpu_side
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
 
 [system.cpu1.tracer]
 type=ExeTracer
@@ -567,13 +695,13 @@ eventq_index=0
 sys=system
 
 [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
 header_cycles=1
 use_default_range=false
 width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 
 [system.iocache]
@@ -598,7 +726,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
 mem_side=system.membus.slave[2]
 
 [system.iocache.tags]
@@ -647,11 +775,12 @@ sequential_access=false
 size=4194304
 
 [system.membus]
-type=CoherentBus
+type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
 header_cycles=1
+snoop_filter=Null
 system=system
 use_default_range=false
 width=8
@@ -679,8 +808,33 @@ pio=system.membus.default
 
 [system.physmem]
 type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
 activation_limit=4
 addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
 channels=1
@@ -689,6 +843,7 @@ conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
 devices_per_rank=8
+dll=true
 eventq_index=0
 in_addr_map=true
 max_accesses_per_row=16
@@ -702,19 +857,26 @@ read_buffer_size=32
 static_backend_latency=10000
 static_frontend_latency=10000
 tBURST=5000
+tCCD_L=0
 tCK=1250
 tCL=13750
+tCS=2500
 tRAS=35000
 tRCD=13750
 tREFI=7800000
 tRFC=260000
 tRP=13750
 tRRD=6000
+tRRD_L=0
 tRTP=7500
 tRTW=2500
 tWR=15000
 tWTR=7500
 tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
 write_buffer_size=64
 write_high_thresh_perc=85
 write_low_thresh_perc=50
@@ -722,12 +884,12 @@ port=system.membus.master[6]
 
 [system.realview]
 type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
 pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
 system=system
 
 [system.realview.a9scu]
@@ -782,6 +944,7 @@ HeaderType=0
 InterruptLine=31
 InterruptPin=1
 LatencyTimer=0
+LegacyIOBase=0
 MSICAPBaseOffset=0
 MSICAPCapId=0
 MSICAPMaskBits=0
@@ -866,6 +1029,16 @@ pio_latency=100000
 system=system
 pio=system.iobus.master[9]
 
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
 [system.realview.flash_fake]
 type=IsaFake
 clk_domain=system.clk_domain
@@ -1184,15 +1357,16 @@ output=true
 port=3456
 
 [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 header_cycles=1
+snoop_filter=Null
 system=system
 use_default_range=false
 width=8
 master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
 
 [system.vncserver]
 type=VncServer