diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
| commit | 3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0 (patch) | |
| tree | 63ce098bc690eb5b58b3297b747794d623cface4 /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual | |
| parent | af2b14a362281f36347728e13dcd6b2c4d3c4991 (diff) | |
| download | gem5-3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0.tar.xz | |
Stats: Update stats for RAS and LRU fixes.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual')
3 files changed, 913 insertions, 938 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 08257cec9..f78b6a8fb 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -22,6 +22,7 @@ machine_type=RealView_PBX mem_mode=timing memories=system.realview.nvmem system.physmem midr_regval=890224640 +multi_proc=true num_work_ids=16 readfile=tests/halt.sh symbolfile= diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index dc9f6d387..ccc6b6e90 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:26:08 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:37:10 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1169707043000 because m5_exit instruction encountered +Exiting @ tick 1169301297000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index c1f17df29..a92b3a054 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.169707 # Number of seconds simulated -sim_ticks 1169707043000 # Number of ticks simulated -final_tick 1169707043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.169301 # Number of seconds simulated +sim_ticks 1169301297000 # Number of ticks simulated +final_tick 1169301297000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 657704 # Simulator instruction rate (inst/s) -host_op_rate 841119 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12730829062 # Simulator tick rate (ticks/s) -host_mem_usage 382856 # Number of bytes of host memory used -host_seconds 91.88 # Real time elapsed on the host -sim_insts 60429704 # Number of instructions simulated -sim_ops 77281862 # Number of ops (including micro ops) simulated +host_inst_rate 971844 # Simulator instruction rate (inst/s) +host_op_rate 1242825 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18805861990 # Simulator tick rate (ticks/s) +host_mem_usage 384788 # Number of bytes of host memory used +host_seconds 62.18 # Real time elapsed on the host +sim_insts 60426768 # Number of instructions simulated +sim_ops 77275723 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -30,309 +30,291 @@ system.realview.nvmem.bw_total::cpu0.inst 17 # T system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 534756 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5211316 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 470236 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5348464 # Number of bytes read from this memory -system.physmem.bytes_read::total 61898788 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 534756 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 470236 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1004992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7051584 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 394404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4694964 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 322780 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4800816 # Number of bytes read from this memory +system.physmem.bytes_read::total 60545060 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 394404 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 322780 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 717184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4092224 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 10078928 # Number of bytes written to this memory +system.physmem.bytes_written::total 7119568 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14574 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 81499 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7429 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 83596 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6478591 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 110181 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12381 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73431 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5125 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 75039 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6457439 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 63941 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 867017 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43029277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 547 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 457171 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 4455232 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 274 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 402012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4572482 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52918197 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 457171 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 402012 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 859183 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6028504 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14534 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2573588 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8616626 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6028504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43029277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 547 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 457171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 4469765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 274 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 402012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7146070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 61534823 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 125934 # number of replacements -system.l2c.tagsinuse 27532.100282 # Cycle average of tags in use -system.l2c.total_refs 1500548 # Total number of references to valid blocks. -system.l2c.sampled_refs 155551 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.646663 # Average number of references to valid blocks. +system.physmem.num_writes::total 820777 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43044208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 337299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 4015188 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 276045 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4105713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51778836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 337299 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 276045 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 613344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3499717 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14539 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2574481 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6088737 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3499717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43044208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 337299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 4029726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 276045 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6680194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57867573 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 69045 # number of replacements +system.l2c.tagsinuse 52660.415221 # Cycle average of tags in use +system.l2c.total_refs 1684870 # Total number of references to valid blocks. +system.l2c.sampled_refs 134185 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.556321 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 17789.012398 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 1.363432 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.117594 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2294.743571 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2778.537805 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 5.252408 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.023319 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2406.434925 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2256.614830 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.271439 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000021 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.035015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.042397 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000080 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.036719 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.034433 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.420107 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4097 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1763 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 399350 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 205866 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5680 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1949 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 446193 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 140780 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1205678 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 577354 # number of Writeback hits -system.l2c.Writeback_hits::total 577354 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1189 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 549 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1738 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 223 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 193 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 416 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 53827 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 49705 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 103532 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4097 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1763 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 399350 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 259693 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5680 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1949 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 446193 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 190485 # number of demand (read+write) hits -system.l2c.demand_hits::total 1309210 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4097 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1763 # number of overall hits -system.l2c.overall_hits::cpu0.inst 399350 # number of overall hits -system.l2c.overall_hits::cpu0.data 259693 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5680 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1949 # number of overall hits -system.l2c.overall_hits::cpu1.inst 446193 # number of overall hits -system.l2c.overall_hits::cpu1.data 190485 # number of overall hits -system.l2c.overall_hits::total 1309210 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 10 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7942 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 11318 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 18 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 7342 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 8301 # number of ReadReq misses -system.l2c.ReadReq_misses::total 34940 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4674 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3622 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8296 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 567 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 452 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1019 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 71101 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 76239 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 147340 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 10 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7942 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 82419 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 18 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 7342 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 84540 # number of demand (read+write) misses -system.l2c.demand_misses::total 182280 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 10 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40032.260655 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40262.207225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40117.173336 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40083.092535 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -528,26 +498,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7070142 # DTB read hits -system.cpu0.dtb.read_misses 3739 # DTB read misses -system.cpu0.dtb.write_hits 5655287 # DTB write hits -system.cpu0.dtb.write_misses 802 # DTB write misses +system.cpu0.dtb.read_hits 7070010 # DTB read hits +system.cpu0.dtb.read_misses 3742 # DTB read misses +system.cpu0.dtb.write_hits 5655317 # DTB write hits +system.cpu0.dtb.write_misses 808 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1790 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7073881 # DTB read accesses -system.cpu0.dtb.write_accesses 5656089 # DTB write accesses +system.cpu0.dtb.read_accesses 7073752 # DTB read accesses +system.cpu0.dtb.write_accesses 5656125 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12725429 # DTB hits -system.cpu0.dtb.misses 4541 # DTB misses -system.cpu0.dtb.accesses 12729970 # DTB accesses -system.cpu0.itb.inst_hits 29439632 # ITB inst hits +system.cpu0.dtb.hits 12725327 # DTB hits +system.cpu0.dtb.misses 4550 # DTB misses +system.cpu0.dtb.accesses 12729877 # DTB accesses +system.cpu0.itb.inst_hits 29439174 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -564,79 +534,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29441837 # ITB inst accesses -system.cpu0.itb.hits 29439632 # DTB hits +system.cpu0.itb.inst_accesses 29441379 # ITB inst accesses +system.cpu0.itb.hits 29439174 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29441837 # DTB accesses -system.cpu0.numCycles 2339414086 # number of cpu cycles simulated +system.cpu0.itb.accesses 29441379 # DTB accesses +system.cpu0.numCycles 2338602594 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28747266 # Number of instructions committed -system.cpu0.committedOps 37085213 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33031535 # Number of integer alu accesses +system.cpu0.committedInsts 28746820 # Number of instructions committed +system.cpu0.committedOps 37084824 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33031249 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1116936 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4321526 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33031535 # number of integer instructions +system.cpu0.num_func_calls 1241704 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4321371 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33031249 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 189616194 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36089294 # number of times the integer registers were written +system.cpu0.num_int_register_reads 189614137 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36088732 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13393398 # number of memory refs -system.cpu0.num_load_insts 7407664 # Number of load instructions -system.cpu0.num_store_insts 5985734 # Number of store instructions -system.cpu0.num_idle_cycles 2203122575.338117 # Number of idle cycles -system.cpu0.num_busy_cycles 136291510.661883 # Number of busy cycles -system.cpu0.not_idle_fraction 0.058259 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.941741 # Percentage of idle cycles +system.cpu0.num_mem_refs 13393278 # number of memory refs +system.cpu0.num_load_insts 7407523 # Number of load instructions +system.cpu0.num_store_insts 5985755 # Number of store instructions +system.cpu0.num_idle_cycles 2203295398.340116 # Number of idle cycles +system.cpu0.num_busy_cycles 135307195.659884 # Number of busy cycles +system.cpu0.not_idle_fraction 0.057858 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.942142 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46688 # number of quiesce instructions executed -system.cpu0.icache.replacements 408172 # number of replacements -system.cpu0.icache.tagsinuse 509.512645 # Cycle average of tags in use -system.cpu0.icache.total_refs 29030930 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 408684 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 71.035152 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 74928815000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.512645 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995142 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995142 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29030930 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29030930 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29030930 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29030930 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29030930 # number of overall hits -system.cpu0.icache.overall_hits::total 29030930 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 408685 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 408685 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 408685 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 408685 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 408685 # number of overall misses -system.cpu0.icache.overall_misses::total 408685 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6059464500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6059464500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6059464500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6059464500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6059464500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6059464500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29439615 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29439615 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29439615 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29439615 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29439615 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29439615 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013882 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013882 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013882 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013882 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013882 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013882 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14826.735750 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14826.735750 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14826.735750 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14826.735750 # average overall miss latency +system.cpu0.kern.inst.quiesce 46685 # number of quiesce instructions executed +system.cpu0.icache.replacements 408143 # number of replacements +system.cpu0.icache.tagsinuse 509.526052 # Cycle average of tags in use +system.cpu0.icache.total_refs 29030502 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 408655 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 71.039145 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 74905211000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.526052 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995168 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995168 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29030502 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29030502 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29030502 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29030502 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29030502 # number of overall hits +system.cpu0.icache.overall_hits::total 29030502 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 408655 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 408655 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 408655 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 408655 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 408655 # number of overall misses +system.cpu0.icache.overall_misses::total 408655 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5965025000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5965025000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5965025000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5965025000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5965025000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5965025000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29439157 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29439157 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29439157 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29439157 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29439157 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29439157 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013881 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013881 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013881 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013881 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013881 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013881 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14596.725845 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14596.725845 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14596.725845 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14596.725845 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14596.725845 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14596.725845 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -645,122 +615,122 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 16458 # number of writebacks -system.cpu0.icache.writebacks::total 16458 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408685 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 408685 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 408685 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 408685 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 408685 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 408685 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4832163500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4832163500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4832163500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4832163500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4832163500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4832163500 # number of overall MSHR miss cycles +system.cpu0.icache.writebacks::writebacks 20759 # number of writebacks +system.cpu0.icache.writebacks::total 20759 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408655 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 408655 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 408655 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 408655 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 408655 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 408655 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4737808500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4737808500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4737808500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4737808500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4737808500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4737808500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013882 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.013882 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.013882 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11823.686947 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11823.686947 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11823.686947 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013881 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013881 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013881 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11593.663359 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11593.663359 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11593.663359 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11593.663359 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11593.663359 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11593.663359 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 335831 # number of replacements -system.cpu0.dcache.tagsinuse 404.122879 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12265513 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 336343 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 36.467276 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 330129 # number of replacements +system.cpu0.dcache.tagsinuse 459.697251 # Cycle average of tags in use +system.cpu0.dcache.total_refs 12270461 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 330641 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 37.111130 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 404.122879 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.789302 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.789302 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6596660 # 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miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030342 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.030342 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15320.382890 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15320.382890 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35592.072418 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 35592.072418 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11039.558127 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11039.558127 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9145.766345 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9145.766345 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 23054.541807 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 23054.541807 # average overall miss latency +system.cpu0.dcache.occ_blocks::cpu0.data 459.697251 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.897846 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.897846 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6600245 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6600245 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5350394 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5350394 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147923 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147923 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149677 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149677 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11950639 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11950639 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11950639 # number of overall hits +system.cpu0.dcache.overall_hits::total 11950639 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 227470 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 227470 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 141496 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 141496 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9302 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9302 # 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number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68140000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 68140000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8219124000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8219124000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8219124000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8219124000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6827715 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6827715 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5491890 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5491890 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157225 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157225 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157166 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157166 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12319605 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12319605 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12319605 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12319605 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033316 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033316 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025765 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025765 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059164 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059164 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047650 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047650 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029949 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029949 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029949 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029949 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14691.135095 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14691.135095 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34469.748261 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 34469.748261 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10580.251559 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10580.251559 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9098.678061 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9098.678061 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22276.101321 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22276.101321 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22276.101321 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22276.101321 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -769,62 +739,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 287163 # number of writebacks -system.cpu0.dcache.writebacks::total 287163 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 231189 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 231189 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 142616 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 142616 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9505 # 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mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047474 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047474 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.030342 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.030342 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.946018 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12319.946018 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32591.360717 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32591.360717 # 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number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 368966 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2659287000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2659287000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4452739000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4452739000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70511500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 70511500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45688000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45688000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7112026000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7112026000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7112026000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7112026000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10424499500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10424499500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 822589000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822589000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11247088500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11247088500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033316 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033316 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025765 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025765 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059164 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059164 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047618 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047618 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029949 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029949 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029949 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029949 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11690.715259 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11690.715259 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31469.009725 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31469.009725 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7580.251559 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7580.251559 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6104.756815 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6104.756815 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19275.559266 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19275.559266 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19275.559266 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19275.559266 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -834,26 +804,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8313009 # DTB read hits -system.cpu1.dtb.read_misses 3663 # DTB read misses -system.cpu1.dtb.write_hits 5829499 # DTB write hits -system.cpu1.dtb.write_misses 1439 # DTB write misses +system.cpu1.dtb.read_hits 8311514 # DTB read hits +system.cpu1.dtb.read_misses 3660 # DTB read misses +system.cpu1.dtb.write_hits 5828200 # DTB write hits +system.cpu1.dtb.write_misses 1442 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1967 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 136 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8316672 # DTB read accesses -system.cpu1.dtb.write_accesses 5830938 # DTB write accesses +system.cpu1.dtb.read_accesses 8315174 # DTB read accesses +system.cpu1.dtb.write_accesses 5829642 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14142508 # DTB hits +system.cpu1.dtb.hits 14139714 # DTB hits system.cpu1.dtb.misses 5102 # DTB misses -system.cpu1.dtb.accesses 14147610 # DTB accesses -system.cpu1.itb.inst_hits 32286240 # ITB inst hits +system.cpu1.dtb.accesses 14144816 # DTB accesses +system.cpu1.itb.inst_hits 32283727 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -870,79 +840,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 32288411 # ITB inst accesses -system.cpu1.itb.hits 32286240 # DTB hits +system.cpu1.itb.inst_accesses 32285898 # ITB inst accesses +system.cpu1.itb.hits 32283727 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 32288411 # DTB accesses -system.cpu1.numCycles 2338003468 # number of cpu cycles simulated +system.cpu1.itb.accesses 32285898 # DTB accesses +system.cpu1.numCycles 2337184534 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 31682438 # Number of instructions committed -system.cpu1.committedOps 40196649 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 36868206 # Number of integer alu accesses +system.cpu1.committedInsts 31679948 # Number of instructions committed +system.cpu1.committedOps 40190899 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 36862651 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 909270 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3487065 # number of instructions that are conditional controls -system.cpu1.num_int_insts 36868206 # number of integer instructions +system.cpu1.num_func_calls 962114 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3486829 # number of instructions that are conditional controls +system.cpu1.num_int_insts 36862651 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 210764243 # number of times the integer registers were read -system.cpu1.num_int_register_writes 38547083 # number of times the integer registers were written +system.cpu1.num_int_register_reads 210732518 # number of times the integer registers were read +system.cpu1.num_int_register_writes 38542658 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14680299 # number of memory refs -system.cpu1.num_load_insts 8634860 # Number of load instructions -system.cpu1.num_store_insts 6045439 # Number of store instructions -system.cpu1.num_idle_cycles 1858954745.472398 # Number of idle cycles -system.cpu1.num_busy_cycles 479048722.527602 # Number of busy cycles -system.cpu1.not_idle_fraction 0.204896 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.795104 # Percentage of idle cycles +system.cpu1.num_mem_refs 14677413 # number of memory refs +system.cpu1.num_load_insts 8633313 # Number of load instructions +system.cpu1.num_store_insts 6044100 # Number of store instructions +system.cpu1.num_idle_cycles 1859139408.190032 # Number of idle cycles +system.cpu1.num_busy_cycles 478045125.809968 # Number of busy cycles +system.cpu1.not_idle_fraction 0.204539 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.795461 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43911 # number of quiesce instructions executed -system.cpu1.icache.replacements 454317 # number of replacements -system.cpu1.icache.tagsinuse 478.423780 # Cycle average of tags in use -system.cpu1.icache.total_refs 31831407 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 454829 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 69.985438 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 91926225000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.423780 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.934421 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.934421 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 31831407 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 31831407 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 31831407 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 31831407 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 31831407 # number of overall hits -system.cpu1.icache.overall_hits::total 31831407 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 454829 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 454829 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 454829 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 454829 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 454829 # number of overall misses -system.cpu1.icache.overall_misses::total 454829 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6679957000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6679957000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6679957000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6679957000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6679957000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6679957000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 32286236 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 32286236 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 32286236 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 32286236 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 32286236 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 32286236 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014087 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014087 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014087 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014087 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014087 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014087 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14686.743809 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14686.743809 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14686.743809 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14686.743809 # average overall miss latency +system.cpu1.kern.inst.quiesce 43902 # number of quiesce instructions executed +system.cpu1.icache.replacements 454250 # number of replacements +system.cpu1.icache.tagsinuse 478.426272 # Cycle average of tags in use +system.cpu1.icache.total_refs 31828961 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 454762 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 69.990371 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 91827158000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 478.426272 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.934426 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.934426 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 31828961 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 31828961 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 31828961 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 31828961 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 31828961 # number of overall hits +system.cpu1.icache.overall_hits::total 31828961 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 454762 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 454762 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 454762 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 454762 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 454762 # number of overall misses +system.cpu1.icache.overall_misses::total 454762 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6579254500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6579254500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6579254500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6579254500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6579254500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6579254500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 32283723 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 32283723 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 32283723 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 32283723 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 32283723 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 32283723 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014086 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014086 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014086 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014086 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014086 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014086 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14467.467598 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14467.467598 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14467.467598 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14467.467598 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14467.467598 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14467.467598 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -951,122 +921,122 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 19149 # number of writebacks -system.cpu1.icache.writebacks::total 19149 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454829 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 454829 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 454829 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 454829 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 454829 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 454829 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5314262500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5314262500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5314262500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5314262500 # 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number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5213754000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5213754000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5213754000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5213754000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5213754000 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014087 # 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number of cycles access was blocked @@ -1075,62 +1045,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 254584 # number of writebacks -system.cpu1.dcache.writebacks::total 254584 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172105 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 172105 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150416 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 150416 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11123 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11123 # 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number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39714562000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714562000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176267834000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176267834000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024175 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024175 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030209 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030209 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119732 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119732 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104604 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104604 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026659 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026659 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11503.175387 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11503.175387 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32153.756914 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32153.756914 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8199.721298 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8199.721298 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4583.110196 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4583.110196 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21134.107546 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21134.107546 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 265856 # number of writebacks +system.cpu1.dcache.writebacks::total 265856 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170577 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170577 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150060 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 150060 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11061 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11061 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10033 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10033 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320637 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320637 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320637 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320637 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1781497000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1781497000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4669562000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4669562000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68967000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 68967000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 45286000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 45286000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6451059000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6451059000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6451059000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6451059000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136551200000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136551200000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39714194000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714194000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176265394000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176265394000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023966 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023966 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030146 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030146 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119094 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119094 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108106 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108106 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026509 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026509 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026509 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026509 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10443.946136 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10443.946136 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31117.966147 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31117.966147 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6235.150529 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6235.150529 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4513.704774 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4513.704774 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20119.508977 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20119.508977 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20119.508977 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20119.508977 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1152,10 +1126,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550616164273 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 550616164273 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550616164273 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 550616164273 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550273882646 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 550273882646 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550273882646 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 550273882646 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |