diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
| commit | 4646369afd408b486fd3515c35d6c6bbe8960839 (patch) | |
| tree | 0649a2372083956dc573d4b0d56d60c1c15a344c /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual | |
| parent | 4920f0d7e5a4c29ada074bf3a73f36510e138016 (diff) | |
| download | gem5-4646369afd408b486fd3515c35d6c6bbe8960839.tar.xz | |
regressions: update due to cache latency fix
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual')
4 files changed, 947 insertions, 941 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 88cdb89c6..2d5c88739 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -13,7 +13,7 @@ atags_addr=256 boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 -dtb_filename= +dtb_filename=False early_kernel_symbols=false enable_context_switch_stats_dump=false flags_addr=268435504 @@ -378,6 +378,7 @@ children=badaddr_responder block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio @@ -403,25 +404,28 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=true in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false @@ -551,7 +555,7 @@ warn_access= pio=system.iobus.master[24] [system.realview.gic] -type=Gic +type=Pl390 clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 @@ -830,6 +834,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=8 master=system.l2c.cpu_side diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr index e8e271d58..4ccac5e7b 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr @@ -1,6 +1,7 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index 97bbe0010..a21ab0771 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 19:46:40 +gem5 compiled Mar 26 2013 15:15:23 +gem5 started Mar 26 2013 15:15:53 gem5 executing on ribera.cs.wisc.edu command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1182882156500 because m5_exit instruction encountered +Exiting @ tick 1183437503500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 10f005f3e..99dfbb1fa 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,146 +1,146 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.182958 # Number of seconds simulated -sim_ticks 1182958259000 # Number of ticks simulated -final_tick 1182958259000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.183438 # Number of seconds simulated +sim_ticks 1183437503500 # Number of ticks simulated +final_tick 1183437503500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 332432 # Simulator instruction rate (inst/s) -host_op_rate 423606 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6399087906 # Simulator tick rate (ticks/s) -host_mem_usage 408760 # Number of bytes of host memory used -host_seconds 184.86 # Real time elapsed on the host -sim_insts 61454647 # Number of instructions simulated -sim_ops 78309315 # Number of ops (including micro ops) simulated +host_inst_rate 462248 # Simulator instruction rate (inst/s) +host_op_rate 589061 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8900686287 # Simulator tick rate (ticks/s) +host_mem_usage 440324 # Number of bytes of host memory used +host_seconds 132.96 # Real time elapsed on the host +sim_insts 61460532 # Number of instructions simulated +sim_ops 78321652 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4709236 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 393828 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4708980 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4815472 # Number of bytes read from this memory -system.physmem.bytes_read::total 62146212 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.data 4819184 # Number of bytes read from this memory +system.physmem.bytes_read::total 62150116 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 393828 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 716544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4116096 # Number of bytes written to this memory +system.physmem.bytes_inst_read::total 716992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4119552 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7143440 # Number of bytes written to this memory +system.physmem.bytes_written::total 7146896 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73654 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12372 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73650 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75268 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654489 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64314 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 75326 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654550 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64368 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821150 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43876875 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821204 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43859107 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 332539 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3980898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 332783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3979069 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 273183 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4070703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52534577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 332539 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 273183 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 605722 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3479494 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14371 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2544759 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6038624 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3479494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43876875 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 273072 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4072191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52516602 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 332783 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 273072 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 605855 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3481005 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14365 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2543729 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6039099 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3481005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43859107 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 332539 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3995269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 332783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3993434 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 273183 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6615462 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58573201 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654489 # Total number of read requests seen -system.physmem.writeReqs 821150 # Total number of write requests seen -system.physmem.cpureqs 235683 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 425887296 # Total number of bytes read from memory -system.physmem.bytesWritten 52553600 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62146212 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7143440 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 112 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 11769 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 422283 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 415708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 415257 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 415923 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 415836 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 415086 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 415138 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 415982 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 415774 # Track reads on a per bank basis +system.physmem.bw_total::cpu1.inst 273072 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6615920 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58555700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654550 # Total number of read requests seen +system.physmem.writeReqs 821204 # Total number of write requests seen +system.physmem.cpureqs 235817 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 425891200 # Total number of bytes read from memory +system.physmem.bytesWritten 52557056 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62150116 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7146896 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 97 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 11788 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 422295 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 415695 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 415259 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 415928 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 415873 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 415149 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 415167 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 415977 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 415766 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 415145 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 415183 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 415686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 415664 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 415065 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 414968 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 415679 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51312 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50892 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51475 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51354 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50696 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50735 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51449 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51887 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51295 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51778 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51726 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51254 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51118 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51796 # Track writes on a per bank basis +system.physmem.perBankRdReqs::11 415709 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 415657 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 415044 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 414930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 415676 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51328 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50890 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51482 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51387 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50754 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50751 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51440 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51875 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51227 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51302 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51806 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51729 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51213 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51075 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51789 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1182953705000 # Total gap between requests +system.physmem.totGap 1183433014000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6825 # Categorize read packet sizes system.physmem.readPktSize::3 6488064 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159600 # Categorize read packet sizes +system.physmem.readPktSize::6 159661 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 64314 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 571059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 408588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 415867 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1537787 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1165425 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1169620 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1140545 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 29607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 48460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 69110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 48185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 5882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 5724 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 75 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64368 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 571102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 408461 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 415701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1537889 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1165282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1169319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1141412 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 29559 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 48416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 68998 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 48154 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 5894 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 5718 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5372 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 81 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -156,59 +156,59 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35695 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 35695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 20 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 147016739500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 189339617000 # Sum of mem lat for all requests -system.physmem.totBusLat 33271885000 # Total cycles spent in databus access -system.physmem.totBankLat 9050992500 # Total cycles spent in bank access -system.physmem.avgQLat 22093.24 # Average queueing delay per request -system.physmem.avgBankLat 1360.16 # Average bank access latency per request +system.physmem.totQLat 147040385750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 189361608250 # Sum of mem lat for all requests +system.physmem.totBusLat 33272265000 # Total cycles spent in databus access +system.physmem.totBankLat 9048957500 # Total cycles spent in bank access +system.physmem.avgQLat 22096.54 # Average queueing delay per request +system.physmem.avgBankLat 1359.83 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28453.39 # Average memory access latency -system.physmem.avgRdBW 360.02 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 44.43 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 52.53 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 28456.37 # Average memory access latency +system.physmem.avgRdBW 359.88 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 44.41 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 52.52 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 6.04 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.16 # Data bus utilization in percentage system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 12.52 # Average write queue length over time -system.physmem.readRowHits 6612346 # Number of row buffer hits during reads -system.physmem.writeRowHits 800481 # Number of row buffer hits during writes +system.physmem.avgWrQLen 11.75 # Average write queue length over time +system.physmem.readRowHits 6612404 # Number of row buffer hits during reads +system.physmem.writeRowHits 800418 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.48 # Row buffer hit rate for writes -system.physmem.avgGap 158241.15 # Average gap between requests +system.physmem.writeRowHitRate 97.47 # Row buffer hit rate for writes +system.physmem.avgGap 158302.83 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -227,237 +227,237 @@ system.realview.nvmem.bw_inst_read::total 57 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 69480 # number of replacements -system.l2c.tagsinuse 53041.287373 # Cycle average of tags in use -system.l2c.total_refs 1677464 # Total number of references to valid blocks. -system.l2c.sampled_refs 134656 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.457403 # Average number of references to valid blocks. +system.l2c.replacements 69541 # number of replacements +system.l2c.tagsinuse 53035.489918 # Cycle average of tags in use +system.l2c.total_refs 1672596 # Total number of references to valid blocks. +system.l2c.sampled_refs 134740 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.413507 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40190.252096 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 40180.165903 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000406 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001419 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3727.107062 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4236.234020 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.741995 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2823.629298 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2061.321078 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.613255 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.itb.walker 0.001420 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3726.817906 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4242.402809 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 2.742182 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2823.857423 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2059.501869 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.613101 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056871 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.064640 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.056867 # 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number of ReadReq hits -system.l2c.Writeback_hits::writebacks 572264 # number of Writeback hits -system.l2c.Writeback_hits::total 572264 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1120 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 606 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1726 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 216 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 100 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 316 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57066 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 52392 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109458 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 3740 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1661 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 419713 # 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number of Writeback hits +system.l2c.Writeback_hits::total 571448 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1206 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 615 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1821 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 214 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 104 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 318 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 56897 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 52477 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 109374 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 3941 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1769 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 419774 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 262542 # 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mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010751 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.280441 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.106779 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000254 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001129 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013487 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.221957 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010751 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.280441 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.106779 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39765.958828 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40533.525754 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40057.977522 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40843.505784 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42330.200833 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49189.672461 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 42152.750427 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10018.325463 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10025.461902 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10021.418465 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10049.822380 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.648188 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10039.745155 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32136.778001 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34767.810300 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 33505.660228 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42272.657811 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 48989.739983 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 42289.325058 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10024.534578 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10033.376047 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10028.352097 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10033.666078 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10037.524008 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10035.434450 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32591.685499 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34860.480797 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 33772.908934 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39765.958828 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 33018.115387 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40057.977522 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 33458.436773 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42330.200833 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35452.406712 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 34694.074809 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42272.657811 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35529.587312 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 34943.188535 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39765.958828 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33018.115387 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40057.977522 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33458.436773 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42330.200833 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35452.406712 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 34694.074809 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42272.657811 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35529.587312 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 34943.188535 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -641,26 +641,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7073604 # DTB read hits -system.cpu0.dtb.read_misses 3763 # DTB read misses -system.cpu0.dtb.write_hits 5658971 # DTB write hits -system.cpu0.dtb.write_misses 806 # DTB write misses +system.cpu0.dtb.read_hits 7074446 # DTB read hits +system.cpu0.dtb.read_misses 3765 # DTB read misses +system.cpu0.dtb.write_hits 5659669 # DTB write hits +system.cpu0.dtb.write_misses 803 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1806 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7077367 # DTB read accesses -system.cpu0.dtb.write_accesses 5659777 # DTB write accesses +system.cpu0.dtb.read_accesses 7078211 # DTB read accesses +system.cpu0.dtb.write_accesses 5660472 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12732575 # DTB hits -system.cpu0.dtb.misses 4569 # DTB misses -system.cpu0.dtb.accesses 12737144 # DTB accesses -system.cpu0.itb.inst_hits 29573368 # ITB inst hits +system.cpu0.dtb.hits 12734115 # DTB hits +system.cpu0.dtb.misses 4568 # DTB misses +system.cpu0.dtb.accesses 12738683 # DTB accesses +system.cpu0.itb.inst_hits 29576941 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -677,79 +677,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29575573 # ITB inst accesses -system.cpu0.itb.hits 29573368 # DTB hits +system.cpu0.itb.inst_accesses 29579146 # ITB inst accesses +system.cpu0.itb.hits 29576941 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29575573 # DTB accesses -system.cpu0.numCycles 2365916518 # number of cpu cycles simulated +system.cpu0.itb.accesses 29579146 # DTB accesses +system.cpu0.numCycles 2366875007 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28875412 # Number of instructions committed -system.cpu0.committedOps 37222765 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33109279 # Number of integer alu accesses +system.cpu0.committedInsts 28878978 # Number of instructions committed +system.cpu0.committedOps 37226861 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33113061 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241807 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4373656 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33109279 # number of integer instructions +system.cpu0.num_func_calls 1241874 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4373945 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33113061 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 190112848 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36234022 # number of times the integer registers were written +system.cpu0.num_int_register_reads 190134215 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36237784 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13400902 # number of memory refs -system.cpu0.num_load_insts 7411207 # Number of load instructions -system.cpu0.num_store_insts 5989695 # Number of store instructions -system.cpu0.num_idle_cycles 2224988060.360119 # Number of idle cycles -system.cpu0.num_busy_cycles 140928457.639881 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059566 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940434 # Percentage of idle cycles +system.cpu0.num_mem_refs 13402466 # number of memory refs +system.cpu0.num_load_insts 7412077 # Number of load instructions +system.cpu0.num_store_insts 5990389 # Number of store instructions +system.cpu0.num_idle_cycles 2224972760.370120 # Number of idle cycles +system.cpu0.num_busy_cycles 141902246.629880 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059953 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940047 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46697 # number of quiesce instructions executed -system.cpu0.icache.replacements 425482 # number of replacements -system.cpu0.icache.tagsinuse 509.601890 # Cycle average of tags in use -system.cpu0.icache.total_refs 29147356 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 425994 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 68.421987 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 74995953000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.601890 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995316 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995316 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29147356 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29147356 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29147356 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29147356 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29147356 # number of overall hits -system.cpu0.icache.overall_hits::total 29147356 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 425995 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 425995 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 425995 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 425995 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 425995 # number of overall misses -system.cpu0.icache.overall_misses::total 425995 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5809941500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5809941500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5809941500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5809941500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5809941500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5809941500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29573351 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29573351 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29573351 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29573351 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29573351 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29573351 # number of overall (read+write) accesses +system.cpu0.kern.inst.quiesce 46700 # number of quiesce instructions executed +system.cpu0.icache.replacements 425548 # number of replacements +system.cpu0.icache.tagsinuse 509.590371 # Cycle average of tags in use +system.cpu0.icache.total_refs 29150863 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 426060 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 68.419619 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 75070085000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.590371 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995294 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995294 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29150863 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29150863 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29150863 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29150863 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29150863 # number of overall hits +system.cpu0.icache.overall_hits::total 29150863 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 426061 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 426061 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 426061 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 426061 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 426061 # number of overall misses +system.cpu0.icache.overall_misses::total 426061 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5812849500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5812849500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5812849500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5812849500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5812849500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5812849500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29576924 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29576924 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29576924 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29576924 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29576924 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29576924 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014405 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.014405 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014405 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.014405 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014405 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.014405 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13638.520405 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13638.520405 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13638.520405 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13638.520405 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13638.520405 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13638.520405 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13643.233011 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13643.233011 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13643.233011 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13643.233011 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13643.233011 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13643.233011 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -758,18 +758,18 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425995 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 425995 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 425995 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 425995 # 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number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 299599000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 299599000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 299599000 # number of overall MSHR uncacheable cycles @@ -780,98 +780,98 @@ system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014405 system.cpu0.icache.demand_mshr_miss_rate::total 0.014405 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.014405 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11638.520405 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11638.520405 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11638.520405 # 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number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 227474 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 227474 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 141720 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 141720 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9335 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9335 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7505 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7505 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 369194 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 369194 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 369194 # number of overall misses +system.cpu0.dcache.overall_misses::total 369194 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3141338000 # 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number of writebacks -system.cpu0.dcache.writebacks::total 306714 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228068 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 228068 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141674 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141674 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9338 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9338 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7487 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7487 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369742 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 369742 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 369742 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 369742 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2690632000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2690632000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3849543500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3849543500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69909500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69909500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29541500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29541500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 306255 # number of writebacks +system.cpu0.dcache.writebacks::total 306255 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227474 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 227474 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141720 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141720 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9335 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9335 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7498 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7498 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 369194 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 369194 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 369194 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 369194 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2686390000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2686390000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3877797500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3877797500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69967000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69967000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29358500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29358500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6540175500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6540175500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6540175500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6540175500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13562243000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13562243000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128446000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128446000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14690689000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14690689000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033386 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033386 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025780 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025780 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059374 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059374 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047631 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047631 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029995 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029995 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029995 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029995 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11797.498992 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11797.498992 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27171.841693 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27171.841693 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7486.560291 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7486.560291 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3945.705890 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3945.705890 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6564187500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6564187500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6564187500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6564187500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13562288000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13562288000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128633000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128633000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14690921000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14690921000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033295 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033295 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025785 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025785 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059350 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059350 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047695 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047695 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029947 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029947 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029947 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029947 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11809.657367 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11809.657367 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27362.387101 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27362.387101 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7495.125870 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7495.125870 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3915.510803 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3915.510803 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17688.484132 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17688.484132 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17688.484132 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17688.484132 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17779.778382 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17779.778382 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17779.778382 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17779.778382 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -949,26 +949,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8309714 # DTB read hits -system.cpu1.dtb.read_misses 3643 # DTB read misses -system.cpu1.dtb.write_hits 5826503 # DTB write hits -system.cpu1.dtb.write_misses 1435 # DTB write misses +system.cpu1.dtb.read_hits 8312224 # DTB read hits +system.cpu1.dtb.read_misses 3649 # DTB read misses +system.cpu1.dtb.write_hits 5828610 # DTB write hits +system.cpu1.dtb.write_misses 1432 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1964 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8313357 # DTB read accesses -system.cpu1.dtb.write_accesses 5827938 # DTB write accesses +system.cpu1.dtb.read_accesses 8315873 # DTB read accesses +system.cpu1.dtb.write_accesses 5830042 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14136217 # DTB hits -system.cpu1.dtb.misses 5078 # DTB misses -system.cpu1.dtb.accesses 14141295 # DTB accesses -system.cpu1.itb.inst_hits 33189716 # ITB inst hits +system.cpu1.dtb.hits 14140834 # DTB hits +system.cpu1.dtb.misses 5081 # DTB misses +system.cpu1.dtb.accesses 14145915 # DTB accesses +system.cpu1.itb.inst_hits 33192056 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -985,79 +985,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33191887 # ITB inst accesses -system.cpu1.itb.hits 33189716 # DTB hits +system.cpu1.itb.inst_accesses 33194227 # ITB inst accesses +system.cpu1.itb.hits 33192056 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33191887 # DTB accesses -system.cpu1.numCycles 2364475282 # number of cpu cycles simulated +system.cpu1.itb.accesses 33194227 # DTB accesses +system.cpu1.numCycles 2365415230 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32579235 # Number of instructions committed -system.cpu1.committedOps 41086550 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37310899 # Number of integer alu accesses +system.cpu1.committedInsts 32581554 # Number of instructions committed +system.cpu1.committedOps 41094791 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 37318858 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962009 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3732730 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37310899 # number of integer instructions +system.cpu1.num_func_calls 962092 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3732954 # number of instructions that are conditional controls +system.cpu1.num_int_insts 37318858 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 213650265 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39453467 # number of times the integer registers were written +system.cpu1.num_int_register_reads 213696952 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39459665 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14673985 # number of memory refs -system.cpu1.num_load_insts 8631614 # Number of load instructions -system.cpu1.num_store_insts 6042371 # Number of store instructions -system.cpu1.num_idle_cycles 1868339828.826306 # Number of idle cycles -system.cpu1.num_busy_cycles 496135453.173694 # Number of busy cycles -system.cpu1.not_idle_fraction 0.209829 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.790171 # Percentage of idle cycles +system.cpu1.num_mem_refs 14678596 # number of memory refs +system.cpu1.num_load_insts 8634126 # Number of load instructions +system.cpu1.num_store_insts 6044470 # Number of store instructions +system.cpu1.num_idle_cycles 1868274479.951726 # Number of idle cycles +system.cpu1.num_busy_cycles 497140750.048273 # Number of busy cycles +system.cpu1.not_idle_fraction 0.210171 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.789829 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43883 # number of quiesce instructions executed -system.cpu1.icache.replacements 469209 # number of replacements -system.cpu1.icache.tagsinuse 478.755545 # Cycle average of tags in use -system.cpu1.icache.total_refs 32719991 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 469721 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 69.658353 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 92137748500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.755545 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.935069 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.935069 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 32719991 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32719991 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32719991 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32719991 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32719991 # number of overall hits -system.cpu1.icache.overall_hits::total 32719991 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 469721 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 469721 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 469721 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 469721 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 469721 # number of overall misses -system.cpu1.icache.overall_misses::total 469721 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6363755000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6363755000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6363755000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6363755000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6363755000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6363755000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33189712 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33189712 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33189712 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33189712 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33189712 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33189712 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014153 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014153 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014153 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014153 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014153 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014153 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13547.946547 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13547.946547 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13547.946547 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13547.946547 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13547.946547 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13547.946547 # average overall miss latency +system.cpu1.kern.inst.quiesce 43886 # number of quiesce instructions executed +system.cpu1.icache.replacements 469169 # number of replacements +system.cpu1.icache.tagsinuse 478.729775 # Cycle average of tags in use +system.cpu1.icache.total_refs 32722371 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 469681 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 69.669352 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 92399174500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 478.729775 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.935019 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.935019 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 32722371 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 32722371 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 32722371 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 32722371 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 32722371 # number of overall hits +system.cpu1.icache.overall_hits::total 32722371 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 469681 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 469681 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 469681 # 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number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 33192052 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 33192052 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 33192052 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 33192052 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014150 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014150 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014150 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014150 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014150 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014150 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13546.474096 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13546.474096 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13546.474096 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13546.474096 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13546.474096 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13546.474096 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1066,120 +1066,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # 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average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11546.474096 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11546.474096 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11546.474096 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11546.474096 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11546.474096 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # 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number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023965 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.023965 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030123 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030123 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119040 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119040 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108258 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108258 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026500 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026500 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026500 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026500 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12685.855726 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12685.855726 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30246.687472 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 30246.687472 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8344.114720 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8344.114720 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5176.473517 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5176.473517 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20901.158311 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20901.158311 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20901.158311 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20901.158311 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1188,66 +1188,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 265550 # number of writebacks -system.cpu1.dcache.writebacks::total 265550 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170725 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170725 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149867 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 149867 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11052 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11052 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10024 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10024 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 320592 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 320592 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 320592 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 320592 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1826791500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1826791500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4225209000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4225209000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70166500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70166500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31611000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31611000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 265193 # number of writebacks +system.cpu1.dcache.writebacks::total 265193 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170592 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170592 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149961 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 149961 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11053 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11053 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10042 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10042 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320553 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320553 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320553 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320553 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1822921500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1822921500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4235901500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4235901500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70121500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70121500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31910500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31910500 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6052000500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6052000500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6052000500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6052000500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168642802500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168642802500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17668343500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17668343500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186311146000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186311146000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023992 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023992 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030117 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030117 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119082 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119082 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108091 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108091 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026513 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026513 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10700.199151 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10700.199151 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28193.057845 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28193.057845 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6348.760405 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6348.760405 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3153.531524 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3153.531524 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6058823000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6058823000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6058823000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6058823000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168642031500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168642031500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17668268500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17668268500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186310300000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186310300000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023965 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023965 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030123 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030123 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119040 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119040 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108237 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108237 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026500 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026500 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026500 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026500 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10685.855726 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10685.855726 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28246.687472 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28246.687472 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6344.114720 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6344.114720 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3177.703645 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3177.703645 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18877.578043 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18877.578043 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18877.578043 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18877.578043 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18901.158311 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18901.158311 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18901.158311 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18901.158311 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1269,10 +1269,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509685021664 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 509685021664 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509685021664 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 509685021664 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509664351240 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 509664351240 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509664351240 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 509664351240 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |