diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual')
3 files changed, 696 insertions, 648 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 82d6c82a5..73f5e0c76 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,7 +9,6 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver -boot_cpu_frequency=500 boot_loader=/dist/m5/system/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 @@ -19,7 +19,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.physmem system.nvmem +memories=system.nvmem system.physmem midr_regval=890224640 num_work_ids=16 physmem=system.physmem @@ -90,6 +90,7 @@ profile=0 progress_interval=0 system=system tracer=system.cpu0.tracer +workload= dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side @@ -104,20 +105,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -149,20 +143,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -214,6 +201,7 @@ profile=0 progress_interval=0 system=system tracer=system.cpu1.tracer +workload= dcache_port=system.cpu1.dcache.cpu_side icache_port=system.cpu1.icache.cpu_side @@ -228,20 +216,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -273,20 +254,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -338,20 +312,13 @@ is_top_level=false latency=50000 max_miss_count=0 mshrs=20 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=500000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -370,20 +337,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=2 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false @@ -409,7 +369,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.realview ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -451,7 +410,6 @@ system=system type=A9SCU pio_addr=520093696 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[5] @@ -461,7 +419,6 @@ amba_id=0 ignore_access=false pio_addr=268451840 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[24] @@ -531,7 +488,6 @@ max_backoff_delay=10000000 min_backoff_delay=4000 pio_addr=268566528 pio_latency=10000 -platform=system.realview system=system vnc=system.vncserver dma=system.iobus.port[6] @@ -543,7 +499,6 @@ amba_id=0 ignore_access=false pio_addr=268632064 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[12] @@ -553,7 +508,6 @@ fake_mem=true pio_addr=1073741824 pio_latency=1000 pio_size=536870912 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -582,7 +536,6 @@ amba_id=0 ignore_access=false pio_addr=268513280 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[19] @@ -592,7 +545,6 @@ amba_id=0 ignore_access=false pio_addr=268517376 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[20] @@ -602,7 +554,6 @@ amba_id=0 ignore_access=false pio_addr=268521472 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[21] @@ -615,7 +566,6 @@ int_num=52 is_mouse=false pio_addr=268460032 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[7] @@ -629,7 +579,6 @@ int_num=53 is_mouse=true pio_addr=268464128 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[8] @@ -640,7 +589,6 @@ fake_mem=false pio_addr=520101888 pio_latency=1000 pio_size=4095 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -659,7 +607,6 @@ int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[6] @@ -669,7 +616,6 @@ amba_id=0 ignore_access=false pio_addr=268455936 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[25] @@ -678,7 +624,6 @@ type=RealViewCtrl idreg=0 pio_addr=268435456 pio_latency=1000 -platform=system.realview proc_id0=201326592 proc_id1=201327138 system=system @@ -690,7 +635,6 @@ amba_id=266289 ignore_access=false pio_addr=268529664 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[26] @@ -700,7 +644,6 @@ amba_id=0 ignore_access=false pio_addr=268492800 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[23] @@ -710,7 +653,6 @@ amba_id=0 ignore_access=false pio_addr=269357056 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[16] @@ -720,7 +662,6 @@ amba_id=0 ignore_access=true pio_addr=268439552 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[17] @@ -730,7 +671,6 @@ amba_id=0 ignore_access=false pio_addr=268488704 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[22] @@ -744,7 +684,6 @@ int_num0=36 int_num1=36 pio_addr=268505088 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[3] @@ -758,7 +697,6 @@ int_num0=37 int_num1=37 pio_addr=268509184 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[4] @@ -781,7 +719,6 @@ amba_id=0 ignore_access=false pio_addr=268476416 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[13] @@ -791,7 +728,6 @@ amba_id=0 ignore_access=false pio_addr=268480512 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[14] @@ -801,7 +737,6 @@ amba_id=0 ignore_access=false pio_addr=268484608 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[15] @@ -811,7 +746,6 @@ amba_id=0 ignore_access=false pio_addr=268500992 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[18] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index 2f40c0e53..83064ae1d 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:21:22 -gem5 started Jan 23 2012 04:25:02 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:38:22 gem5 executing on zizzer -command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing-dual +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 6f6f084e3..46b5d4b73 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -4,11 +4,13 @@ sim_seconds 2.669611 # Nu sim_ticks 2669611225000 # Number of ticks simulated final_tick 2669611225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 842154 # Simulator instruction rate (inst/s) -host_tick_rate 28671225175 # Simulator tick rate (ticks/s) -host_mem_usage 380676 # Number of bytes of host memory used -host_seconds 93.11 # Real time elapsed on the host -sim_insts 78413959 # Number of instructions simulated +host_inst_rate 868396 # Simulator instruction rate (inst/s) +host_op_rate 1110924 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37821516206 # Simulator tick rate (ticks/s) +host_mem_usage 377896 # Number of bytes of host memory used +host_seconds 70.58 # Real time elapsed on the host +sim_insts 61295262 # Number of instructions simulated +sim_ops 78413959 # Number of ops (including micro ops) simulated system.nvmem.bytes_read 68 # Number of bytes read from this memory system.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory system.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -34,127 +36,233 @@ system.l2c.total_refs 1540412 # To system.l2c.sampled_refs 157158 # Sample count of references to valid blocks. system.l2c.avg_refs 9.801677 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 6351.465954 # Average occupied blocks per context -system.l2c.occ_blocks::1 4614.904109 # Average occupied blocks per context -system.l2c.occ_blocks::2 15206.143377 # Average occupied blocks per context -system.l2c.occ_percent::0 0.096916 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.070418 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.232027 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 562859 # number of ReadReq hits -system.l2c.ReadReq_hits::1 656143 # number of ReadReq hits -system.l2c.ReadReq_hits::2 11798 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 15197.869059 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 8.069070 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.114155 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 2680.486069 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3670.979885 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 0.091092 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.000002 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2441.904066 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2173.000042 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.231901 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000123 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.040901 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.056015 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.037260 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.033157 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.399361 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 4237 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1502 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 371106 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 191753 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 4185 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1874 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 499097 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 157046 # number of ReadReq hits system.l2c.ReadReq_hits::total 1230800 # number of ReadReq hits -system.l2c.Writeback_hits::0 589400 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 589400 # number of Writeback hits system.l2c.Writeback_hits::total 589400 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 1143 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 692 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu0.data 1143 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 692 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 1835 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 168 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 186 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 168 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 186 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 354 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 42506 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 58554 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 42506 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 58554 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 101060 # number of ReadExReq hits -system.l2c.demand_hits::0 605365 # number of demand (read+write) hits -system.l2c.demand_hits::1 714697 # number of demand (read+write) hits -system.l2c.demand_hits::2 11798 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.dtb.walker 4237 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1502 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 371106 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 234259 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 4185 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1874 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 499097 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 215600 # number of demand (read+write) hits system.l2c.demand_hits::total 1331860 # number of demand (read+write) hits -system.l2c.overall_hits::0 605365 # number of overall hits -system.l2c.overall_hits::1 714697 # number of overall hits -system.l2c.overall_hits::2 11798 # number of overall hits +system.l2c.overall_hits::cpu0.dtb.walker 4237 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1502 # number of overall hits +system.l2c.overall_hits::cpu0.inst 371106 # number of overall hits +system.l2c.overall_hits::cpu0.data 234259 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 4185 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1874 # number of overall hits +system.l2c.overall_hits::cpu1.inst 499097 # number of overall hits +system.l2c.overall_hits::cpu1.data 215600 # number of overall hits system.l2c.overall_hits::total 1331860 # number of overall hits -system.l2c.ReadReq_misses::0 18655 # number of ReadReq misses -system.l2c.ReadReq_misses::1 16034 # number of ReadReq misses -system.l2c.ReadReq_misses::2 50 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.dtb.walker 24 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 14 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7728 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 10927 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 8 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 4 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 7533 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 8501 # number of ReadReq misses system.l2c.ReadReq_misses::total 34739 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 3515 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 5223 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 3515 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 5223 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 8738 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 546 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 614 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 546 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 614 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1160 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 97324 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 51524 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 97324 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 51524 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 148848 # number of ReadExReq misses -system.l2c.demand_misses::0 115979 # number of demand (read+write) misses -system.l2c.demand_misses::1 67558 # number of demand (read+write) misses -system.l2c.demand_misses::2 50 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.dtb.walker 24 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 14 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7728 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 108251 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 8 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 4 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 7533 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 60025 # number of demand (read+write) misses system.l2c.demand_misses::total 183587 # number of demand (read+write) misses -system.l2c.overall_misses::0 115979 # number of overall misses -system.l2c.overall_misses::1 67558 # number of overall misses -system.l2c.overall_misses::2 50 # number of overall misses +system.l2c.overall_misses::cpu0.dtb.walker 24 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 14 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7728 # number of overall misses +system.l2c.overall_misses::cpu0.data 108251 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 8 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 4 # number of overall misses +system.l2c.overall_misses::cpu1.inst 7533 # number of overall misses +system.l2c.overall_misses::cpu1.data 60025 # number of overall misses system.l2c.overall_misses::total 183587 # number of overall misses -system.l2c.ReadReq_miss_latency 1812504500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 56471000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency 6300000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7751543000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 9564047500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 9564047500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 581514 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 672177 # number of ReadReq accesses(hits+misses) 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(read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 5632578000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 416000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 208000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 393731000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3132782000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9564047500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 1250500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 728500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 402353500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 5632578000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 416000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 208000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 393731000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3132782000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9564047500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4261 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 1516 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 378834 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 202680 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 4193 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1878 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 506630 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 165547 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1265539 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 589400 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 589400 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 589400 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 4658 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 5915 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 4658 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5915 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 10573 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 714 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 800 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 714 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 800 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1514 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 139830 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 110078 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 139830 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 110078 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 249908 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 721344 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 782255 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 11848 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.dtb.walker 4261 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1516 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 378834 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 342510 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 4193 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1878 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 506630 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 275625 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1515447 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 721344 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 782255 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 11848 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4261 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1516 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 378834 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 342510 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 4193 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1878 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 506630 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 275625 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1515447 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.032080 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.023854 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.004220 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.060154 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.754616 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.883009 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.764706 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.767500 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.696017 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.468068 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.160782 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.086363 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.004220 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.251365 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.160782 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.086363 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.004220 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.251365 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 97159.179845 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 113041.318448 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 36250090 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 36460290.498293 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 16065.718350 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 10811.985449 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 11538.461538 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 10260.586319 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 79646.777773 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 150445.287633 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 82463.614103 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 141567.949022 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 191280950 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 191504981.563124 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 82463.614103 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 141567.949022 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 191280950 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 191504981.563124 # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.005632 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.009235 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.020399 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.053913 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001908 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.002130 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.014869 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.051351 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.754616 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.883009 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.764706 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.767500 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.696017 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.468068 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.005632 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.009235 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.020399 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.316052 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001908 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.002130 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.014869 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.217778 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.005632 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.009235 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.020399 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.316052 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001908 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.002130 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.014869 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.217778 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52104.166667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52035.714286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52064.376294 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52033.403496 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52267.489712 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52375.955770 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 7304.694168 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5896.036760 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3047.619048 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 7550.488599 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52032.479142 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52160.818259 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52104.166667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52035.714286 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52064.376294 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52032.572447 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52267.489712 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52191.286964 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52104.166667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52035.714286 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52064.376294 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52032.572447 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52267.489712 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52191.286964 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -163,61 +271,172 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 111955 # number of writebacks -system.l2c.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 9 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 9 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 34730 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 8738 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 1160 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 148848 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 183578 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 183578 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 1395310000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 350593500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 46546000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5965367000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 7360677000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 7360677000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 131926671000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 31372379500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 163299050500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.059723 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.051668 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 2.931296 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 3.042688 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 1.875912 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 1.477261 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.624650 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.450000 # mshr miss rate for SCUpgradeReq accesses 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0.234678 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 15.494429 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 15.983602 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40175.928592 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40122.854200 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40125.862069 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40076.903956 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40095.637822 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40095.637822 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 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cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 962000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 560000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 309600000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 4333262000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 320000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 160000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 303331000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2412482000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 7360677000 # number of demand (read+write) MSHR miss cycles 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accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.051351 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.754616 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.883009 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.764706 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.767500 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.696017 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.468068 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.005632 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.009235 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.020397 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.316029 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001908 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.002130 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014869 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.217778 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.005632 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.009235 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.020397 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.316029 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001908 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.002130 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014869 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.217778 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40083.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40067.296493 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40034.893305 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40266.958715 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40375.955770 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40076.671408 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40153.934520 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40086.080586 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40161.237785 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.479142 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40160.818259 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40083.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40067.296493 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40032.722670 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40266.958715 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40191.286964 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40083.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40067.296493 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40032.722670 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40266.958715 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40191.286964 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -270,7 +489,8 @@ system.cpu0.itb.accesses 35749115 # DT system.cpu0.numCycles 5337805216 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.num_insts 43969024 # Number of instructions executed +system.cpu0.committedInsts 35373502 # Number of instructions committed +system.cpu0.committedOps 43969024 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 39881498 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4107 # Number of float alu accesses system.cpu0.num_func_calls 977479 # number of times a function call or return occured @@ -296,51 +516,39 @@ system.cpu0.icache.total_refs 35367311 # To system.cpu0.icache.sampled_refs 380581 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 92.929786 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 74921716000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 510.849663 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.997753 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 35367311 # number of ReadReq hits +system.cpu0.icache.occ_blocks::cpu0.inst 510.849663 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.997753 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.997753 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 35367311 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 35367311 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 35367311 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu0.inst 35367311 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 35367311 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 35367311 # number of overall hits -system.cpu0.icache.overall_hits::1 0 # number of overall hits +system.cpu0.icache.overall_hits::cpu0.inst 35367311 # number of overall hits system.cpu0.icache.overall_hits::total 35367311 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 380583 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu0.inst 380583 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 380583 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 380583 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu0.inst 380583 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 380583 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::0 380583 # number of overall misses -system.cpu0.icache.overall_misses::1 0 # number of overall misses +system.cpu0.icache.overall_misses::cpu0.inst 380583 # number of overall misses system.cpu0.icache.overall_misses::total 380583 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 5651439000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 5651439000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 5651439000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::0 35747894 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5651439000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5651439000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5651439000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5651439000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5651439000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5651439000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 35747894 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 35747894 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::0 35747894 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu0.inst 35747894 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 35747894 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::0 35747894 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 35747894 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 35747894 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::0 0.010646 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::0 0.010646 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.010646 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::0 14849.425749 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::0 14849.425749 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 14849.425749 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010646 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010646 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010646 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14849.425749 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14849.425749 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14849.425749 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -349,34 +557,32 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 12960 # number of writebacks -system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 380583 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 380583 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 380583 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 4509188500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 4509188500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 4509188500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency 351814000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency 351814000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.010646 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::0 0.010646 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::0 0.010646 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11848.108034 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11848.108034 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11848.108034 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.writebacks::writebacks 12960 # number of writebacks +system.cpu0.icache.writebacks::total 12960 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 380583 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 380583 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 380583 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 380583 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 380583 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 380583 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4509188500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4509188500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4509188500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4509188500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4509188500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4509188500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010646 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010646 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010646 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11848.108034 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11848.108034 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11848.108034 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 334596 # number of replacements system.cpu0.dcache.tagsinuse 450.118381 # Cycle average of tags in use @@ -384,84 +590,69 @@ system.cpu0.dcache.total_refs 12875674 # To system.cpu0.dcache.sampled_refs 335004 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 38.434389 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 450.118381 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.879137 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::0 7428609 # number of ReadReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 450.118381 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.879137 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.879137 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7428609 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 7428609 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::0 5172633 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5172633 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 5172633 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::0 126778 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 126778 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 126778 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::0 127996 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127996 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 127996 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::0 12601242 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 12601242 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 12601242 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::0 12601242 # number of overall hits -system.cpu0.dcache.overall_hits::1 0 # number of overall hits +system.cpu0.dcache.overall_hits::cpu0.data 12601242 # number of overall hits system.cpu0.dcache.overall_hits::total 12601242 # number of overall hits -system.cpu0.dcache.ReadReq_misses::0 217330 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu0.data 217330 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 217330 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::0 155538 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 155538 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 155538 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::0 9456 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9456 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 9456 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::0 8189 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 8189 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 8189 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::0 372868 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu0.data 372868 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 372868 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::0 372868 # number of overall misses -system.cpu0.dcache.overall_misses::1 0 # number of overall misses +system.cpu0.dcache.overall_misses::cpu0.data 372868 # number of overall misses system.cpu0.dcache.overall_misses::total 372868 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 3330686000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 6317758500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency 100249000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency 70240000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency 9648444500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 9648444500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::0 7645939 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3330686000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3330686000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6317758500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6317758500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100249000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 100249000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 70240000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 70240000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 9648444500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 9648444500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 9648444500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 9648444500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7645939 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 7645939 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::0 5328171 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5328171 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 5328171 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::0 136234 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 136234 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 136234 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::0 136185 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 136185 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 136185 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::0 12974110 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 12974110 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 12974110 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::0 12974110 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12974110 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 12974110 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.028424 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.029192 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.069410 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.060131 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.028739 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.028739 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::0 15325.477385 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::0 40618.745901 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 10601.628596 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 8577.359873 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::0 25876.300728 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 25876.300728 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028424 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.029192 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.069410 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.060131 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028739 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028739 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15325.477385 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40618.745901 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10601.628596 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8577.359873 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25876.300728 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25876.300728 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,56 +661,56 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 294891 # number of writebacks -system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 217330 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 155538 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses 9456 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses 8184 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 372868 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 372868 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 2678673500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 5851029000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 71881000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 45691000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 8529702500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 8529702500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 9171180500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 40129379500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 49300560000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028424 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.029192 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.069410 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.060095 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::0 0.028739 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0.028739 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12325.373855 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 37618.003318 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 7601.628596 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 5582.966764 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 22875.930624 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 22875.930624 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.writebacks::writebacks 294891 # number of writebacks +system.cpu0.dcache.writebacks::total 294891 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 217330 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 217330 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 155538 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 155538 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9456 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9456 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 8184 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 8184 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 372868 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 372868 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 372868 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 372868 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2678673500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2678673500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5851029000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5851029000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71881000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 71881000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45691000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45691000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8529702500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 8529702500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8529702500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 8529702500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9171180500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9171180500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 40129379500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 40129379500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 49300560000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 49300560000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028424 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029192 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.069410 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.060095 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028739 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028739 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12325.373855 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37618.003318 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7601.628596 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5582.966764 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22875.930624 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22875.930624 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses @@ -566,7 +757,8 @@ system.cpu1.itb.accesses 26851434 # DT system.cpu1.numCycles 5339222450 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.num_insts 34444935 # Number of instructions executed +system.cpu1.committedInsts 25921760 # Number of instructions committed +system.cpu1.committedOps 34444935 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 31033253 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5714 # Number of float alu accesses system.cpu1.num_func_calls 1093852 # number of times a function call or return occured @@ -592,51 +784,39 @@ system.cpu1.icache.total_refs 26339543 # To system.cpu1.icache.sampled_refs 508733 # Sample count of references to valid blocks. system.cpu1.icache.avg_refs 51.774788 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 191336880000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 497.375159 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.971436 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 26339543 # number of ReadReq hits +system.cpu1.icache.occ_blocks::cpu1.inst 497.375159 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.971436 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.971436 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 26339543 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 26339543 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 26339543 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::cpu1.inst 26339543 # number of demand (read+write) hits system.cpu1.icache.demand_hits::total 26339543 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 26339543 # number of overall hits -system.cpu1.icache.overall_hits::1 0 # number of overall hits +system.cpu1.icache.overall_hits::cpu1.inst 26339543 # number of overall hits system.cpu1.icache.overall_hits::total 26339543 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 508733 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::cpu1.inst 508733 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 508733 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 508733 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::cpu1.inst 508733 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 508733 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 508733 # number of overall misses -system.cpu1.icache.overall_misses::1 0 # number of overall misses +system.cpu1.icache.overall_misses::cpu1.inst 508733 # number of overall misses system.cpu1.icache.overall_misses::total 508733 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 7436442000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 7436442000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 7436442000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 26848276 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7436442000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7436442000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7436442000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7436442000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7436442000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7436442000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 26848276 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 26848276 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 26848276 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::cpu1.inst 26848276 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::total 26848276 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 26848276 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 26848276 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 26848276 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.018948 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.018948 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.018948 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::0 14617.573462 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::0 14617.573462 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 14617.573462 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018948 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018948 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018948 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14617.573462 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14617.573462 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14617.573462 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -645,34 +825,32 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 27998 # number of writebacks -system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 508733 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 508733 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 508733 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 5908060000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 5908060000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 5908060000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency 5250000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency 5250000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.018948 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::0 0.018948 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0.018948 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11613.282409 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11613.282409 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11613.282409 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.writebacks::writebacks 27998 # number of writebacks +system.cpu1.icache.writebacks::total 27998 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 508733 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 508733 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 508733 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 508733 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 508733 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 508733 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5908060000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5908060000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5908060000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5908060000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5908060000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5908060000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11613.282409 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11613.282409 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11613.282409 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 295754 # number of replacements system.cpu1.dcache.tagsinuse 467.166427 # Cycle average of tags in use @@ -680,84 +858,69 @@ system.cpu1.dcache.total_refs 11737107 # To system.cpu1.dcache.sampled_refs 296266 # Sample count of references to valid blocks. system.cpu1.dcache.avg_refs 39.616787 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 75924171000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 467.166427 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.912434 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 6345290 # number of ReadReq hits +system.cpu1.dcache.occ_blocks::cpu1.data 467.166427 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.912434 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.912434 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 6345290 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 6345290 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 5152610 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 5152610 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 5152610 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 104795 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 104795 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 104795 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::0 106403 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 106403 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 106403 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::0 11497900 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::cpu1.data 11497900 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 11497900 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::0 11497900 # number of overall hits -system.cpu1.dcache.overall_hits::1 0 # number of overall hits +system.cpu1.dcache.overall_hits::cpu1.data 11497900 # number of overall hits system.cpu1.dcache.overall_hits::total 11497900 # number of overall hits -system.cpu1.dcache.ReadReq_misses::0 188245 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::cpu1.data 188245 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 188245 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::0 137493 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 137493 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 137493 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::0 11557 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11557 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 11557 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::0 9906 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9906 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 9906 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::0 325738 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::cpu1.data 325738 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 325738 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::0 325738 # number of overall misses -system.cpu1.dcache.overall_misses::1 0 # number of overall misses +system.cpu1.dcache.overall_misses::cpu1.data 325738 # number of overall misses system.cpu1.dcache.overall_misses::total 325738 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 2729023500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 4123985000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency 131721000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency 82493000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency 6853008500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 6853008500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::0 6533535 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2729023500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2729023500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4123985000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4123985000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131721000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 131721000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 82493000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 82493000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6853008500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6853008500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6853008500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6853008500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 6533535 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 6533535 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::0 5290103 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5290103 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 5290103 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::0 116352 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 116352 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 116352 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::0 116309 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 116309 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 116309 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 11823638 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 11823638 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 11823638 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 11823638 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 11823638 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 11823638 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.028812 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.025991 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.099328 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.085170 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.027550 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.027550 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::0 14497.189832 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::0 29994.145156 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11397.508004 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 8327.579245 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::0 21038.406634 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 21038.406634 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.028812 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025991 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.099328 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.085170 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027550 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027550 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14497.189832 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 29994.145156 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11397.508004 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8327.579245 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21038.406634 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21038.406634 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -766,54 +929,53 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 253551 # number of writebacks -system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 188245 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 137493 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses 11557 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses 9900 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 325738 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 325738 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 2164153000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 3711466500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 97050000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 52793000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 5875619500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 5875619500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 137931975000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 470526000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 138402501000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.028812 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.025991 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.099328 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.085118 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::0 0.027550 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0.027550 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11496.470026 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 26993.857869 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8397.508004 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 5332.626263 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 18037.869392 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 18037.869392 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.writebacks::writebacks 253551 # number of writebacks +system.cpu1.dcache.writebacks::total 253551 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 188245 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 188245 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 137493 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 137493 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11557 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11557 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9900 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 9900 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 325738 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 325738 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 325738 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 325738 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2164153000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2164153000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3711466500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3711466500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 97050000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 97050000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 52793000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 52793000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5875619500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5875619500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5875619500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5875619500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137931975000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137931975000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 470526000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 470526000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 138402501000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 138402501000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028812 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025991 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.099328 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085118 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027550 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027550 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11496.470026 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26993.857869 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8397.508004 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5332.626263 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18037.869392 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18037.869392 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -821,38 +983,6 @@ system.iocache.total_refs 0 # To system.iocache.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.avg_refs no_value # Average number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 0 # number of demand (read+write) misses -system.iocache.demand_misses::total 0 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 0 # number of overall misses -system.iocache.overall_misses::total 0 # number of overall misses -system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -861,28 +991,12 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 0 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 0 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_uncacheable_latency 1342252853622 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency 1342252853622 # number of overall MSHR uncacheable cycles -system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342252853622 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1342252853622 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342252853622 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1342252853622 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |