diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2013-01-07 13:05:54 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2013-01-07 13:05:54 -0500 |
| commit | 9f15510c2c0c346faf107a47486cc06d4921e7c9 (patch) | |
| tree | fab449df2fd9f1a698ce68437efec47e2d45d5f7 /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual | |
| parent | 009970f59b86eac6c9a35eeb175dd9e3a3079d13 (diff) | |
| download | gem5-9f15510c2c0c346faf107a47486cc06d4921e7c9.tar.xz | |
stats: update stats for previous changes.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual')
4 files changed, 1068 insertions, 1048 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index edcbc8719..8e8c112af 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -10,20 +10,21 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/gem5/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 -clock=1 +clock=1000 dtb_filename= early_kernel_symbols=false +enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.physmem system.realview.nvmem -midr_regval=890224640 +mem_ranges=0:134217727 +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -39,7 +40,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 @@ -64,16 +65,15 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/gem5/dist/disks/linux-arm-ael.img read_only=true [system.cpu0] type=TimingSimpleCPU -children=dcache dtb icache interrupts itb tracer +children=dcache dtb icache interrupts isa itb tracer checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -81,6 +81,7 @@ dtb=system.cpu0.dtb function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts +isa=system.cpu0.isa itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -89,6 +90,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +switched_out=false system=system tracer=system.cpu0.tracer workload= @@ -100,23 +102,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=1000 +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port @@ -130,7 +127,7 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -140,23 +137,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=1000 +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port @@ -165,6 +157,23 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.interrupts] type=ArmInterrupts +[system.cpu0.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu0.itb] type=ArmTLB children=walker @@ -173,7 +182,7 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -183,11 +192,10 @@ type=ExeTracer [system.cpu1] type=TimingSimpleCPU -children=dcache dtb icache interrupts itb tracer +children=dcache dtb icache interrupts isa itb tracer checker=Null clock=500 cpu_id=1 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -195,6 +203,7 @@ dtb=system.cpu1.dtb function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts +isa=system.cpu1.isa itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -203,6 +212,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +switched_out=false system=system tracer=system.cpu1.tracer workload= @@ -214,23 +224,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=1000 +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port @@ -244,7 +249,7 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[7] @@ -254,23 +259,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=1000 +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port @@ -279,6 +279,23 @@ mem_side=system.toL2Bus.slave[4] [system.cpu1.interrupts] type=ArmInterrupts +[system.cpu1.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu1.itb] type=ArmTLB children=walker @@ -287,7 +304,7 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[6] @@ -311,57 +328,47 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=BaseCache -addr_ranges=0:268435455 +addr_ranges=0:134217727 assoc=8 block_size=64 -clock=1 +clock=1000 forward_snoops=false -hash_delay=1 -hit_latency=50000 -is_top_level=false +hit_latency=50 +is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=50000 +response_latency=50 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.iobus.master[25] -mem_side=system.membus.slave[1] +mem_side=system.membus.slave[2] [system.l2c] type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=92 +mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=10000 +response_latency=20 size=4194304 -subblock_size=0 system=system -tgts_per_mshr=16 -trace_addr=0 +tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] +mem_side=system.membus.slave[1] [system.membus] type=CoherentBus @@ -373,11 +380,11 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio -slave=system.system_port system.iocache.mem_side system.l2c.mem_side +slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=0 pio_latency=100000 @@ -393,15 +400,28 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=true in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[2] @@ -416,7 +436,7 @@ system=system [system.realview.a9scu] type=A9SCU -clock=1 +clock=1000 pio_addr=520093696 pio_latency=100000 system=system @@ -425,7 +445,7 @@ pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -472,7 +492,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1 +clock=1000 config_latency=20000 ctrl_offset=2 disks=system.cf0 @@ -490,11 +510,12 @@ pio=system.iobus.master[7] [system.realview.clcd] type=Pl111 amba_id=1315089 -clock=41667 +clock=1000 gic=system.realview.gic int_num=55 pio_addr=268566528 pio_latency=10000 +pixel_clock=41667 system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -503,7 +524,7 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -512,7 +533,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -529,7 +550,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic -clock=1 +clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -543,7 +564,7 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -553,7 +574,7 @@ pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -563,7 +584,7 @@ pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -573,7 +594,7 @@ pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -587,7 +608,7 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -600,7 +621,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -629,7 +650,7 @@ pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -639,7 +660,7 @@ pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 @@ -651,7 +672,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl -clock=1 +clock=1000 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -663,7 +684,7 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 -clock=1 +clock=1000 gic=system.realview.gic int_delay=100000 int_num=42 @@ -676,7 +697,7 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -686,7 +707,7 @@ pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -696,7 +717,7 @@ pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -706,7 +727,7 @@ pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -716,7 +737,7 @@ pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -730,7 +751,7 @@ pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -743,7 +764,7 @@ pio=system.iobus.master[3] [system.realview.uart] type=Pl011 -clock=1 +clock=1000 end_on_eot=false gic=system.realview.gic int_delay=100000 @@ -758,7 +779,7 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -768,7 +789,7 @@ pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -778,7 +799,7 @@ pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -788,7 +809,7 @@ pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -805,7 +826,7 @@ port=3456 [system.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false width=8 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr index 04178bb32..e8e271d58 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr @@ -12,7 +12,6 @@ warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index 155c18cca..cecfd8ad7 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 11:19:18 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 4 2013 23:31:36 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1207290627000 because m5_exit instruction encountered +Exiting @ tick 1182882156500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index af19e8e2a..b637311d9 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,122 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.182883 # Number of seconds simulated -sim_ticks 1182883275000 # Number of ticks simulated -final_tick 1182883275000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.182882 # Number of seconds simulated +sim_ticks 1182882156500 # Number of ticks simulated +final_tick 1182882156500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 656929 # Simulator instruction rate (inst/s) -host_op_rate 837075 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12645375755 # Simulator tick rate (ticks/s) -host_mem_usage 400812 # Number of bytes of host memory used -host_seconds 93.54 # Real time elapsed on the host -sim_insts 61450949 # Number of instructions simulated -sim_ops 78302298 # Number of ops (including micro ops) simulated +host_inst_rate 184229 # Simulator instruction rate (inst/s) +host_op_rate 234741 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3546252898 # Simulator tick rate (ticks/s) +host_mem_usage 402168 # Number of bytes of host memory used +host_seconds 333.56 # Real time elapsed on the host +sim_insts 61450993 # Number of instructions simulated +sim_ops 78299715 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4708212 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 393572 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4715764 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4780336 # Number of bytes read from this memory -system.physmem.bytes_read::total 62110052 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.data 4806320 # Number of bytes read from this memory +system.physmem.bytes_read::total 62143780 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 393572 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 716544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4085888 # Number of bytes written to this memory +system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4114688 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7113232 # Number of bytes written to this memory +system.physmem.bytes_written::total 7142032 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73638 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12368 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73756 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74719 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6653924 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 63842 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 75125 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654451 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64292 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 820678 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43879657 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821128 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43879698 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 332560 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3980285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 332723 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3986673 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 273200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4041258 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52507338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 332560 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 273200 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 605761 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3454177 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 273201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4063228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52535901 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 332723 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 273201 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 605923 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3478527 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 14372 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2544921 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6013469 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3454177 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43879657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2544923 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6037822 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3478527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43879698 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 332560 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3994656 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 332723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 4001044 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 273200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6586178 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58520807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6653924 # Total number of read requests seen -system.physmem.writeReqs 820678 # Total number of write requests seen -system.physmem.cpureqs 271841 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 425851136 # Total number of bytes read from memory -system.physmem.bytesWritten 52523392 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62110052 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7113232 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.inst 273201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6608151 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58573723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654451 # Total number of read requests seen +system.physmem.writeReqs 821128 # Total number of write requests seen +system.physmem.cpureqs 272784 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 425884864 # Total number of bytes read from memory +system.physmem.bytesWritten 52552192 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62143780 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7142032 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 132 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 11752 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 415519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 415704 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 11751 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 415571 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 415750 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 415458 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 415464 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 415493 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 415211 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 415304 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 415265 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 422311 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 415383 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 415455 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 415586 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 415355 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 415574 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 415386 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 415468 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 415552 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 415207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 415303 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 415263 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 422360 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 415431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 415464 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 415652 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 415419 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 415645 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 415452 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 415324 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50680 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50792 # Track writes on a per bank basis +system.physmem.perBankWrReqs::0 50727 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50837 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 50611 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50650 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51629 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50656 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51686 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 51413 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51506 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51453 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51654 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51491 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51429 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51462 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51424 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51618 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51455 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51505 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51451 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51696 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51531 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51439 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51528 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51471 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51659 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51507 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 51411 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1182878800500 # Total gap between requests +system.physmem.totGap 1182877668000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6825 # Categorize read packet sizes system.physmem.readPktSize::3 6488064 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159035 # Categorize read packet sizes +system.physmem.readPktSize::6 159562 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -125,7 +143,7 @@ system.physmem.writePktSize::2 756836 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 63842 # categorize write packet sizes +system.physmem.writePktSize::6 64292 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -134,26 +152,26 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 11752 # categorize neither packet sizes +system.physmem.neitherpktsize::6 11751 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 6596894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 41002 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1803 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 662 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 574129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 411417 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 411845 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 427327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1182593 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1193140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2312606 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 25343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15031 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 14611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 14622 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 26114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 14563 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 25574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2767 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 62 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -170,309 +188,291 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3569461684 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 123099843684 # Sum of mem lat for all requests -system.physmem.totBusLat 26615168000 # Total cycles spent in databus access -system.physmem.totBankLat 92915214000 # Total cycles spent in bank access -system.physmem.avgQLat 536.46 # Average queueing delay per request -system.physmem.avgBankLat 13964.25 # Average bank access latency per request +system.physmem.totQLat 123719908904 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 159121708904 # Sum of mem lat for all requests +system.physmem.totBusLat 26617276000 # Total cycles spent in databus access +system.physmem.totBankLat 8784524000 # Total cycles spent in bank access +system.physmem.avgQLat 18592.42 # Average queueing delay per request +system.physmem.avgBankLat 1320.12 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 18500.71 # Average memory access latency -system.physmem.avgRdBW 360.01 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 44.40 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 52.51 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.01 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 23912.55 # Average memory access latency +system.physmem.avgRdBW 360.04 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 44.43 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 52.54 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.04 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # 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average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10037.230277 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10037.287512 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 31770.497729 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34630.548411 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 33256.033393 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 37110.672889 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32833.976067 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36611.750131 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32456.960728 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 38801.841792 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35260.147845 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 34311.151928 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 38247.519826 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35139.235400 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 34046.380963 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 37110.672889 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32833.976067 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36611.750131 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32456.960728 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 38801.841792 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35260.147845 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 34311.151928 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 38247.519826 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35139.235400 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 34046.380963 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -656,26 +656,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7072907 # DTB read hits -system.cpu0.dtb.read_misses 3765 # DTB read misses -system.cpu0.dtb.write_hits 5658426 # DTB write hits -system.cpu0.dtb.write_misses 809 # DTB write misses +system.cpu0.dtb.read_hits 7070111 # DTB read hits +system.cpu0.dtb.read_misses 3764 # DTB read misses +system.cpu0.dtb.write_hits 5656042 # DTB write hits +system.cpu0.dtb.write_misses 804 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7076672 # DTB read accesses -system.cpu0.dtb.write_accesses 5659235 # DTB write accesses +system.cpu0.dtb.read_accesses 7073875 # DTB read accesses +system.cpu0.dtb.write_accesses 5656846 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12731333 # DTB hits -system.cpu0.dtb.misses 4574 # DTB misses -system.cpu0.dtb.accesses 12735907 # DTB accesses -system.cpu0.itb.inst_hits 29570611 # ITB inst hits +system.cpu0.dtb.hits 12726153 # DTB hits +system.cpu0.dtb.misses 4568 # DTB misses +system.cpu0.dtb.accesses 12730721 # DTB accesses +system.cpu0.itb.inst_hits 29570310 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -692,79 +692,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29572816 # ITB inst accesses -system.cpu0.itb.hits 29570611 # DTB hits +system.cpu0.itb.inst_accesses 29572515 # ITB inst accesses +system.cpu0.itb.hits 29570310 # DTB hits system.cpu0.itb.misses 2205 # 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number of instructions that are conditional controls -system.cpu0.num_int_insts 33106294 # number of integer instructions +system.cpu0.num_func_calls 1241715 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4373222 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33098187 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 190095681 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36231150 # number of times the integer registers were written +system.cpu0.num_int_register_reads 190047206 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36225366 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13399479 # 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average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13604.584769 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13604.584769 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13604.584769 # average overall miss latency +system.cpu0.icache.occ_blocks::cpu0.inst 509.616014 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995344 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995344 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29144335 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29144335 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29144335 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29144335 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29144335 # number of overall hits +system.cpu0.icache.overall_hits::total 29144335 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 425958 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 425958 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 425958 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 425958 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 425958 # number of overall misses +system.cpu0.icache.overall_misses::total 425958 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5792188000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5792188000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5792188000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5792188000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5792188000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5792188000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29570293 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29570293 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29570293 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29570293 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29570293 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29570293 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014405 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014405 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014405 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014405 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014405 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014405 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13598.026096 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13598.026096 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13598.026096 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13598.026096 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13598.026096 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13598.026096 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -773,120 +773,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # 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average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014405 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014405 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014405 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11598.026096 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11598.026096 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11598.026096 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11598.026096 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11598.026096 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11598.026096 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 330832 # number of replacements -system.cpu0.dcache.tagsinuse 453.835370 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12275735 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 331344 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.048309 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 330355 # number of replacements +system.cpu0.dcache.tagsinuse 453.331528 # Cycle average of tags in use +system.cpu0.dcache.total_refs 12270860 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 330867 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 37.086987 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 462692000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 453.835370 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.886397 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.886397 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6602660 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6602660 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157172 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 157172 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12325592 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12325592 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12325592 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12325592 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033369 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033369 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025787 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.025787 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059318 # 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average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9464.622642 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9464.622642 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5928.523759 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5928.523759 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19640.712545 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19640.712545 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19640.712545 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 19640.712545 # average overall miss latency +system.cpu0.dcache.demand_misses::cpu0.data 369378 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 369378 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 369378 # 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miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029981 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029981 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029981 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029981 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13736.815543 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13736.815543 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 28999.014239 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 28999.014239 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9459.627997 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9459.627997 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5940.803524 # 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number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2677263500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3843326000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3843326000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69630000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69630000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29442500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29442500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6520589500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6520589500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6520589500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6520589500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13560077000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13560077000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128521500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128521500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14688598500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14688598500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033369 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033369 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025787 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025787 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059318 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059318 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047648 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047648 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029989 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029989 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029989 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029989 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11745.938464 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11745.938464 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27122.595306 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27122.595306 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7464.622642 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7464.622642 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3931.432768 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3931.432768 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_misses::cpu0.data 369378 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 369378 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 369378 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 369378 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2674386000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2674386000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3820765500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3820765500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69382000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69382000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29532500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29532500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6495151500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6495151500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6495151500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6495151500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13561363000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13561363000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128479500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128479500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14689842500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14689842500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033373 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033373 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025764 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025764 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059151 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059151 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047654 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047654 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029981 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029981 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029981 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029981 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11736.815543 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11736.815543 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26999.014239 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26999.014239 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7459.627997 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7459.627997 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3943.450394 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3943.450394 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17640.712545 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17640.712545 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17640.712545 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17640.712545 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17584.023683 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17584.023683 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17584.023683 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17584.023683 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -964,26 +964,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8308581 # DTB read hits +system.cpu1.dtb.read_hits 8310545 # DTB read hits system.cpu1.dtb.read_misses 3643 # DTB read misses -system.cpu1.dtb.write_hits 5825594 # DTB write hits -system.cpu1.dtb.write_misses 1436 # DTB write misses +system.cpu1.dtb.write_hits 5827351 # DTB write hits +system.cpu1.dtb.write_misses 1434 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8312224 # DTB read accesses -system.cpu1.dtb.write_accesses 5827030 # DTB write accesses +system.cpu1.dtb.read_accesses 8314188 # DTB read accesses +system.cpu1.dtb.write_accesses 5828785 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14134175 # DTB hits -system.cpu1.dtb.misses 5079 # DTB misses -system.cpu1.dtb.accesses 14139254 # DTB accesses -system.cpu1.itb.inst_hits 33188757 # ITB inst hits +system.cpu1.dtb.hits 14137896 # DTB hits +system.cpu1.dtb.misses 5077 # DTB misses +system.cpu1.dtb.accesses 14142973 # DTB accesses +system.cpu1.itb.inst_hits 33189113 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1000,79 +1000,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33190928 # ITB inst accesses -system.cpu1.itb.hits 33188757 # DTB hits +system.cpu1.itb.inst_accesses 33191284 # ITB inst accesses +system.cpu1.itb.hits 33189113 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33190928 # DTB accesses -system.cpu1.numCycles 2364324282 # number of cpu cycles simulated +system.cpu1.itb.accesses 33191284 # DTB accesses +system.cpu1.numCycles 2364318212 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32578272 # Number of instructions committed -system.cpu1.committedOps 41082658 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37307259 # Number of integer alu accesses +system.cpu1.committedInsts 32578626 # Number of instructions committed +system.cpu1.committedOps 41088668 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 37313171 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 961975 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3732574 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37307259 # number of integer instructions +system.cpu1.num_func_calls 962009 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3732639 # number of instructions that are conditional controls +system.cpu1.num_int_insts 37313171 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 213628675 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39450611 # number of times the integer registers were written +system.cpu1.num_int_register_reads 213663418 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39454743 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14671912 # number of memory refs -system.cpu1.num_load_insts 8630468 # Number of load instructions -system.cpu1.num_store_insts 6041444 # Number of store instructions -system.cpu1.num_idle_cycles 1868307269.461274 # Number of idle cycles -system.cpu1.num_busy_cycles 496017012.538726 # Number of busy cycles -system.cpu1.not_idle_fraction 0.209792 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.790208 # Percentage of idle cycles +system.cpu1.num_mem_refs 14675641 # number of memory refs +system.cpu1.num_load_insts 8632449 # Number of load instructions +system.cpu1.num_store_insts 6043192 # Number of store instructions +system.cpu1.num_idle_cycles 1868258895.232782 # Number of idle cycles +system.cpu1.num_busy_cycles 496059316.767218 # Number of busy cycles +system.cpu1.not_idle_fraction 0.209811 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.790189 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43897 # number of quiesce instructions executed -system.cpu1.icache.replacements 469210 # number of replacements -system.cpu1.icache.tagsinuse 478.783126 # Cycle average of tags in use -system.cpu1.icache.total_refs 32719031 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 469722 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 69.656160 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 92024110500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.783126 # Average occupied blocks per requestor +system.cpu1.kern.inst.quiesce 43883 # number of quiesce instructions executed +system.cpu1.icache.replacements 469194 # number of replacements +system.cpu1.icache.tagsinuse 478.783096 # Cycle average of tags in use +system.cpu1.icache.total_refs 32719403 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 469706 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 69.659325 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 92023963500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 478.783096 # Average occupied blocks per requestor system.cpu1.icache.occ_percent::cpu1.inst 0.935123 # Average percentage of cache occupancy system.cpu1.icache.occ_percent::total 0.935123 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 32719031 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32719031 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32719031 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32719031 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32719031 # number of overall hits -system.cpu1.icache.overall_hits::total 32719031 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 469722 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 469722 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 469722 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 469722 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 469722 # number of overall misses -system.cpu1.icache.overall_misses::total 469722 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6346616500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6346616500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6346616500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6346616500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6346616500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6346616500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33188753 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33188753 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33188753 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33188753 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33188753 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33188753 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014153 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014153 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014153 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014153 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014153 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014153 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13511.431230 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13511.431230 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13511.431230 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13511.431230 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13511.431230 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13511.431230 # average overall miss latency +system.cpu1.icache.ReadReq_hits::cpu1.inst 32719403 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 32719403 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 32719403 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 32719403 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 32719403 # number of overall hits +system.cpu1.icache.overall_hits::total 32719403 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 469706 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 469706 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 469706 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 469706 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 469706 # number of overall misses +system.cpu1.icache.overall_misses::total 469706 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6343605000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6343605000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6343605000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6343605000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6343605000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6343605000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 33189109 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 33189109 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 33189109 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 33189109 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 33189109 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 33189109 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014152 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014152 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014152 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014152 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014152 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014152 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13505.480024 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13505.480024 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13505.480024 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13505.480024 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13505.480024 # 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miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026496 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026496 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026496 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12604.357388 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12604.357388 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30195.842560 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 30195.842560 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8334.432598 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8334.432598 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5152.327784 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5152.327784 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20834.896813 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20834.896813 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20834.896813 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20834.896813 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1203,66 +1203,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 265120 # number of writebacks -system.cpu1.dcache.writebacks::total 265120 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170295 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170295 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149789 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 149789 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11069 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11069 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10028 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10028 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 320084 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 320084 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 320084 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 320084 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1810577000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1810577000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4218979500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4218979500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 69863000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 69863000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31600000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31600000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 265102 # number of writebacks +system.cpu1.dcache.writebacks::total 265102 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170515 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170515 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149924 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 149924 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11068 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11068 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10026 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10026 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320439 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320439 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320439 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320439 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1808202000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1808202000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4227233500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4227233500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70109500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70109500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31633000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31633000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6029556500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6029556500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6029556500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6029556500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168626695000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168626695000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17666887000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17666887000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186293582000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186293582000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023936 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023936 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030107 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030107 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119237 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119237 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108126 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108126 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026475 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026475 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026475 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026475 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10632.003288 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10632.003288 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28166.150385 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28166.150385 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6311.590930 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6311.590930 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3151.176705 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3151.176705 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6035435500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6035435500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6035435500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6035435500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168635770000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168635770000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17673871500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17673871500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186309641500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186309641500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023960 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023960 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030123 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030123 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119242 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119242 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108103 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108103 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026496 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026496 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026496 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026496 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10604.357388 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10604.357388 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28195.842560 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28195.842560 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6334.432598 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6334.432598 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3155.096748 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3155.096748 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18837.419240 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18837.419240 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18837.419240 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18837.419240 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18834.896813 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18834.896813 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18834.896813 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18834.896813 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1284,10 +1284,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 446757532781 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 446757532781 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 446757532781 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 446757532781 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 479634051298 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 479634051298 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 479634051298 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 479634051298 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |