diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-07-27 16:08:05 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-07-27 16:08:05 -0400 |
| commit | b1a58933e07d7af0eb5f43942f8ad9bc93f28039 (patch) | |
| tree | 21f36b849ba0aed06ec18ed45aef46feeacd7532 /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual | |
| parent | 630068be6f7b6dc5c612867c764c37e41fd90a4a (diff) | |
| download | gem5-b1a58933e07d7af0eb5f43942f8ad9bc93f28039.tar.xz | |
stats: update stats for icache change not allowing dirty data
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual')
3 files changed, 815 insertions, 819 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 363bd4c66..f88222537 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -361,7 +361,7 @@ header_cycles=1 use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index 70032b595..3225b7372 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 15:21:03 +gem5 compiled Jul 26 2012 21:40:00 +gem5 started Jul 27 2012 00:58:01 gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1171612619000 because m5_exit instruction encountered +Exiting @ tick 1172544977000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index bf3a52c45..2693ffabe 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,71 +1,71 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.171613 # Number of seconds simulated -sim_ticks 1171612619000 # Number of ticks simulated -final_tick 1171612619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.172545 # Number of seconds simulated +sim_ticks 1172544977000 # Number of ticks simulated +final_tick 1172544977000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 639669 # Simulator instruction rate (inst/s) -host_op_rate 818158 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12399663305 # Simulator tick rate (ticks/s) -host_mem_usage 384708 # Number of bytes of host memory used -host_seconds 94.49 # Real time elapsed on the host -sim_insts 60440687 # Number of instructions simulated -sim_ops 77305655 # Number of ops (including micro ops) simulated +host_inst_rate 706392 # Simulator instruction rate (inst/s) +host_op_rate 900233 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13469238975 # Simulator tick rate (ticks/s) +host_mem_usage 389548 # Number of bytes of host memory used +host_seconds 87.05 # Real time elapsed on the host +sim_insts 61493926 # Number of instructions simulated +sim_ops 78368454 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 395940 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4717108 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 394788 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4717236 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 321948 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4794672 # Number of bytes read from this memory -system.physmem.bytes_read::total 60561764 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 395940 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 321948 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 717888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4107520 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 322588 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4794736 # Number of bytes read from this memory +system.physmem.bytes_read::total 60561444 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 394788 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 322588 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 717376 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4107264 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7134864 # Number of bytes written to this memory +system.physmem.bytes_written::total 7134608 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12405 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73777 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12387 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73779 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5112 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74943 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6457700 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64180 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5122 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 74944 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6457695 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64176 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821016 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 42959291 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821012 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 42925132 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 337944 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 4026167 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 274790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4092370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51690945 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 337944 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 274790 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 612735 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3505869 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14510 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2569402 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6089781 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3505869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 42959291 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 336693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 4023075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 218 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 275118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4089170 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51649570 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 336693 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 275118 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 611811 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3502863 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14498 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2567359 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6084720 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3502863 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 42925132 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 337944 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 4040677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 274790 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6661772 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57780726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 336693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 4037573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 218 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 275118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6656529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57734290 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -84,237 +84,237 @@ system.realview.nvmem.bw_inst_read::total 58 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 69306 # number of replacements -system.l2c.tagsinuse 52659.016481 # Cycle average of tags in use -system.l2c.total_refs 1685686 # Total number of references to valid blocks. -system.l2c.sampled_refs 134505 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.532516 # Average number of references to valid blocks. +system.l2c.replacements 69301 # number of replacements +system.l2c.tagsinuse 52667.431766 # Cycle average of tags in use +system.l2c.total_refs 1645571 # Total number of references to valid blocks. +system.l2c.sampled_refs 134500 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.234729 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39891.573384 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 39900.139395 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000282 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001243 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3742.951187 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4216.912189 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.733680 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2750.765696 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2054.078820 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.608697 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.itb.walker 0.001242 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3730.644795 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4216.663550 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 2.734150 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2763.076938 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2054.171414 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.608828 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.057113 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.064345 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.056925 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.064341 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.041973 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.031343 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.803513 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4104 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1844 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 401511 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 204865 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5725 # number of ReadReq hits +system.l2c.occ_percent::cpu1.inst 0.042161 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.031344 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.803641 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 4102 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1845 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 402958 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 205810 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5738 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 1962 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 448415 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 143316 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1211742 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 616867 # number of Writeback hits -system.l2c.Writeback_hits::total 616867 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1168 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 575 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1743 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 101 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 311 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56775 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 52975 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109750 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4104 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1844 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 401511 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 261640 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5725 # number of demand (read+write) hits +system.l2c.ReadReq_hits::cpu1.inst 449307 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 144268 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1215990 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 572486 # number of Writeback hits +system.l2c.Writeback_hits::total 572486 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1132 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 588 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1720 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 206 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 104 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 310 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 56781 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 53046 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 109827 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4102 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1845 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 402958 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 262591 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5738 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 1962 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 448415 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 196291 # number of demand (read+write) hits -system.l2c.demand_hits::total 1321492 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4104 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1844 # number of overall hits -system.l2c.overall_hits::cpu0.inst 401511 # number of overall hits -system.l2c.overall_hits::cpu0.data 261640 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5725 # number of overall hits +system.l2c.demand_hits::cpu1.inst 449307 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 197314 # number of demand (read+write) hits +system.l2c.demand_hits::total 1325817 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4102 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1845 # number of overall hits +system.l2c.overall_hits::cpu0.inst 402958 # number of overall hits +system.l2c.overall_hits::cpu0.data 262591 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5738 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 1962 # number of overall hits -system.l2c.overall_hits::cpu1.inst 448415 # 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mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577121 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.559610 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014172 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.222857 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014078 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.222234 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000697 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.279216 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.109125 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.278174 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.108805 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014172 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.222857 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014078 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.222234 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000697 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.279216 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.109125 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.278174 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.108805 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40116.424116 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40042.593770 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40102.015989 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40037.757437 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40147.860697 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40133.296764 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40100.201658 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40036.203942 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40064.570466 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40048.481166 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40058.510638 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40100.208768 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40077.660594 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40018.469716 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.829666 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40043.555680 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40187.487587 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40135.216676 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40104.043393 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.090290 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40068.036656 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40047.125467 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40052.816901 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40066.265060 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40059.099437 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40015.975583 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40062.463740 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40040.090571 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40116.424116 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40020.998547 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40102.015989 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40018.259120 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40147.860697 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40070.016702 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40051.364658 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40187.487587 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40065.952130 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40048.904347 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40116.424116 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40020.998547 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40102.015989 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40018.259120 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40147.860697 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40070.016702 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40051.364658 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40187.487587 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40065.952130 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40048.904347 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -498,9 +498,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7077919 # DTB read hits -system.cpu0.dtb.read_misses 3740 # DTB read misses -system.cpu0.dtb.write_hits 5661726 # DTB write hits +system.cpu0.dtb.read_hits 7082876 # DTB read hits +system.cpu0.dtb.read_misses 3736 # DTB read misses +system.cpu0.dtb.write_hits 5665319 # DTB write hits system.cpu0.dtb.write_misses 804 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -511,13 +511,13 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7081659 # DTB read accesses -system.cpu0.dtb.write_accesses 5662530 # DTB write accesses +system.cpu0.dtb.read_accesses 7086612 # DTB read accesses +system.cpu0.dtb.write_accesses 5666123 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12739645 # DTB hits -system.cpu0.dtb.misses 4544 # DTB misses -system.cpu0.dtb.accesses 12744189 # DTB accesses -system.cpu0.itb.inst_hits 29451654 # ITB inst hits +system.cpu0.dtb.hits 12748195 # DTB hits +system.cpu0.dtb.misses 4540 # DTB misses +system.cpu0.dtb.accesses 12752735 # DTB accesses +system.cpu0.itb.inst_hits 29606138 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -534,79 +534,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29453859 # ITB inst accesses -system.cpu0.itb.hits 29451654 # DTB hits +system.cpu0.itb.inst_accesses 29608343 # ITB inst accesses +system.cpu0.itb.hits 29606138 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29453859 # DTB accesses -system.cpu0.numCycles 2343225238 # number of cpu cycles simulated +system.cpu0.itb.accesses 29608343 # DTB accesses +system.cpu0.numCycles 2345089954 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28759206 # Number of instructions committed -system.cpu0.committedOps 37112849 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33058293 # Number of integer alu accesses +system.cpu0.committedInsts 28907917 # Number of instructions committed +system.cpu0.committedOps 37265600 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33149705 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1242118 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4322812 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33058293 # number of integer instructions +system.cpu0.num_func_calls 1243107 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4358822 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33149705 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 189772382 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36110779 # number of times the integer registers were written +system.cpu0.num_int_register_reads 190344582 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36275228 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13408219 # number of memory refs -system.cpu0.num_load_insts 7415624 # Number of load instructions -system.cpu0.num_store_insts 5992595 # Number of store instructions -system.cpu0.num_idle_cycles 2203054927.350120 # Number of idle cycles -system.cpu0.num_busy_cycles 140170310.649880 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059819 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940181 # Percentage of idle cycles +system.cpu0.num_mem_refs 13418689 # number of memory refs +system.cpu0.num_load_insts 7420825 # Number of load instructions +system.cpu0.num_store_insts 5997864 # Number of store instructions +system.cpu0.num_idle_cycles 2204555139.350120 # Number of idle cycles +system.cpu0.num_busy_cycles 140534814.649880 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059927 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940073 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46686 # number of quiesce instructions executed -system.cpu0.icache.replacements 408292 # number of replacements -system.cpu0.icache.tagsinuse 509.494086 # Cycle average of tags in use -system.cpu0.icache.total_refs 29042833 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 408804 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 71.043417 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 75128321000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.494086 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995106 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995106 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29042833 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29042833 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29042833 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29042833 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29042833 # number of overall hits -system.cpu0.icache.overall_hits::total 29042833 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 408804 # 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number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29451637 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29451637 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29451637 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29451637 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29451637 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013881 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013881 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013881 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013881 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013881 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013881 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14920.138991 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14920.138991 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14920.138991 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14920.138991 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14920.138991 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14920.138991 # average overall miss latency +system.cpu0.kern.inst.quiesce 46687 # number of quiesce instructions executed +system.cpu0.icache.replacements 408797 # number of replacements +system.cpu0.icache.tagsinuse 509.495989 # Cycle average of tags in use +system.cpu0.icache.total_refs 29196812 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 409309 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 71.331957 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 75128897000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.495989 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995109 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995109 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29196812 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29196812 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29196812 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29196812 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29196812 # number of overall hits +system.cpu0.icache.overall_hits::total 29196812 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 409309 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 409309 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157218 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157218 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12342373 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12342373 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12342373 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12342373 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033349 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033349 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025764 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025764 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059000 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059000 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047654 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047654 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029968 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029968 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029968 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029968 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15092.960000 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15092.960000 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34694.216538 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 34694.216538 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10813.611381 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10813.611381 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9961.025093 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9961.025093 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22604.865441 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22604.865441 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22604.865441 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22604.865441 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -739,62 +737,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 306522 # number of writebacks -system.cpu0.dcache.writebacks::total 306522 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228069 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 228069 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141727 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141727 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9289 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9289 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7492 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7492 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369796 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 369796 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 369796 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 369796 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2751577168 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2751577168 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4491927564 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4491927564 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72683507 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72683507 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 51983021 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 51983021 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7243504732 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7243504732 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7243504732 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7243504732 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10423590500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10423590500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 819778500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 819778500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11243369000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11243369000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033365 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033365 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025777 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025777 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059059 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059059 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047650 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047650 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029982 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029982 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029982 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029982 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12064.669762 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12064.669762 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31694.225970 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31694.225970 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7824.685865 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7824.685865 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6938.470502 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6938.470502 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19587.839598 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19587.839598 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19587.839598 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19587.839598 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 306322 # number of writebacks +system.cpu0.dcache.writebacks::total 306322 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228125 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 228125 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141749 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141749 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9279 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9279 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7485 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7485 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 369874 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 369874 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 369874 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 369874 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758091164 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758091164 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4492431566 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4492431566 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72483506 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72483506 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52154019 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52154019 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7250522730 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7250522730 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7250522730 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7250522730 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10425846000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10425846000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 819721500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 819721500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11245567500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11245567500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033349 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033349 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025764 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025764 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059000 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059000 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047609 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047609 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029968 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029968 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029968 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029968 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12090.262637 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12090.262637 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31692.862496 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31692.862496 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7811.564393 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7811.564393 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6967.804810 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6967.804810 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19602.682887 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19602.682887 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19602.682887 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19602.682887 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -804,9 +802,9 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8311872 # DTB read hits -system.cpu1.dtb.read_misses 3663 # DTB read misses -system.cpu1.dtb.write_hits 5828412 # DTB write hits +system.cpu1.dtb.read_hits 8314117 # DTB read hits +system.cpu1.dtb.read_misses 3669 # DTB read misses +system.cpu1.dtb.write_hits 5830380 # DTB write hits system.cpu1.dtb.write_misses 1436 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -817,13 +815,13 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8315535 # DTB read accesses -system.cpu1.dtb.write_accesses 5829848 # DTB write accesses +system.cpu1.dtb.read_accesses 8317786 # DTB read accesses +system.cpu1.dtb.write_accesses 5831816 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14140284 # DTB hits -system.cpu1.dtb.misses 5099 # DTB misses -system.cpu1.dtb.accesses 14145383 # DTB accesses -system.cpu1.itb.inst_hits 32285286 # ITB inst hits +system.cpu1.dtb.hits 14144497 # DTB hits +system.cpu1.dtb.misses 5105 # DTB misses +system.cpu1.dtb.accesses 14149602 # DTB accesses +system.cpu1.itb.inst_hits 33196626 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -840,79 +838,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 32287457 # ITB inst accesses -system.cpu1.itb.hits 32285286 # DTB hits +system.cpu1.itb.inst_accesses 33198797 # ITB inst accesses +system.cpu1.itb.hits 33196626 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 32287457 # DTB accesses -system.cpu1.numCycles 2341739150 # number of cpu cycles simulated +system.cpu1.itb.accesses 33198797 # DTB accesses +system.cpu1.numCycles 2343593518 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 31681481 # Number of instructions committed -system.cpu1.committedOps 40192806 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 36864445 # Number of integer alu accesses +system.cpu1.committedInsts 32586009 # Number of instructions committed +system.cpu1.committedOps 41102854 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 37326288 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962202 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3487066 # number of instructions that are conditional controls -system.cpu1.num_int_insts 36864445 # number of integer instructions +system.cpu1.num_func_calls 962171 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3714570 # number of instructions that are conditional controls +system.cpu1.num_int_insts 37326288 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 210742691 # number of times the integer registers were read -system.cpu1.num_int_register_writes 38544620 # number of times the integer registers were written +system.cpu1.num_int_register_reads 213739964 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39466250 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14678127 # number of memory refs -system.cpu1.num_load_insts 8633777 # Number of load instructions -system.cpu1.num_store_insts 6044350 # Number of store instructions -system.cpu1.num_idle_cycles 1858809543.114650 # Number of idle cycles -system.cpu1.num_busy_cycles 482929606.885350 # Number of busy cycles -system.cpu1.not_idle_fraction 0.206227 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.793773 # Percentage of idle cycles +system.cpu1.num_mem_refs 14682267 # number of memory refs +system.cpu1.num_load_insts 8636040 # Number of load instructions +system.cpu1.num_store_insts 6046227 # Number of store instructions +system.cpu1.num_idle_cycles 1858750530.714142 # Number of idle cycles +system.cpu1.num_busy_cycles 484842987.285858 # Number of busy cycles +system.cpu1.not_idle_fraction 0.206880 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.793120 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43917 # number of quiesce instructions executed -system.cpu1.icache.replacements 454429 # number of replacements -system.cpu1.icache.tagsinuse 478.358537 # Cycle average of tags in use -system.cpu1.icache.total_refs 31830341 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 454941 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 69.965866 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 92993102000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.358537 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.934294 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.934294 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 31830341 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 31830341 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 31830341 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 31830341 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 31830341 # number of overall hits -system.cpu1.icache.overall_hits::total 31830341 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 454941 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 454941 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 454941 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 454941 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 454941 # number of overall misses -system.cpu1.icache.overall_misses::total 454941 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6716097000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6716097000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6716097000 # 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number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 170766 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 150259 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 150259 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11112 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11112 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10077 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10077 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 321025 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 321025 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 321025 # number of overall misses +system.cpu1.dcache.overall_misses::total 321025 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2375372000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2375372000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5143695000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 5143695000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106521500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 106521500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 88394000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 88394000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 7519067000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 7519067000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 7519067000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 7519067000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7120080 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7120080 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4979982 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4979982 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92929 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 92929 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92849 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 92849 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 12100062 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 12100062 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 12100062 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 12100062 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023984 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.023984 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030173 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030173 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119575 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119575 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108531 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108531 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026531 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026531 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026531 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026531 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13910.099200 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13910.099200 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34232.192414 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34232.192414 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9586.168107 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9586.168107 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8771.856703 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8771.856703 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23422.060587 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23422.060587 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23422.060587 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23422.060587 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1045,62 +1041,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 266082 # number of writebacks -system.cpu1.dcache.writebacks::total 266082 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170612 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170612 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150091 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 150091 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11098 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11098 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10038 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10038 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 320703 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 320703 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 320703 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 320703 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1855824122 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1855824122 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4690597670 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4690597670 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72957002 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72957002 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57198010 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57198010 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6546421792 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6546421792 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6546421792 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6546421792 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136480079000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136480079000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39677118500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39677118500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176157197500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176157197500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023970 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023970 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030151 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030151 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119446 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119446 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108127 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108127 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026513 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026513 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10877.453649 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10877.453649 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31251.691774 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31251.691774 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6573.887367 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6573.887367 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5698.148037 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5698.148037 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20412.723897 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20412.723897 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20412.723897 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20412.723897 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 266164 # number of writebacks +system.cpu1.dcache.writebacks::total 266164 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170766 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170766 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150259 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 150259 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11112 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11112 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10067 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10067 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 321025 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 321025 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 321025 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 321025 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1862452631 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1862452631 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4692688176 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4692688176 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73165002 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 73165002 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 58182011 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 58182011 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6555140807 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6555140807 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6555140807 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6555140807 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136477204500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136477204500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39709759000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39709759000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176186963500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176186963500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023984 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023984 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030173 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030173 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119575 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119575 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108423 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108423 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026531 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026531 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026531 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026531 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10906.460484 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10906.460484 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31230.662895 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31230.662895 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6584.323434 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6584.323434 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5779.478593 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5779.478593 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20419.409102 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20419.409102 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20419.409102 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20419.409102 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1122,10 +1118,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550047772786 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 550047772786 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550047772786 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 550047772786 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550791407487 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 550791407487 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550791407487 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 550791407487 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |