diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-10 11:57:37 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-10 11:57:37 -0400 |
| commit | d6283445744d5be2a9ac33f0adbc729d48e22c40 (patch) | |
| tree | 67910602fd144f50fa86b1c8a90e0e4f0e66ee90 /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual | |
| parent | cf5935445f23d0ba2f41debc50952fe45d7c9f4a (diff) | |
| download | gem5-d6283445744d5be2a9ac33f0adbc729d48e22c40.tar.xz | |
Device: Update stats for PIO and PCI latency change
This patch merely updates the regression stats to reflect the change
in PIO and PCI latency.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt | 1760 |
1 files changed, 897 insertions, 863 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 2693ffabe..a84f458bf 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,71 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.172545 # Number of seconds simulated -sim_ticks 1172544977000 # Number of ticks simulated -final_tick 1172544977000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.207291 # Number of seconds simulated +sim_ticks 1207290627000 # Number of ticks simulated +final_tick 1207290627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 706392 # Simulator instruction rate (inst/s) -host_op_rate 900233 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13469238975 # Simulator tick rate (ticks/s) -host_mem_usage 389548 # Number of bytes of host memory used -host_seconds 87.05 # Real time elapsed on the host -sim_insts 61493926 # Number of instructions simulated -sim_ops 78368454 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 394788 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4717236 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 322588 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4794736 # Number of bytes read from this memory -system.physmem.bytes_read::total 60561444 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 394788 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 322588 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 717376 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4107264 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7134608 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12387 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73779 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5122 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74944 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6457695 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64176 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821012 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 42925132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 336693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 4023075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 218 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 275118 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4089170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51649570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 336693 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 275118 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 611811 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3502863 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14498 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2567359 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6084720 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3502863 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 42925132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 336693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 4037573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 218 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 275118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6656529 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57734290 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 1000042 # Simulator instruction rate (inst/s) +host_op_rate 1274494 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19638848032 # Simulator tick rate (ticks/s) +host_mem_usage 383956 # Number of bytes of host memory used +host_seconds 61.47 # Real time elapsed on the host +sim_insts 61477134 # Number of instructions simulated +sim_ops 78349023 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -76,245 +21,318 @@ system.realview.nvmem.num_reads::cpu0.inst 5 # system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 58 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 56 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 58 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 56 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 69301 # number of replacements -system.l2c.tagsinuse 52667.431766 # Cycle average of tags in use -system.l2c.total_refs 1645571 # Total number of references to valid blocks. -system.l2c.sampled_refs 134500 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.234729 # Average number of references to valid blocks. +system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 52642784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 394084 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4718772 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 323100 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4791152 # Number of bytes read from this memory +system.physmem.bytes_read::total 62870404 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 394084 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 323100 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 717184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4105920 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory +system.physmem.bytes_written::total 7133264 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 6580348 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12376 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73803 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5130 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 74888 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6746553 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64155 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory +system.physmem.num_writes::total 820991 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43604069 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 106 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 326420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3908563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 212 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 53 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 267624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3968516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52075617 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 326420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 267624 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 594044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3400938 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14081 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2493471 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5908490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3400938 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43604069 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 326420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3922645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 267624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6461987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57984106 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 69267 # number of replacements +system.l2c.tagsinuse 52917.687187 # Cycle average of tags in use +system.l2c.total_refs 1645693 # Total number of references to valid blocks. +system.l2c.sampled_refs 134464 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.238912 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39900.139395 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000282 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001242 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3730.644795 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4216.663550 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.734150 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2763.076938 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2054.171414 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.608828 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 40124.661939 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 0.000403 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.001466 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3720.854168 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4213.259552 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 2.746626 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.001732 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2800.295642 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2055.865658 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.612254 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056925 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.064341 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.056776 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.064289 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.042161 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.031344 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.803641 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4102 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1845 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 402958 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 205810 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5738 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1962 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 449307 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 144268 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1215990 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 572486 # number of Writeback hits -system.l2c.Writeback_hits::total 572486 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1132 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 588 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1720 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 206 # number of SCUpgradeReq hits +system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.042729 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.031370 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.807460 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 4114 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1841 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 402307 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 205875 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5723 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1959 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 449970 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 144091 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1215880 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 572580 # number of Writeback hits +system.l2c.Writeback_hits::total 572580 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1130 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 572 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1702 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 212 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 104 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 310 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56781 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 53046 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109827 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4102 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1845 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 402958 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 262591 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5738 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1962 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 449307 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 197314 # number of demand (read+write) hits -system.l2c.demand_hits::total 1325817 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4102 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1845 # number of overall hits -system.l2c.overall_hits::cpu0.inst 402958 # number of overall hits -system.l2c.overall_hits::cpu0.data 262591 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5738 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1962 # number of overall hits -system.l2c.overall_hits::cpu1.inst 449307 # number of overall hits -system.l2c.overall_hits::cpu1.data 197314 # number of overall hits -system.l2c.overall_hits::total 1325817 # number of overall hits +system.l2c.SCUpgradeReq_hits::total 316 # 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number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 31316076500 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154365734497 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167083883995 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1128303000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30843793500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31972096500 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10009780499 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13576971498 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152778471500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 163057732999 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014078 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036813 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000697 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024649 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.018015 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.805765 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.859632 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.828292 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.733850 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.827243 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.774709 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.541889 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577121 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.559610 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014078 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.222234 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000697 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.278174 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.108805 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014078 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.222234 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000697 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.278174 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.108805 # mshr miss rate for overall accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185209527997 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 199055980495 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036838 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024633 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.018016 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.806308 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.862368 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.829630 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.728553 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.823430 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.769343 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.542246 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577072 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.559760 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.222312 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.278223 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.108803 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.222312 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.278223 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.108803 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40102.015989 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40037.757437 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40044.227756 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40030.226060 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40187.487587 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40135.216676 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40104.043393 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.090290 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40068.036656 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40047.125467 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40052.816901 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40066.265060 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40059.099437 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40015.975583 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40062.463740 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40040.090571 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40174.895895 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40071.723001 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40073.295378 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40083.971088 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40087.890625 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40085.666023 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40014.059754 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40086.597938 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40047.438330 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40007.203131 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40041.125242 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40024.789835 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40102.015989 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40018.259120 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40044.227756 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40009.618075 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40187.487587 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40065.952130 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40048.904347 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40174.895895 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40042.590716 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40031.475531 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40102.015989 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40018.259120 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40044.227756 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40009.618075 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40187.487587 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40065.952130 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40048.904347 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40174.895895 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40042.590716 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40031.475531 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -498,26 +528,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7082876 # DTB read hits -system.cpu0.dtb.read_misses 3736 # DTB read misses -system.cpu0.dtb.write_hits 5665319 # DTB write hits +system.cpu0.dtb.read_hits 7076084 # DTB read hits +system.cpu0.dtb.read_misses 3743 # DTB read misses +system.cpu0.dtb.write_hits 5660386 # DTB write hits system.cpu0.dtb.write_misses 804 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1790 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7086612 # DTB read accesses -system.cpu0.dtb.write_accesses 5666123 # DTB write accesses +system.cpu0.dtb.read_accesses 7079827 # DTB read accesses +system.cpu0.dtb.write_accesses 5661190 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12748195 # DTB hits -system.cpu0.dtb.misses 4540 # DTB misses -system.cpu0.dtb.accesses 12752735 # DTB accesses -system.cpu0.itb.inst_hits 29606138 # ITB inst hits +system.cpu0.dtb.hits 12736470 # DTB hits +system.cpu0.dtb.misses 4547 # DTB misses +system.cpu0.dtb.accesses 12741017 # DTB accesses +system.cpu0.itb.inst_hits 29574655 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -534,79 +564,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29608343 # ITB inst accesses -system.cpu0.itb.hits 29606138 # DTB hits +system.cpu0.itb.inst_accesses 29576860 # ITB inst accesses +system.cpu0.itb.hits 29574655 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29608343 # DTB accesses -system.cpu0.numCycles 2345089954 # number of cpu cycles simulated +system.cpu0.itb.accesses 29576860 # DTB accesses +system.cpu0.numCycles 2414581254 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28907917 # Number of instructions committed -system.cpu0.committedOps 37265600 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33149705 # Number of integer alu accesses +system.cpu0.committedInsts 28876799 # Number of instructions committed +system.cpu0.committedOps 37228975 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33114839 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1243107 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4358822 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33149705 # number of integer instructions +system.cpu0.num_func_calls 1241592 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4354316 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33114839 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 190344582 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36275228 # number of times the integer registers were written +system.cpu0.num_int_register_reads 190147140 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36238708 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13418689 # number of memory refs -system.cpu0.num_load_insts 7420825 # Number of load instructions -system.cpu0.num_store_insts 5997864 # Number of store instructions -system.cpu0.num_idle_cycles 2204555139.350120 # Number of idle cycles -system.cpu0.num_busy_cycles 140534814.649880 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059927 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940073 # Percentage of idle cycles +system.cpu0.num_mem_refs 13404188 # number of memory refs +system.cpu0.num_load_insts 7413537 # Number of load instructions +system.cpu0.num_store_insts 5990651 # Number of store instructions +system.cpu0.num_idle_cycles 2267023722.330122 # Number of idle cycles +system.cpu0.num_busy_cycles 147557531.669878 # Number of busy cycles +system.cpu0.not_idle_fraction 0.061111 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.938889 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46687 # number of quiesce instructions executed -system.cpu0.icache.replacements 408797 # number of replacements -system.cpu0.icache.tagsinuse 509.495989 # Cycle average of tags in use -system.cpu0.icache.total_refs 29196812 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 409309 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 71.331957 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 75128897000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.495989 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995109 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995109 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29196812 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29196812 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29196812 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29196812 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29196812 # number of overall hits -system.cpu0.icache.overall_hits::total 29196812 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 409309 # 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number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29606121 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29606121 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29606121 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29606121 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29606121 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013825 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013825 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013825 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013825 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013825 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013825 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14923.131424 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14923.131424 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14923.131424 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14923.131424 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14923.131424 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14923.131424 # average overall miss latency +system.cpu0.kern.inst.quiesce 46683 # number of quiesce instructions executed +system.cpu0.icache.replacements 408135 # number of replacements +system.cpu0.icache.tagsinuse 509.469782 # Cycle average of tags in use +system.cpu0.icache.total_refs 29165991 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 408647 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 71.372091 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 75845657000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.469782 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995058 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995058 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29165991 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29165991 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29165991 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29165991 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29165991 # number of overall hits +system.cpu0.icache.overall_hits::total 29165991 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 408647 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 408647 # 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number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29574638 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29574638 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29574638 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29574638 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013817 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013817 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013817 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013817 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013817 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013817 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.044180 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.044180 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.044180 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14918.044180 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.044180 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14918.044180 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -615,120 +645,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # 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mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013825 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.013825 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11921.036430 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11921.036430 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11921.036430 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11921.036430 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11921.036430 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11921.036430 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013817 # 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average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 330813 # number of replacements -system.cpu0.dcache.tagsinuse 457.939353 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12292528 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 331325 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.101118 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 330734 # 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miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059000 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059000 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047654 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047654 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029968 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029968 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029968 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029968 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15092.960000 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15092.960000 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34694.216538 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 34694.216538 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10813.611381 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10813.611381 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9961.025093 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9961.025093 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22604.865441 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 22604.865441 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22604.865441 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 22604.865441 # average overall miss latency +system.cpu0.dcache.occ_blocks::cpu0.data 459.649704 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.897753 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.897753 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6605687 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6605687 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5355220 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5355220 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147939 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147939 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149683 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149683 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11960907 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11960907 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11960907 # number of overall hits +system.cpu0.dcache.overall_hits::total 11960907 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 228053 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 228053 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 141722 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 141722 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9325 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9325 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7497 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7497 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 369775 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 369775 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 369775 # number of overall misses +system.cpu0.dcache.overall_misses::total 369775 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3443053000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3443053000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4918745500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4918745500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100903000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 100903000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74598000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 74598000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8361798500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8361798500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8361798500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8361798500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6833740 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6833740 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5496942 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5496942 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157264 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157264 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157180 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157180 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12330682 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12330682 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12330682 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12330682 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033372 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033372 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025782 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025782 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059295 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059295 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047697 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047697 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029988 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029988 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029988 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029988 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15097.600119 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15097.600119 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34707.000325 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 34707.000325 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10820.697051 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10820.697051 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9950.380152 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9950.380152 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22613.206680 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22613.206680 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.206680 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22613.206680 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -737,62 +767,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 306322 # number of writebacks -system.cpu0.dcache.writebacks::total 306322 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228125 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 228125 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141749 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141749 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9279 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9279 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7485 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7485 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369874 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 369874 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 369874 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 369874 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758091164 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758091164 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4492431566 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4492431566 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72483506 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72483506 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52154019 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52154019 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7250522730 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7250522730 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7250522730 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7250522730 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10425846000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10425846000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 819721500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 819721500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11245567500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11245567500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033349 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033349 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025764 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025764 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059000 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059000 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047609 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047609 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029968 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029968 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029968 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029968 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12090.262637 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12090.262637 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31692.862496 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31692.862496 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7811.564393 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7811.564393 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6967.804810 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6967.804810 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19602.682887 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19602.682887 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19602.682887 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19602.682887 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 306480 # number of writebacks +system.cpu0.dcache.writebacks::total 306480 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228053 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 228053 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141722 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141722 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9325 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9325 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7489 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7489 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 369775 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 369775 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 369775 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 369775 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758299641 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758299641 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4493384071 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4493384071 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72902006 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72902006 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52119015 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52119015 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1001 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1001 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7251683712 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7251683712 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7251683712 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7251683712 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559859000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559859000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253198500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253198500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14813057500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14813057500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033372 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033372 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025782 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025782 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059295 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059295 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047646 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047646 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029988 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029988 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12094.993887 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12094.993887 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.621364 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.621364 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7817.909491 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.909491 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6959.409133 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6959.409133 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.070819 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.070819 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.070819 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.070819 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -802,26 +836,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8314117 # DTB read hits -system.cpu1.dtb.read_misses 3669 # DTB read misses -system.cpu1.dtb.write_hits 5830380 # DTB write hits -system.cpu1.dtb.write_misses 1436 # DTB write misses +system.cpu1.dtb.read_hits 8318170 # DTB read hits +system.cpu1.dtb.read_misses 3663 # DTB read misses +system.cpu1.dtb.write_hits 5832653 # DTB write hits +system.cpu1.dtb.write_misses 1435 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1967 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1968 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8317786 # DTB read accesses -system.cpu1.dtb.write_accesses 5831816 # DTB write accesses +system.cpu1.dtb.read_accesses 8321833 # DTB read accesses +system.cpu1.dtb.write_accesses 5834088 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14144497 # DTB hits -system.cpu1.dtb.misses 5105 # DTB misses -system.cpu1.dtb.accesses 14149602 # DTB accesses -system.cpu1.itb.inst_hits 33196626 # ITB inst hits +system.cpu1.dtb.hits 14150823 # DTB hits +system.cpu1.dtb.misses 5098 # DTB misses +system.cpu1.dtb.accesses 14155921 # DTB accesses +system.cpu1.itb.inst_hits 33211066 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -838,79 +872,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33198797 # ITB inst accesses -system.cpu1.itb.hits 33196626 # DTB hits +system.cpu1.itb.inst_accesses 33213237 # ITB inst accesses +system.cpu1.itb.hits 33211066 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33198797 # DTB accesses -system.cpu1.numCycles 2343593518 # number of cpu cycles simulated +system.cpu1.itb.accesses 33213237 # DTB accesses +system.cpu1.numCycles 2413083038 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32586009 # Number of instructions committed -system.cpu1.committedOps 41102854 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37326288 # Number of integer alu accesses +system.cpu1.committedInsts 32600335 # Number of instructions committed +system.cpu1.committedOps 41120048 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 37342001 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962171 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3714570 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37326288 # number of integer instructions +system.cpu1.num_func_calls 963082 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3716244 # number of instructions that are conditional controls +system.cpu1.num_int_insts 37342001 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 213739964 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39466250 # number of times the integer registers were written +system.cpu1.num_int_register_reads 213831809 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39482622 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14682267 # number of memory refs -system.cpu1.num_load_insts 8636040 # Number of load instructions -system.cpu1.num_store_insts 6046227 # Number of store instructions -system.cpu1.num_idle_cycles 1858750530.714142 # Number of idle cycles -system.cpu1.num_busy_cycles 484842987.285858 # Number of busy cycles -system.cpu1.not_idle_fraction 0.206880 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.793120 # Percentage of idle cycles +system.cpu1.num_mem_refs 14689113 # number of memory refs +system.cpu1.num_load_insts 8640454 # Number of load instructions +system.cpu1.num_store_insts 6048659 # Number of store instructions +system.cpu1.num_idle_cycles 1863361909.381196 # Number of idle cycles +system.cpu1.num_busy_cycles 549721128.618804 # Number of busy cycles +system.cpu1.not_idle_fraction 0.227809 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.772191 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43921 # number of quiesce instructions executed -system.cpu1.icache.replacements 454393 # number of replacements -system.cpu1.icache.tagsinuse 478.384673 # Cycle average of tags in use -system.cpu1.icache.total_refs 32741717 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 454905 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 71.974845 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 92994898000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.384673 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.934345 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.934345 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 32741717 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32741717 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32741717 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32741717 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32741717 # number of overall hits -system.cpu1.icache.overall_hits::total 32741717 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 454905 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 454905 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 454905 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 454905 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 454905 # number of overall misses -system.cpu1.icache.overall_misses::total 454905 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6718353500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6718353500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6718353500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6718353500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6718353500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6718353500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33196622 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33196622 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33196622 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33196622 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33196622 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33196622 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013703 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.013703 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013703 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.013703 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013703 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.013703 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.695662 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.695662 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.695662 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14768.695662 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.695662 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14768.695662 # average overall miss latency +system.cpu1.kern.inst.quiesce 43948 # number of quiesce instructions executed +system.cpu1.icache.replacements 455071 # number of replacements +system.cpu1.icache.tagsinuse 479.019014 # Cycle average of tags in use +system.cpu1.icache.total_refs 32755479 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 455583 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 71.897940 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 94151388000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 479.019014 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.935584 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.935584 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 32755479 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 32755479 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 32755479 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 32755479 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 32755479 # number of overall hits +system.cpu1.icache.overall_hits::total 32755479 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 455583 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 455583 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 455583 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 455583 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 455583 # number of overall misses +system.cpu1.icache.overall_misses::total 455583 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6728267000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6728267000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6728267000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6728267000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6728267000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6728267000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 33211062 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 33211062 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 33211062 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 33211062 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 33211062 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 33211062 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013718 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.013718 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013718 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.013718 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013718 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.013718 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.476875 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.476875 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.476875 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14768.476875 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.476875 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14768.476875 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -919,120 +953,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454905 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 454905 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 454905 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 454905 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 454905 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 454905 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5352734000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5352734000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5352734000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5352734000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5352734000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5352734000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 455583 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 455583 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 455583 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 455583 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 455583 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 455583 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5360614000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5360614000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5360614000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5360614000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5360614000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5360614000 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013703 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013703 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013703 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.013703 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013703 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.013703 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.707334 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.707334 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.707334 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.707334 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.707334 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.707334 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013718 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.013718 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.013718 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.492604 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.492604 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.492604 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 292476 # number of replacements -system.cpu1.dcache.tagsinuse 472.237187 # Cycle average of tags in use -system.cpu1.dcache.total_refs 11966907 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 292816 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 40.868351 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 84138671000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 472.237187 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.922338 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.922338 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 6949314 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6949314 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4829723 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4829723 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81817 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 81817 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82772 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 82772 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11779037 # 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number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1860610613 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1860610613 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4686894192 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4686894192 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72963005 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72963005 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57623011 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57623011 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6547504805 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6547504805 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6547504805 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6547504805 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686172000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686172000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39932194000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39932194000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618366000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618366000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024002 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024002 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030142 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030142 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119518 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119518 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108316 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108316 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026529 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026529 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10881.527435 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10881.527435 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.381445 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.381445 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6560.831310 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6560.831310 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5722.245382 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5722.245382 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.112941 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.112941 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.112941 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.112941 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1118,10 +1152,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550791407487 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 550791407487 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550791407487 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 550791407487 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574301885796 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 574301885796 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574301885796 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 574301885796 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |