diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
| commit | fda338f8d3ba6f6cb271e2c10cb880ff064edb61 (patch) | |
| tree | 20a91f6acacb2cb40967ce56a539d8444b744b9e /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual | |
| parent | b265d9925c123f0df50db98cf56dab6a3596b54b (diff) | |
| download | gem5-fda338f8d3ba6f6cb271e2c10cb880ff064edb61.tar.xz | |
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual')
3 files changed, 869 insertions, 873 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index f78b6a8fb..363bd4c66 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem midr_regval=890224640 multi_proc=true num_work_ids=16 @@ -298,7 +298,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma @@ -359,7 +359,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side @@ -772,7 +772,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index ccc6b6e90..70032b595 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:37:10 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 15:21:03 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1169301297000 because m5_exit instruction encountered +Exiting @ tick 1171612619000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index a92b3a054..bf3a52c45 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,320 +1,320 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.169301 # Number of seconds simulated -sim_ticks 1169301297000 # Number of ticks simulated -final_tick 1169301297000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.171613 # Number of seconds simulated +sim_ticks 1171612619000 # Number of ticks simulated +final_tick 1171612619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 971844 # Simulator instruction rate (inst/s) -host_op_rate 1242825 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18805861990 # Simulator tick rate (ticks/s) -host_mem_usage 384788 # Number of bytes of host memory used -host_seconds 62.18 # Real time elapsed on the host -sim_insts 60426768 # Number of instructions simulated -sim_ops 77275723 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 58 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 58 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 639669 # Simulator instruction rate (inst/s) +host_op_rate 818158 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12399663305 # Simulator tick rate (ticks/s) +host_mem_usage 384708 # Number of bytes of host memory used +host_seconds 94.49 # Real time elapsed on the host +sim_insts 60440687 # Number of instructions simulated +sim_ops 77305655 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 394404 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4694964 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 395940 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4717108 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 322780 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4800816 # Number of bytes read from this memory -system.physmem.bytes_read::total 60545060 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 394404 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 322780 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 717184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4092224 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 321948 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4794672 # Number of bytes read from this memory +system.physmem.bytes_read::total 60561764 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 395940 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 321948 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 717888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4107520 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7119568 # Number of bytes written to this memory +system.physmem.bytes_written::total 7134864 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12381 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73431 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12405 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73777 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5125 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75039 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6457439 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 63941 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5112 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 74943 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6457700 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64180 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 820777 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43044208 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821016 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 42959291 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 337299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 4015188 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 337944 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 4026167 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 276045 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4105713 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51778836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 337299 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 276045 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 613344 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3499717 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14539 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2574481 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6088737 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3499717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43044208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 274790 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4092370 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51690945 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 337944 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 274790 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 612735 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3505869 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14510 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2569402 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6089781 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3505869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 42959291 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 337299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 4029726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 337944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 4040677 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 276045 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6680194 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57867573 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 69045 # number of replacements -system.l2c.tagsinuse 52660.415221 # Cycle average of tags in use -system.l2c.total_refs 1684870 # Total number of references to valid blocks. -system.l2c.sampled_refs 134185 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.556321 # Average number of references to valid blocks. +system.physmem.bw_total::cpu1.inst 274790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6661772 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57780726 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 58 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 58 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 69306 # number of replacements +system.l2c.tagsinuse 52659.016481 # Cycle average of tags in use +system.l2c.total_refs 1685686 # Total number of references to valid blocks. +system.l2c.sampled_refs 134505 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.532516 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39883.931908 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000281 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001232 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3733.911815 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4222.338805 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.732261 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2761.000373 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2056.498545 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.608581 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 39891.573384 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 0.000282 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.001243 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3742.951187 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4216.912189 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 2.733680 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2750.765696 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2054.078820 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.608697 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056975 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.064428 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.057113 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.064345 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.042130 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.031380 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.803534 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4332 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1875 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 401384 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 204711 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5503 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1891 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 448240 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 143182 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1211118 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 615916 # number of Writeback hits -system.l2c.Writeback_hits::total 615916 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1171 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 482 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1653 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 214 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 105 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 319 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56705 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 52894 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109599 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4332 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1875 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 401384 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 261416 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5503 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1891 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 448240 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 196076 # number of demand (read+write) hits -system.l2c.demand_hits::total 1320717 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4332 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1875 # number of overall hits -system.l2c.overall_hits::cpu0.inst 401384 # number of overall hits -system.l2c.overall_hits::cpu0.data 261416 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5503 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1891 # number of overall hits -system.l2c.overall_hits::cpu1.inst 448240 # number of overall hits -system.l2c.overall_hits::cpu1.data 196076 # number of overall hits -system.l2c.overall_hits::total 1320717 # number of overall hits +system.l2c.occ_percent::cpu1.inst 0.041973 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.031343 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.803513 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 4104 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1844 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 401511 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 204865 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5725 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1962 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 448415 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 143316 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1211742 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 616867 # number of Writeback hits +system.l2c.Writeback_hits::total 616867 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1168 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 575 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1743 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 101 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 311 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 56775 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 52975 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 109750 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4104 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1844 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 401511 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 261640 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5725 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1962 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 448415 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 196291 # number of demand (read+write) hits +system.l2c.demand_hits::total 1321492 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4104 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1844 # number of overall hits +system.l2c.overall_hits::cpu0.inst 401511 # number of overall hits +system.l2c.overall_hits::cpu0.data 261640 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5725 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1962 # number of overall hits +system.l2c.overall_hits::cpu1.inst 448415 # number of overall hits +system.l2c.overall_hits::cpu1.data 196291 # number of overall hits +system.l2c.overall_hits::total 1321492 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 5749 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 7868 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 5773 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 7865 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5038 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 3631 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22293 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4671 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3578 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8249 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 565 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 471 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1036 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 66836 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 72487 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139323 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 5025 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 3646 # number of ReadReq misses +system.l2c.ReadReq_misses::total 22316 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 4668 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3562 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8230 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 564 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 479 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1043 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 67164 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 72393 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139557 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 5749 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 74704 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 5773 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 75029 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5038 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 76118 # number of demand (read+write) misses -system.l2c.demand_misses::total 161616 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 5025 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 76039 # number of demand (read+write) misses +system.l2c.demand_misses::total 161873 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 5749 # number of overall misses -system.l2c.overall_misses::cpu0.data 74704 # number of overall misses +system.l2c.overall_misses::cpu0.inst 5773 # number of overall misses +system.l2c.overall_misses::cpu0.data 75029 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu1.inst 5038 # number of overall misses -system.l2c.overall_misses::cpu1.data 76118 # number of overall misses -system.l2c.overall_misses::total 161616 # number of overall misses +system.l2c.overall_misses::cpu1.inst 5025 # number of overall misses +system.l2c.overall_misses::cpu1.data 76039 # number of overall misses +system.l2c.overall_misses::total 161873 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 104000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 299700000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 409350000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 211000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 263300500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 189429000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1162146500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 29698000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 27084000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 56782000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4004000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5670000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 9674000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3477668000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3777626000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7255294000 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 300844500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 409319998 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 208500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 262047000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 190080500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1162656498 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 28957997 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 27214000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 56171997 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3588000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6004000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 9592000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3493801976 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3769288495 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7263090471 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 104000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 299700000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3887018000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 211000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 263300500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3967055000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8417440500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 300844500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3903121974 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 208500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 262047000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3959368995 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8425746969 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 104000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 299700000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3887018000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 211000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 263300500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3967055000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8417440500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4333 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 1877 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 407133 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 212579 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5507 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1891 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 453278 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 146813 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1233411 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 615916 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 615916 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 5842 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4060 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 9902 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 779 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 576 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1355 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 123541 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 125381 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 248922 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4333 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 1877 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 407133 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 336120 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5507 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1891 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 453278 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 272194 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1482333 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4333 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 1877 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 407133 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 336120 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5507 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1891 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 453278 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 272194 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1482333 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000231 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001066 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014121 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.037012 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.011115 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024732 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.018074 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.799555 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.881281 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.833064 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.725289 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.817708 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.764576 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.541003 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.578134 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.559705 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000231 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.001066 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014121 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.222254 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.011115 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.279646 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.109028 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000231 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.001066 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014121 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.222254 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.011115 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.279646 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.109028 # miss rate for overall accesses +system.l2c.overall_miss_latency::cpu0.inst 300844500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3903121974 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 208500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 262047000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3959368995 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8425746969 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4105 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 1846 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 407284 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 212730 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5729 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1962 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 453440 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 146962 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1234058 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 616867 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 616867 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 5836 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4137 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 9973 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 774 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 580 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1354 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 123939 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 125368 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 249307 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4105 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1846 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 407284 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 336669 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5729 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1962 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 453440 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 272330 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1483365 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4105 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1846 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 407284 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 336669 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5729 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1962 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 453440 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 272330 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1483365 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000244 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001083 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014174 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036972 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.011082 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024809 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.018083 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.799863 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.861010 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.825228 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.728682 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.825862 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.770310 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.541912 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.577444 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.559780 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000244 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.001083 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014174 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.222857 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.011082 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.279216 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.109126 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000244 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.001083 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014174 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.222857 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.011082 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.279216 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.109126 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52130.805357 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52027.198780 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52262.901945 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52169.925640 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52130.556677 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6357.953329 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7569.591951 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 6883.501030 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7086.725664 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12038.216561 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 9337.837838 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52032.856544 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52114.530881 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52075.350086 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52112.333276 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52043.229243 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52125 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52148.656716 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52133.982447 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52099.681753 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6203.512639 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7640.089837 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 6825.273026 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6361.702128 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12534.446764 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 9196.548418 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52018.968138 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52067.029892 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52043.899417 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52130.805357 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52032.260655 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52262.901945 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52117.173336 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52082.965177 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52112.333276 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52021.511336 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52148.656716 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52070.240206 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52051.589635 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52130.805357 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52032.260655 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52262.901945 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52117.173336 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52082.965177 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52112.333276 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52021.511336 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52148.656716 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52070.240206 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52051.589635 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -323,8 +323,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 63941 # number of writebacks -system.l2c.writebacks::total 63941 # number of writebacks +system.l2c.writebacks::writebacks 64180 # number of writebacks +system.l2c.writebacks::total 64180 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits @@ -333,149 +333,149 @@ system.l2c.overall_mshr_hits::cpu0.inst 1 # nu system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 5748 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 7868 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 5772 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 7865 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 5038 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 3631 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 22292 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 4671 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3578 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8249 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 565 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 471 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1036 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 66836 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 72487 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 139323 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 5025 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 3646 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 22315 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 4668 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3562 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8230 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 564 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 479 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1043 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 67164 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 72393 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 139557 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 5748 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 74704 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 5772 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 75029 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 5038 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 76118 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 161615 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 5025 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 76039 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 161872 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 5748 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 74704 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 5772 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 75029 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 5038 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 76118 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 161615 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 5025 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 76039 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 161872 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 40000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 80000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 230696000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 314934000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 163000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 202841000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 145857000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 894611000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 186977000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 143294000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 330271000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22610000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 18883000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 41493000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2675636000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2907782000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5583418000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 231552000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 314935000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 160000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 201743000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 146326000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 894836000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 186889000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 142710000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 329599000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22593000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 19208000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 41801000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2687800500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2900558000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5588358500 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 40000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 80000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 230696000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2990570000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 163000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 202841000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3053639000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6478029000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 231552000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 3002735500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 160000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 201743000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3046884000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6483194500 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 40000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 80000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 230696000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2990570000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 163000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 202841000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3053639000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6478029000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 231552000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 3002735500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 160000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 201743000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3046884000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6483194500 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 9317572500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 9312662000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122235998500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131823052000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 699470000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30625900500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 31325370500 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122159781000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131741924000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 694882000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30588601000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31283483000 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10017042500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10007544000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152861899000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 163148422500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000231 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014118 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.037012 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011115 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024732 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.018073 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.799555 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.881281 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.833064 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.725289 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.817708 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.764576 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.541003 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.578134 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.559705 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000231 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014118 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.222254 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011115 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.279646 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.109027 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000231 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014118 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.222254 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011115 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.279646 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.109027 # mshr miss rate for overall accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152748382000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 163025407000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014172 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036972 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024809 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.018083 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.799863 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.861010 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.825228 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.728682 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.825862 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770310 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.541912 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577444 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.559780 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014172 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.222857 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.279216 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.109125 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014172 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.222857 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.279216 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.109125 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40135.003479 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40027.198780 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40262.207225 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40169.925640 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40131.482146 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.329908 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40048.630520 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.701540 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40017.699115 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40091.295117 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.158301 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.856544 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40114.530881 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40075.350086 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40116.424116 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40042.593770 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40147.860697 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40133.296764 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40100.201658 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40036.203942 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40064.570466 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40048.481166 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40058.510638 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40100.208768 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40077.660594 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40018.469716 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.829666 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40043.555680 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40135.003479 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40032.260655 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40262.207225 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40117.173336 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40083.092535 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40116.424116 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40020.998547 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40147.860697 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40070.016702 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40051.364658 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40135.003479 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40032.260655 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40262.207225 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40117.173336 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40083.092535 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40116.424116 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40020.998547 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40147.860697 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40070.016702 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40051.364658 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -498,10 +498,10 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7070010 # DTB read hits -system.cpu0.dtb.read_misses 3742 # DTB read misses -system.cpu0.dtb.write_hits 5655317 # DTB write hits -system.cpu0.dtb.write_misses 808 # DTB write misses +system.cpu0.dtb.read_hits 7077919 # DTB read hits +system.cpu0.dtb.read_misses 3740 # DTB read misses +system.cpu0.dtb.write_hits 5661726 # DTB write hits +system.cpu0.dtb.write_misses 804 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID @@ -511,13 +511,13 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7073752 # DTB read accesses -system.cpu0.dtb.write_accesses 5656125 # DTB write accesses +system.cpu0.dtb.read_accesses 7081659 # DTB read accesses +system.cpu0.dtb.write_accesses 5662530 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12725327 # DTB hits -system.cpu0.dtb.misses 4550 # DTB misses -system.cpu0.dtb.accesses 12729877 # DTB accesses -system.cpu0.itb.inst_hits 29439174 # ITB inst hits +system.cpu0.dtb.hits 12739645 # DTB hits +system.cpu0.dtb.misses 4544 # DTB misses +system.cpu0.dtb.accesses 12744189 # DTB accesses +system.cpu0.itb.inst_hits 29451654 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -534,79 +534,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29441379 # ITB inst accesses -system.cpu0.itb.hits 29439174 # DTB hits +system.cpu0.itb.inst_accesses 29453859 # ITB inst accesses +system.cpu0.itb.hits 29451654 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29441379 # DTB accesses -system.cpu0.numCycles 2338602594 # number of cpu cycles simulated +system.cpu0.itb.accesses 29453859 # DTB accesses +system.cpu0.numCycles 2343225238 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28746820 # Number of instructions committed -system.cpu0.committedOps 37084824 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33031249 # Number of integer alu accesses +system.cpu0.committedInsts 28759206 # Number of instructions committed +system.cpu0.committedOps 37112849 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33058293 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241704 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4321371 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33031249 # number of integer instructions +system.cpu0.num_func_calls 1242118 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4322812 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33058293 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 189614137 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36088732 # number of times the integer registers were written +system.cpu0.num_int_register_reads 189772382 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36110779 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13393278 # number of memory refs -system.cpu0.num_load_insts 7407523 # Number of load instructions -system.cpu0.num_store_insts 5985755 # Number of store instructions -system.cpu0.num_idle_cycles 2203295398.340116 # Number of idle cycles -system.cpu0.num_busy_cycles 135307195.659884 # Number of busy cycles -system.cpu0.not_idle_fraction 0.057858 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.942142 # Percentage of idle cycles +system.cpu0.num_mem_refs 13408219 # number of memory refs +system.cpu0.num_load_insts 7415624 # Number of load instructions +system.cpu0.num_store_insts 5992595 # Number of store instructions +system.cpu0.num_idle_cycles 2203054927.350120 # Number of idle cycles +system.cpu0.num_busy_cycles 140170310.649880 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059819 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940181 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46685 # number of quiesce instructions executed -system.cpu0.icache.replacements 408143 # number of replacements -system.cpu0.icache.tagsinuse 509.526052 # Cycle average of tags in use -system.cpu0.icache.total_refs 29030502 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 408655 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 71.039145 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 74905211000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.526052 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995168 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995168 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29030502 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29030502 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29030502 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29030502 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29030502 # number of overall hits -system.cpu0.icache.overall_hits::total 29030502 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 408655 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 408655 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 408655 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 408655 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 408655 # number of overall misses -system.cpu0.icache.overall_misses::total 408655 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5965025000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5965025000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5965025000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5965025000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5965025000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5965025000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29439157 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29439157 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29439157 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29439157 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29439157 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29439157 # number of overall (read+write) accesses +system.cpu0.kern.inst.quiesce 46686 # number of quiesce instructions executed +system.cpu0.icache.replacements 408292 # number of replacements +system.cpu0.icache.tagsinuse 509.494086 # Cycle average of tags in use +system.cpu0.icache.total_refs 29042833 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 408804 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 71.043417 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 75128321000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.494086 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995106 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995106 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29042833 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29042833 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29042833 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29042833 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29042833 # number of overall hits +system.cpu0.icache.overall_hits::total 29042833 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 408804 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 408804 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 408804 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 408804 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 408804 # number of overall misses +system.cpu0.icache.overall_misses::total 408804 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6099412500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6099412500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6099412500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6099412500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6099412500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6099412500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29451637 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29451637 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29451637 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29451637 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29451637 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29451637 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013881 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.013881 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013881 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.013881 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013881 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013881 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14596.725845 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14596.725845 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14596.725845 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14596.725845 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14596.725845 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14596.725845 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14920.138991 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14920.138991 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14920.138991 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14920.138991 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14920.138991 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14920.138991 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -615,20 +615,20 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 20759 # number of writebacks -system.cpu0.icache.writebacks::total 20759 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408655 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 408655 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 408655 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 408655 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 408655 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 408655 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4737808500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4737808500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4737808500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4737808500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4737808500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4737808500 # number of overall MSHR miss cycles +system.cpu0.icache.writebacks::writebacks 20827 # number of writebacks +system.cpu0.icache.writebacks::total 20827 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408804 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 408804 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 408804 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 408804 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 408804 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 408804 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4872150503 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4872150503 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4872150503 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4872150503 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4872150503 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4872150503 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles @@ -639,98 +639,98 @@ system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013881 system.cpu0.icache.demand_mshr_miss_rate::total 0.013881 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.013881 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11593.663359 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11593.663359 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11593.663359 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11593.663359 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11593.663359 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11593.663359 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11918.059762 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11918.059762 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11918.059762 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11918.059762 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11918.059762 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11918.059762 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 330129 # number of replacements -system.cpu0.dcache.tagsinuse 459.697251 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12270461 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 330641 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.111130 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 459.697251 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.897846 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.897846 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6600245 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6600245 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5350394 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5350394 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147923 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 147923 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149677 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 149677 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11950639 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11950639 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11950639 # number of overall hits -system.cpu0.dcache.overall_hits::total 11950639 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 227470 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 227470 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 141496 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 141496 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9302 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9302 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7489 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7489 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 368966 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 368966 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 368966 # number of overall misses -system.cpu0.dcache.overall_misses::total 368966 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3341792500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3341792500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4877331500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4877331500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98417500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 98417500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68140000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 68140000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8219124000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 8219124000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8219124000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 8219124000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6827715 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6827715 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5491890 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5491890 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157225 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 157225 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157166 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 157166 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12319605 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12319605 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12319605 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12319605 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033316 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033316 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025765 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.025765 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059164 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059164 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047650 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047650 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029949 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029949 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029949 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029949 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14691.135095 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14691.135095 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34469.748261 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 34469.748261 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10580.251559 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10580.251559 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9098.678061 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9098.678061 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22276.101321 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 22276.101321 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22276.101321 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 22276.101321 # average overall miss latency +system.cpu0.dcache.replacements 330880 # number of replacements +system.cpu0.dcache.tagsinuse 457.764906 # Cycle average of tags in use +system.cpu0.dcache.total_refs 12284019 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 331392 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 37.067941 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 664264000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 457.764906 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.894072 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.894072 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6607497 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6607497 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5356507 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5356507 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147994 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147994 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149732 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149732 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11964004 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11964004 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11964004 # number of overall hits +system.cpu0.dcache.overall_hits::total 11964004 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 228069 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 228069 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 141727 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 141727 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9289 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9289 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7498 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7498 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 369796 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 369796 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 369796 # number of overall misses +system.cpu0.dcache.overall_misses::total 369796 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3436407000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3436407000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4917296000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4917296000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100570500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 100570500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74480000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 74480000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8353703000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8353703000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8353703000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8353703000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6835566 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6835566 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5498234 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5498234 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157283 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157283 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157230 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157230 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12333800 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12333800 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12333800 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12333800 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033365 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033365 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025777 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025777 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059059 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059059 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047688 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047688 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029982 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029982 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029982 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029982 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15067.400655 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15067.400655 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34695.548484 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 34695.548484 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10826.838196 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10826.838196 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9933.315551 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9933.315551 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22590.030720 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22590.030720 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22590.030720 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22590.030720 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -739,62 +739,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 306018 # number of writebacks -system.cpu0.dcache.writebacks::total 306018 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227470 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 227470 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141496 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141496 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9302 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9302 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7484 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7484 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 368966 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 368966 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 368966 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 368966 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2659287000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2659287000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4452739000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4452739000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70511500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 70511500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45688000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45688000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7112026000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7112026000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7112026000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7112026000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10424499500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10424499500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 822589000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822589000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11247088500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11247088500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033316 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033316 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025765 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025765 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059164 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059164 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047618 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047618 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029949 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029949 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029949 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029949 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11690.715259 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11690.715259 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31469.009725 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31469.009725 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7580.251559 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7580.251559 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6104.756815 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6104.756815 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19275.559266 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19275.559266 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19275.559266 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19275.559266 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 306522 # number of writebacks +system.cpu0.dcache.writebacks::total 306522 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228069 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 228069 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141727 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141727 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9289 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9289 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7492 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7492 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 369796 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 369796 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 369796 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 369796 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2751577168 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2751577168 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4491927564 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4491927564 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72683507 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72683507 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 51983021 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 51983021 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7243504732 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7243504732 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7243504732 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7243504732 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10423590500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10423590500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 819778500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 819778500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11243369000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11243369000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033365 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033365 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025777 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025777 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059059 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059059 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047650 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047650 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029982 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029982 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029982 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029982 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12064.669762 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12064.669762 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31694.225970 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31694.225970 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7824.685865 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7824.685865 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6938.470502 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6938.470502 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19587.839598 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19587.839598 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19587.839598 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19587.839598 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -804,26 +804,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8311514 # DTB read hits -system.cpu1.dtb.read_misses 3660 # DTB read misses -system.cpu1.dtb.write_hits 5828200 # DTB write hits -system.cpu1.dtb.write_misses 1442 # DTB write misses +system.cpu1.dtb.read_hits 8311872 # DTB read hits +system.cpu1.dtb.read_misses 3663 # DTB read misses +system.cpu1.dtb.write_hits 5828412 # DTB write hits +system.cpu1.dtb.write_misses 1436 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1967 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8315174 # DTB read accesses -system.cpu1.dtb.write_accesses 5829642 # DTB write accesses +system.cpu1.dtb.read_accesses 8315535 # DTB read accesses +system.cpu1.dtb.write_accesses 5829848 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14139714 # DTB hits -system.cpu1.dtb.misses 5102 # DTB misses -system.cpu1.dtb.accesses 14144816 # DTB accesses -system.cpu1.itb.inst_hits 32283727 # ITB inst hits +system.cpu1.dtb.hits 14140284 # DTB hits +system.cpu1.dtb.misses 5099 # DTB misses +system.cpu1.dtb.accesses 14145383 # DTB accesses +system.cpu1.itb.inst_hits 32285286 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -840,79 +840,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 32285898 # ITB inst accesses -system.cpu1.itb.hits 32283727 # DTB hits +system.cpu1.itb.inst_accesses 32287457 # ITB inst accesses +system.cpu1.itb.hits 32285286 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 32285898 # DTB accesses -system.cpu1.numCycles 2337184534 # number of cpu cycles simulated +system.cpu1.itb.accesses 32287457 # DTB accesses +system.cpu1.numCycles 2341739150 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 31679948 # Number of instructions committed -system.cpu1.committedOps 40190899 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 36862651 # Number of integer alu accesses +system.cpu1.committedInsts 31681481 # Number of instructions committed +system.cpu1.committedOps 40192806 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 36864445 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962114 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3486829 # number of instructions that are conditional controls -system.cpu1.num_int_insts 36862651 # number of integer instructions +system.cpu1.num_func_calls 962202 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3487066 # number of instructions that are conditional controls +system.cpu1.num_int_insts 36864445 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 210732518 # number of times the integer registers were read -system.cpu1.num_int_register_writes 38542658 # number of times the integer registers were written +system.cpu1.num_int_register_reads 210742691 # number of times the integer registers were read +system.cpu1.num_int_register_writes 38544620 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14677413 # number of memory refs -system.cpu1.num_load_insts 8633313 # Number of load instructions -system.cpu1.num_store_insts 6044100 # Number of store instructions -system.cpu1.num_idle_cycles 1859139408.190032 # Number of idle cycles -system.cpu1.num_busy_cycles 478045125.809968 # Number of busy cycles -system.cpu1.not_idle_fraction 0.204539 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.795461 # Percentage of idle cycles +system.cpu1.num_mem_refs 14678127 # number of memory refs +system.cpu1.num_load_insts 8633777 # Number of load instructions +system.cpu1.num_store_insts 6044350 # Number of store instructions +system.cpu1.num_idle_cycles 1858809543.114650 # Number of idle cycles +system.cpu1.num_busy_cycles 482929606.885350 # Number of busy cycles +system.cpu1.not_idle_fraction 0.206227 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.793773 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43902 # number of quiesce instructions executed -system.cpu1.icache.replacements 454250 # number of replacements -system.cpu1.icache.tagsinuse 478.426272 # Cycle average of tags in use -system.cpu1.icache.total_refs 31828961 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 454762 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 69.990371 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 91827158000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.426272 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.934426 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.934426 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 31828961 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 31828961 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 31828961 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 31828961 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 31828961 # number of overall hits -system.cpu1.icache.overall_hits::total 31828961 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 454762 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 454762 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 454762 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 454762 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 454762 # number of overall misses -system.cpu1.icache.overall_misses::total 454762 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6579254500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6579254500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6579254500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6579254500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6579254500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6579254500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 32283723 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 32283723 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 32283723 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 32283723 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 32283723 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 32283723 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014086 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014086 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014086 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014086 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014086 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014086 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14467.467598 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14467.467598 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14467.467598 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14467.467598 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14467.467598 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14467.467598 # average overall miss latency +system.cpu1.kern.inst.quiesce 43917 # number of quiesce instructions executed +system.cpu1.icache.replacements 454429 # number of replacements +system.cpu1.icache.tagsinuse 478.358537 # Cycle average of tags in use +system.cpu1.icache.total_refs 31830341 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 454941 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 69.965866 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 92993102000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 478.358537 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.934294 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.934294 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 31830341 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 31830341 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 31830341 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 31830341 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 31830341 # number of overall hits +system.cpu1.icache.overall_hits::total 31830341 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 454941 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 454941 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 454941 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 454941 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 454941 # number of overall misses +system.cpu1.icache.overall_misses::total 454941 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6716097000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6716097000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6716097000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6716097000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6716097000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6716097000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 32285282 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 32285282 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 32285282 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 32285282 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 32285282 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 32285282 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014091 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014091 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014091 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014091 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014091 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014091 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14762.567014 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14762.567014 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14762.567014 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14762.567014 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14762.567014 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14762.567014 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -921,122 +921,122 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 23283 # number of writebacks -system.cpu1.icache.writebacks::total 23283 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454762 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 454762 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 454762 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 454762 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 454762 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 454762 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5213754000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5213754000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5213754000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5213754000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5213754000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5213754000 # number of overall MSHR miss cycles +system.cpu1.icache.writebacks::writebacks 23436 # number of writebacks +system.cpu1.icache.writebacks::total 23436 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454941 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 454941 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 454941 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 454941 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 454941 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 454941 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5350372502 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5350372502 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5350372502 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5350372502 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5350372502 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5350372502 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014086 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014086 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014086 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.014086 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014086 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.014086 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11464.796971 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11464.796971 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11464.796971 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11464.796971 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11464.796971 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11464.796971 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014091 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014091 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014091 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.014091 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014091 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.014091 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11760.585443 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11760.585443 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11760.585443 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11760.585443 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11760.585443 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11760.585443 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 292077 # number of replacements -system.cpu1.dcache.tagsinuse 472.260521 # Cycle average of tags in use -system.cpu1.dcache.total_refs 11962886 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 292453 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 40.905328 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 83467733000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 472.260521 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.922384 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.922384 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 6946947 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6946947 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4827784 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4827784 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81815 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 81815 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82770 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 82770 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11774731 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11774731 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11774731 # number of overall hits -system.cpu1.dcache.overall_hits::total 11774731 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 170577 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 170577 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 150060 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 150060 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11061 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11061 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10037 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10037 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 320637 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 320637 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 320637 # number of overall misses -system.cpu1.dcache.overall_misses::total 320637 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2293338000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2293338000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5119779000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 5119779000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 102150000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 102150000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 75382000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 75382000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 7413117000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 7413117000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 7413117000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 7413117000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 7117524 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7117524 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4977844 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4977844 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92876 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 92876 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92807 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 92807 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 12095368 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 12095368 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 12095368 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 12095368 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023966 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.023966 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030146 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030146 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119094 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119094 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108149 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108149 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026509 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026509 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026509 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.026509 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13444.591006 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13444.591006 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34118.212715 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 34118.212715 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9235.150529 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9235.150529 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7510.411478 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7510.411478 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23119.967440 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23119.967440 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23119.967440 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23119.967440 # average overall miss latency +system.cpu1.dcache.replacements 292285 # number of replacements +system.cpu1.dcache.tagsinuse 472.233445 # Cycle average of tags in use +system.cpu1.dcache.total_refs 11962904 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 292625 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 40.881346 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 84136899000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 472.233445 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.922331 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.922331 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 6947233 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 6947233 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4827936 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4827936 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81814 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 81814 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82788 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 82788 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 11775169 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11775169 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 11775169 # number of overall hits +system.cpu1.dcache.overall_hits::total 11775169 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 170612 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 170612 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 150091 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 150091 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11098 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11098 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10047 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10047 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 320703 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 320703 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 320703 # number of overall misses +system.cpu1.dcache.overall_misses::total 320703 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2368289000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2368289000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5141096000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 5141096000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106270500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 106270500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87322000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 87322000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 7509385000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 7509385000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 7509385000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 7509385000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7117845 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7117845 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4978027 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4978027 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92912 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 92912 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92835 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 92835 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 12095872 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 12095872 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 12095872 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 12095872 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023970 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.023970 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030151 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030151 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119446 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119446 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108224 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108224 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026513 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026513 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026513 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026513 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13881.139662 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13881.139662 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34253.193063 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34253.193063 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9575.644260 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9575.644260 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8691.350652 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8691.350652 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23415.387446 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23415.387446 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23415.387446 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23415.387446 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1045,66 +1045,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 265856 # number of writebacks -system.cpu1.dcache.writebacks::total 265856 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170577 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170577 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150060 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 150060 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11061 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11061 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10033 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10033 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 320637 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 320637 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 320637 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 320637 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1781497000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1781497000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4669562000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4669562000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68967000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 68967000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 45286000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 45286000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6451059000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6451059000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6451059000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6451059000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136551200000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136551200000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39714194000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714194000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176265394000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176265394000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023966 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023966 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030146 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030146 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119094 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119094 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108106 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108106 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026509 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026509 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026509 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026509 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10443.946136 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10443.946136 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31117.966147 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31117.966147 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6235.150529 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6235.150529 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4513.704774 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4513.704774 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20119.508977 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20119.508977 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20119.508977 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20119.508977 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 266082 # number of writebacks +system.cpu1.dcache.writebacks::total 266082 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170612 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170612 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150091 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 150091 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11098 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11098 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10038 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10038 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320703 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320703 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320703 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320703 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1855824122 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1855824122 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4690597670 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4690597670 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72957002 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72957002 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57198010 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57198010 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6546421792 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6546421792 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6546421792 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6546421792 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136480079000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136480079000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39677118500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39677118500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176157197500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176157197500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023970 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023970 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030151 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030151 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119446 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119446 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108127 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108127 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026513 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026513 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10877.453649 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10877.453649 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31251.691774 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31251.691774 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6573.887367 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6573.887367 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5698.148037 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5698.148037 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20412.723897 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20412.723897 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20412.723897 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20412.723897 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1126,10 +1122,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550273882646 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 550273882646 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550273882646 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 550273882646 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550047772786 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 550047772786 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550047772786 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 550047772786 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |