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authorAndreas Sandberg <andreas.sandberg@arm.com>2016-06-02 14:14:36 +0100
committerAndreas Sandberg <andreas.sandberg@arm.com>2016-06-02 14:14:36 +0100
commit1d933447fc62de67db938970a8308ac47189fd96 (patch)
treedf7f389eeae7916c3a58082644d6929bf0e94280 /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
parent660fbd543f7c84dec81cd17bdb4ff08f954aec77 (diff)
downloadgem5-1d933447fc62de67db938970a8308ac47189fd96.tar.xz
stats: Update to match ARM ISA changes
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout')
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
index 244ffaad4..b2ef01666 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
@@ -27,4 +27,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2909596171500 because m5_exit instruction encountered
+Exiting @ tick 2909586837500 because m5_exit instruction encountered