diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
| commit | 806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6 (patch) | |
| tree | bf8944a02c194cb657534276190f2a17859b3675 /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt | |
| parent | a9a7002a3b3ad1e423d16ace826e80574d4ddc4f (diff) | |
| download | gem5-806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6.tar.xz | |
stats: Update stats to reflect snoop-filter changes
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt | 1900 |
1 files changed, 948 insertions, 952 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 2f0ebe667..79e3a7b0a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.903468 # Number of seconds simulated -sim_ticks 2903467553500 # Number of ticks simulated -final_tick 2903467553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.909343 # Number of seconds simulated +sim_ticks 2909343316500 # Number of ticks simulated +final_tick 2909343316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 455888 # Simulator instruction rate (inst/s) -host_op_rate 549660 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11767164312 # Simulator tick rate (ticks/s) -host_mem_usage 571472 # Number of bytes of host memory used -host_seconds 246.74 # Real time elapsed on the host -sim_insts 112487279 # Number of instructions simulated -sim_ops 135624752 # Number of ops (including micro ops) simulated +host_inst_rate 666869 # Simulator instruction rate (inst/s) +host_op_rate 804035 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17251437084 # Simulator tick rate (ticks/s) +host_mem_usage 624248 # Number of bytes of host memory used +host_seconds 168.64 # Real time elapsed on the host +sim_insts 112463069 # Number of instructions simulated +sim_ops 135595282 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1189412 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9042916 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1184996 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8901092 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10233864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1189412 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1189412 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7647616 # Number of bytes written to this memory +system.physmem.bytes_read::total 10087624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1184996 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1184996 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7517376 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7665140 # Number of bytes written to this memory +system.physmem.bytes_written::total 7534900 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27038 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141815 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26969 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 139599 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168877 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 119494 # Number of write requests responded to by this memory +system.physmem.num_reads::total 166592 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117459 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123875 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121840 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 409652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3114523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3524704 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 409652 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 409652 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2633960 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6036 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2639995 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2633960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 407307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3059485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3467320 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 407307 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 407307 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2583874 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6023 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2589897 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2583874 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 409652 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3120558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6164699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168877 # Number of read requests accepted -system.physmem.writeReqs 123875 # Number of write requests accepted -system.physmem.readBursts 168877 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123875 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10799552 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8576 # Total number of bytes read from write queue -system.physmem.bytesWritten 7677760 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10233864 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7665140 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 134 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu.inst 407307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3065508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6057217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166592 # Number of read requests accepted +system.physmem.writeReqs 121840 # Number of write requests accepted +system.physmem.readBursts 166592 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121840 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10654272 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue +system.physmem.bytesWritten 7547776 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10087624 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7534900 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40733 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10018 # Per bank write bursts -system.physmem.perBankRdBursts::1 9658 # Per bank write bursts -system.physmem.perBankRdBursts::2 10300 # Per bank write bursts -system.physmem.perBankRdBursts::3 9945 # Per bank write bursts -system.physmem.perBankRdBursts::4 18863 # Per bank write bursts -system.physmem.perBankRdBursts::5 10091 # Per bank write bursts -system.physmem.perBankRdBursts::6 10302 # Per bank write bursts -system.physmem.perBankRdBursts::7 10601 # Per bank write bursts -system.physmem.perBankRdBursts::8 9921 # Per bank write bursts -system.physmem.perBankRdBursts::9 10207 # Per bank write bursts -system.physmem.perBankRdBursts::10 9962 # Per bank write bursts -system.physmem.perBankRdBursts::11 9026 # Per bank write bursts -system.physmem.perBankRdBursts::12 9868 # Per bank write bursts -system.physmem.perBankRdBursts::13 10473 # Per bank write bursts -system.physmem.perBankRdBursts::14 9981 # Per bank write bursts -system.physmem.perBankRdBursts::15 9527 # Per bank write bursts -system.physmem.perBankWrBursts::0 7412 # Per bank write bursts -system.physmem.perBankWrBursts::1 7255 # Per bank write bursts -system.physmem.perBankWrBursts::2 8123 # Per bank write bursts -system.physmem.perBankWrBursts::3 7537 # Per bank write bursts -system.physmem.perBankWrBursts::4 7355 # Per bank write bursts -system.physmem.perBankWrBursts::5 7348 # Per bank write bursts -system.physmem.perBankWrBursts::6 7577 # Per bank write bursts -system.physmem.perBankWrBursts::7 7905 # Per bank write bursts -system.physmem.perBankWrBursts::8 7603 # Per bank write bursts -system.physmem.perBankWrBursts::9 7853 # Per bank write bursts -system.physmem.perBankWrBursts::10 7551 # Per bank write bursts -system.physmem.perBankWrBursts::11 6940 # Per bank write bursts -system.physmem.perBankWrBursts::12 7397 # Per bank write bursts -system.physmem.perBankWrBursts::13 7831 # Per bank write bursts -system.physmem.perBankWrBursts::14 7359 # Per bank write bursts -system.physmem.perBankWrBursts::15 6919 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 40724 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10226 # Per bank write bursts +system.physmem.perBankRdBursts::1 9700 # Per bank write bursts +system.physmem.perBankRdBursts::2 10356 # Per bank write bursts +system.physmem.perBankRdBursts::3 10496 # Per bank write bursts +system.physmem.perBankRdBursts::4 18505 # Per bank write bursts +system.physmem.perBankRdBursts::5 10022 # Per bank write bursts +system.physmem.perBankRdBursts::6 10179 # Per bank write bursts +system.physmem.perBankRdBursts::7 10614 # Per bank write bursts +system.physmem.perBankRdBursts::8 9478 # Per bank write bursts +system.physmem.perBankRdBursts::9 10041 # Per bank write bursts +system.physmem.perBankRdBursts::10 9320 # Per bank write bursts +system.physmem.perBankRdBursts::11 9342 # Per bank write bursts +system.physmem.perBankRdBursts::12 9424 # Per bank write bursts +system.physmem.perBankRdBursts::13 10229 # Per bank write bursts +system.physmem.perBankRdBursts::14 9340 # Per bank write bursts +system.physmem.perBankRdBursts::15 9201 # Per bank write bursts +system.physmem.perBankWrBursts::0 7577 # Per bank write bursts +system.physmem.perBankWrBursts::1 7036 # Per bank write bursts +system.physmem.perBankWrBursts::2 7887 # Per bank write bursts +system.physmem.perBankWrBursts::3 8049 # Per bank write bursts +system.physmem.perBankWrBursts::4 7151 # Per bank write bursts +system.physmem.perBankWrBursts::5 7579 # Per bank write bursts +system.physmem.perBankWrBursts::6 7566 # Per bank write bursts +system.physmem.perBankWrBursts::7 7770 # Per bank write bursts +system.physmem.perBankWrBursts::8 7275 # Per bank write bursts +system.physmem.perBankWrBursts::9 7619 # Per bank write bursts +system.physmem.perBankWrBursts::10 6810 # Per bank write bursts +system.physmem.perBankWrBursts::11 7097 # Per bank write bursts +system.physmem.perBankWrBursts::12 7200 # Per bank write bursts +system.physmem.perBankWrBursts::13 7753 # Per bank write bursts +system.physmem.perBankWrBursts::14 6925 # Per bank write bursts +system.physmem.perBankWrBursts::15 6640 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 2903467231500 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 2909342872000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159305 # Read request sizes (log2) +system.physmem.readPktSize::6 157020 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 119494 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167939 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 544 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 248 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117459 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165675 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 258 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,159 +159,152 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 165 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 59281 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 311.689209 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.095727 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.740944 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21592 36.42% 36.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15113 25.49% 61.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5696 9.61% 71.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3272 5.52% 77.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2400 4.05% 81.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1627 2.74% 83.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1059 1.79% 85.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 986 1.66% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7536 12.71% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 59281 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5916 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.520960 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 582.774923 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5915 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58587 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 310.682984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.521208 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.535953 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21321 36.39% 36.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14587 24.90% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6073 10.37% 71.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3205 5.47% 77.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2612 4.46% 81.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1486 2.54% 84.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1112 1.90% 86.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1062 1.81% 87.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7129 12.17% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58587 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5766 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.870621 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 589.954659 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5765 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5916 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5916 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.278059 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.578317 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.228760 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5122 86.58% 86.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 35 0.59% 87.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 194 3.28% 90.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 61 1.03% 91.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 61 1.03% 92.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 181 3.06% 95.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.24% 95.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.08% 95.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 7 0.12% 96.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.08% 96.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.08% 96.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.12% 96.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 163 2.76% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.03% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 7 0.12% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 6 0.10% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 4 0.07% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.29% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5916 # Writes before turning the bus around for reads -system.physmem.totQLat 1515248250 # Total ticks spent queuing -system.physmem.totMemAccLat 4679179500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 843715000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8979.62 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5766 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5766 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.453347 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.695263 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.074003 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4962 86.06% 86.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 90 1.56% 87.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 33 0.57% 88.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 174 3.02% 91.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 30 0.52% 91.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 151 2.62% 94.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 46 0.80% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 5 0.09% 95.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 17 0.29% 95.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 15 0.26% 95.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 7 0.12% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.03% 95.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 166 2.88% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.09% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 8 0.14% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 26 0.45% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 17 0.29% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 4 0.07% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5766 # Writes before turning the bus around for reads +system.physmem.totQLat 1636363750 # Total ticks spent queuing +system.physmem.totMemAccLat 4757732500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 832365000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9829.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27729.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.64 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.64 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28579.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.59 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.93 # Average write queue length when enqueuing -system.physmem.readRowHits 138696 # Number of row buffer hits during reads -system.physmem.writeRowHits 90730 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.62 # Row buffer hit rate for writes -system.physmem.avgGap 9917839.10 # Average gap between requests -system.physmem.pageHitRate 79.46 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229068000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 124987500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 700268400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392117760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 189639989760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 87025634640 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1665738759750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1943850825810 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.494214 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2770947478500 # Time in different power states -system.physmem_0.memoryStateTime::REF 96952960000 # Time in different power states +system.physmem.avgWrQLen 26.26 # Average write queue length when enqueuing +system.physmem.readRowHits 136200 # Number of row buffer hits during reads +system.physmem.writeRowHits 89619 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.82 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.98 # Row buffer hit rate for writes +system.physmem.avgGap 10086754.84 # Average gap between requests +system.physmem.pageHitRate 79.39 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 229098240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125004000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 702764400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 392785200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 190023952560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 90217297485 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1666466226750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1948157128635 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.621597 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2772138232000 # Time in different power states +system.physmem_0.memoryStateTime::REF 97149260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35561301500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40052866750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 219096360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 119546625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 615919200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385255440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 189639989760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85786607970 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1666825625250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1943592040605 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.405084 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2772773591250 # Time in different power states -system.physmem_1.memoryStateTime::REF 96952960000 # Time in different power states +system.physmem_1.actEnergy 213819480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116667375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 595717200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 371427120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 190023952560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88066202985 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668353151750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1947740938470 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.478544 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2775299661000 # Time in different power states +system.physmem_1.memoryStateTime::REF 97149260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33740904250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 36894247500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -361,56 +354,55 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 9548 # Table walker walks requested -system.cpu.dtb.walker.walksShort 9548 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1269 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8279 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 9548 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 9548 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 9548 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7384 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 11763.949079 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 9756.046308 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7392.958780 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 5809 78.67% 78.67% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 1570 21.26% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7384 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 925393500 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 925393500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 925393500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6162 83.45% 83.45% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1222 16.55% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7384 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9548 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 9555 # Table walker walks requested +system.cpu.dtb.walker.walksShort 9555 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1270 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8285 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 9555 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 9555 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 9555 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7391 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 12962.724936 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 10716.855962 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8397.253568 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 7386 99.93% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.05% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7391 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 1638910500 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 1638910500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 1638910500 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6168 83.45% 83.45% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1223 16.55% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7391 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9555 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9548 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7384 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9555 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7391 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7384 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 16932 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7391 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 16946 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24527083 # DTB read hits -system.cpu.dtb.read_misses 8134 # DTB read misses -system.cpu.dtb.write_hits 19611642 # DTB write hits -system.cpu.dtb.write_misses 1414 # DTB write misses +system.cpu.dtb.read_hits 24521784 # DTB read hits +system.cpu.dtb.read_misses 8135 # DTB read misses +system.cpu.dtb.write_hits 19607400 # DTB write hits +system.cpu.dtb.write_misses 1420 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4269 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1680 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 1651 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24535217 # DTB read accesses -system.cpu.dtb.write_accesses 19613056 # DTB write accesses +system.cpu.dtb.read_accesses 24529919 # DTB read accesses +system.cpu.dtb.write_accesses 19608820 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44138725 # DTB hits -system.cpu.dtb.misses 9548 # DTB misses -system.cpu.dtb.accesses 44148273 # DTB accesses +system.cpu.dtb.hits 44129184 # DTB hits +system.cpu.dtb.misses 9555 # DTB misses +system.cpu.dtb.accesses 44138739 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -440,38 +432,36 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 4762 # Table walker walks requested -system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 309 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walks 4763 # Table walker walks requested +system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 11752.816221 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 9620.437143 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7446.323545 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1417 45.61% 45.61% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1012 32.57% 78.18% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 676 21.76% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 925066000 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 925066000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 925066000 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated +system.cpu.itb.walker.walkWaitTime::samples 4763 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12663.288288 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10495.066195 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7808.701731 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2418 77.80% 77.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 688 22.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 1638383000 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 1638383000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 1638383000 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2798 90.03% 90.03% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 310 9.97% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3108 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 115585268 # ITB inst hits -system.cpu.itb.inst_misses 4762 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 115560644 # ITB inst hits +system.cpu.itb.inst_misses 4763 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -487,38 +477,38 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115590030 # ITB inst accesses -system.cpu.itb.hits 115585268 # DTB hits -system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 115590030 # DTB accesses -system.cpu.numCycles 5806935107 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 115565407 # ITB inst accesses +system.cpu.itb.hits 115560644 # DTB hits +system.cpu.itb.misses 4763 # DTB misses +system.cpu.itb.accesses 115565407 # DTB accesses +system.cpu.numCycles 5818686633 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112487279 # Number of instructions committed -system.cpu.committedOps 135624752 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119926396 # Number of integer alu accesses +system.cpu.committedInsts 112463069 # Number of instructions committed +system.cpu.committedOps 135595282 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119900050 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses -system.cpu.num_func_calls 9895067 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15234125 # number of instructions that are conditional controls -system.cpu.num_int_insts 119926396 # number of integer instructions +system.cpu.num_func_calls 9893453 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15231190 # number of instructions that are conditional controls +system.cpu.num_int_insts 119900050 # number of integer instructions system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218121828 # number of times the integer registers were read -system.cpu.num_int_register_writes 82669566 # number of times the integer registers were written +system.cpu.num_int_register_reads 218076436 # number of times the integer registers were read +system.cpu.num_int_register_writes 82650791 # number of times the integer registers were written system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489877250 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51907763 # number of times the CC registers were written -system.cpu.num_mem_refs 45420046 # number of memory refs -system.cpu.num_load_insts 24850080 # Number of load instructions -system.cpu.num_store_insts 20569966 # Number of store instructions -system.cpu.num_idle_cycles 5385437399.888144 # Number of idle cycles -system.cpu.num_busy_cycles 421497707.111855 # Number of busy cycles -system.cpu.not_idle_fraction 0.072585 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.927415 # Percentage of idle cycles -system.cpu.Branches 25923230 # Number of branches fetched +system.cpu.num_cc_register_reads 489768723 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51897400 # number of times the CC registers were written +system.cpu.num_mem_refs 45409486 # number of memory refs +system.cpu.num_load_insts 24844046 # Number of load instructions +system.cpu.num_store_insts 20565440 # Number of store instructions +system.cpu.num_idle_cycles 5379802959.980151 # Number of idle cycles +system.cpu.num_busy_cycles 438883673.019849 # Number of busy cycles +system.cpu.not_idle_fraction 0.075427 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.924573 # Percentage of idle cycles +system.cpu.Branches 25918657 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93200379 67.17% 67.18% # Class of executed instruction -system.cpu.op_class::IntMult 114573 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93180998 67.17% 67.18% # Class of executed instruction +system.cpu.op_class::IntMult 114440 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -546,110 +536,110 @@ system.cpu.op_class::SimdFloatMisc 8455 0.01% 67.26% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24850080 17.91% 85.17% # Class of executed instruction -system.cpu.op_class::MemWrite 20569966 14.83% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24844046 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20565440 14.83% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138745790 # Class of executed instruction +system.cpu.op_class::total 138715716 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3030 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 820821 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.829842 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43246183 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 821333 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.653653 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 996611500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.829842 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999668 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999668 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 821347 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.702129 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43235829 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 821859 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.607356 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.702129 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999418 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999418 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177159261 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177159261 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23117842 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23117842 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18828857 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18828857 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392869 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392869 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443457 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443457 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460420 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460420 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41946699 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41946699 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42339568 # number of overall hits -system.cpu.dcache.overall_hits::total 42339568 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 401262 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 401262 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 298702 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 298702 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118314 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118314 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22748 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22748 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 177121649 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177121649 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23112263 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23112263 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18824569 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18824569 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 392807 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 392807 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443229 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443229 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460200 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460200 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41936832 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41936832 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42329639 # number of overall hits +system.cpu.dcache.overall_hits::total 42329639 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 401818 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 401818 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 298972 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 298972 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 118323 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 118323 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22757 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22757 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 699964 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 699964 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 818278 # number of overall misses -system.cpu.dcache.overall_misses::total 818278 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5968529500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5968529500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12574790000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12574790000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 282012000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 282012000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 700790 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 700790 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 819113 # number of overall misses +system.cpu.dcache.overall_misses::total 819113 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6512815000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6512815000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19103648000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19103648000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 294606000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 294606000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18543319500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18543319500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18543319500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18543319500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23519104 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23519104 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19127559 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19127559 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511183 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511183 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466205 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 466205 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460422 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460422 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42646663 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42646663 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43157846 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43157846 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017061 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.017061 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015616 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015616 # 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average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13910.384417 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13553.716097 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13553.716097 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25499.003266 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25499.003266 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23738.923670 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23738.923670 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189708.897951 # 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average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190659.595992 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190659.595992 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173673.039980 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173673.039980 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 182679.585199 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 182679.585199 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1698833 # number of replacements -system.cpu.icache.tags.tagsinuse 510.737457 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113885917 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1699345 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.017537 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 25666177500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.737457 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997534 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997534 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1696276 # number of replacements +system.cpu.icache.tags.tagsinuse 510.440576 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 113863850 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1696788 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.105525 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 28967481500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.440576 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996954 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 117284619 # Number of tag accesses -system.cpu.icache.tags.data_accesses 117284619 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 113885917 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113885917 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 113885917 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 113885917 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 113885917 # number of overall hits -system.cpu.icache.overall_hits::total 113885917 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1699351 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1699351 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1699351 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1699351 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1699351 # number of overall misses -system.cpu.icache.overall_misses::total 1699351 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23351891000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23351891000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23351891000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23351891000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23351891000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23351891000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115585268 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115585268 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115585268 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115585268 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115585268 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115585268 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014702 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014702 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014702 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014702 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014702 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014702 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13741.652549 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13741.652549 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13741.652549 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13741.652549 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13741.652549 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13741.652549 # average overall miss latency +system.cpu.icache.tags.tag_accesses 117257438 # Number of tag accesses +system.cpu.icache.tags.data_accesses 117257438 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 113863850 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113863850 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113863850 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113863850 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 113863850 # number of overall hits +system.cpu.icache.overall_hits::total 113863850 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1696794 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1696794 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1696794 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1696794 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1696794 # number of overall misses +system.cpu.icache.overall_misses::total 1696794 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24262817500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24262817500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24262817500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24262817500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24262817500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24262817500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 115560644 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 115560644 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 115560644 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 115560644 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 115560644 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 115560644 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014683 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014683 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014683 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014683 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014683 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014683 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14299.212220 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14299.212220 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14299.212220 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14299.212220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14299.212220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14299.212220 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -804,212 +794,212 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1699351 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1699351 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1699351 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1699351 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1699351 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1699351 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696794 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1696794 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1696794 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1696794 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1696794 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1696794 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21652540000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21652540000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21652540000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21652540000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21652540000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21652540000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 676974000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 676974000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 676974000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 676974000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014702 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014702 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014702 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12741.652549 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12741.652549 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12741.652549 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12741.652549 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12741.652549 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12741.652549 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75035.912215 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75035.912215 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75035.912215 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75035.912215 # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22566023500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22566023500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22566023500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22566023500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22566023500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22566023500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1142541000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 1142541000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014683 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014683 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014683 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014683 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014683 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014683 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13299.212220 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13299.212220 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13299.212220 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13299.212220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13299.212220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13299.212220 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 89784 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64924.949267 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4551273 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 155017 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 29.359832 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 87598 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64865.821065 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4548879 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 152768 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 29.776386 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50366.375395 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.807733 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012270 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9623.804573 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4930.949297 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.768530 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50190.412542 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.801705 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012642 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9659.374197 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5012.219980 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.765845 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # 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mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063749 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74642.857143 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 73000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74277.777778 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20795.429414 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20795.429414 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.434832 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.434832 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010581 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023362 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023362 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000900 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.171658 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.062853 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000900 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.171658 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062853 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 122777.777778 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70800.548446 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70800.548446 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66422.426361 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66422.426361 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70080.452755 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70080.452755 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72705.316558 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72705.316558 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74642.857143 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70080.452755 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66962.471482 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67311.133903 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74642.857143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70080.452755 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66962.471482 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67311.133903 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62535.912215 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177208.865840 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 151449.992531 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154209.665145 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154209.665145 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62535.912215 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166403.909017 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 152573.851058 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117148.641724 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117148.641724 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121367.271917 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121367.271917 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122269.562739 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122269.562739 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121367.271917 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117594.404752 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118020.597685 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121367.271917 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117594.404752 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118020.597685 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178159.563877 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163777.353088 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162173.039980 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162173.039980 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170649.352087 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 163124.038731 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 67206 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2292179 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27594 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27594 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 801878 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1805693 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2736 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 5058225 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2539566 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38059 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 583 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 583 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadReq 67216 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2289899 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 802569 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1801014 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2759 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2738 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699351 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 525637 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696794 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 525904 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5084414 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2579570 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12812 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24764 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7701560 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108793272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96436737 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14388 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27748 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205272145 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 179423 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5300588 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.035792 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.185771 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5077168 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2580972 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13250 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25621 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7697011 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108629432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96644509 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31124 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205321201 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 175948 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5294343 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018110 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.133351 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5110870 96.42% 96.42% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 189718 3.58% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5198460 98.19% 98.19% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 95883 1.81% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5300588 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3265127000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5294343 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3265837500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2558048500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2554213000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1278361999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1279146500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17827000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 17840000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30183 # Transaction distribution -system.iobus.trans_dist::ReadResp 30183 # Transaction distribution +system.iobus.trans_dist::ReadReq 30177 # Transaction distribution +system.iobus.trans_dist::ReadResp 30177 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1211,9 +1207,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -1236,9 +1232,9 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) @@ -1279,52 +1275,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 187438974 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186318027 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.134160 # Cycle average of tags in use +system.iocache.tags.replacements 36418 # number of replacements +system.iocache.tags.tagsinuse 1.083918 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 299040065000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.134160 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.070885 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.070885 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 313622510000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.083918 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067745 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067745 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328122 # Number of tag accesses -system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses -system.iocache.ReadReq_misses::total 234 # number of ReadReq misses +system.iocache.tags.tag_accesses 328068 # Number of tag accesses +system.iocache.tags.data_accesses 328068 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses +system.iocache.ReadReq_misses::total 228 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses -system.iocache.demand_misses::total 234 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 234 # number of overall misses -system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28776877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28776877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4271537097 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4271537097 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28776877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28776877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28776877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28776877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses +system.iocache.demand_misses::total 228 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 228 # number of overall misses +system.iocache.overall_misses::total 228 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28366877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28366877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4697294150 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4697294150 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28366877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28366877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28366877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28366877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1333,14 +1329,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 122978.106838 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122978.106838 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117920.083287 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 117920.083287 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 122978.106838 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122978.106838 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 122978.106838 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122978.106838 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 124416.127193 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124416.127193 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129673.535501 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129673.535501 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124416.127193 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124416.127193 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124416.127193 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124416.127193 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1351,22 +1347,22 @@ system.iocache.fast_writes 0 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17076877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17076877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2460337097 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2460337097 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17076877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17076877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17076877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17076877 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16966877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16966877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2886094150 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2886094150 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16966877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16966877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16966877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16966877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1375,68 +1371,68 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72978.106838 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72978.106838 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67920.083287 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67920.083287 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72978.106838 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72978.106838 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72978.106838 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72978.106838 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74416.127193 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74416.127193 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79673.535501 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79673.535501 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74416.127193 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74416.127193 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74416.127193 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74416.127193 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 40164 # Transaction distribution -system.membus.trans_dist::ReadResp 70750 # Transaction distribution -system.membus.trans_dist::WriteReq 27594 # Transaction distribution -system.membus.trans_dist::WriteResp 27594 # Transaction distribution -system.membus.trans_dist::Writeback 119494 # Transaction distribution -system.membus.trans_dist::CleanEvict 6493 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4509 # Transaction distribution +system.membus.trans_dist::ReadReq 40160 # Transaction distribution +system.membus.trans_dist::ReadResp 70632 # Transaction distribution +system.membus.trans_dist::WriteReq 27589 # Transaction distribution +system.membus.trans_dist::WriteResp 27589 # Transaction distribution +system.membus.trans_dist::Writeback 117459 # Transaction distribution +system.membus.trans_dist::CleanEvict 6342 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4500 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution -system.membus.trans_dist::ReadExReq 129215 # Transaction distribution -system.membus.trans_dist::ReadExResp 129215 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30586 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4502 # Transaction distribution +system.membus.trans_dist::ReadExReq 127038 # Transaction distribution +system.membus.trans_dist::ReadExResp 127038 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30472 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445567 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553177 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 662077 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438793 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546385 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 655279 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15581884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15745273 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15305404 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15468757 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18062393 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 394512 # Request fanout histogram +system.membus.pkt_size::total 17785877 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 492 # Total snoops (count) +system.membus.snoop_fanout::samples 390004 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 394512 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 390004 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 394512 # Request fanout histogram -system.membus.reqLayer0.occupancy 90495000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 390004 # Request fanout histogram +system.membus.reqLayer0.occupancy 90504500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1709000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1698500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 834776313 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 821932659 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 964479239 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 952275997 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64484992 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64458066 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1469,13 +1465,13 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks |