diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-02 06:08:25 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-02 06:08:25 -0500 |
| commit | 6489598fb449531c34bfb25a52189196ee2b1086 (patch) | |
| tree | 5f8bb88862ffd187cb7b182f4a0d20599b4409bf /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt | |
| parent | 966c3f4bc5581347a411c25db1440afb97f12dab (diff) | |
| download | gem5-6489598fb449531c34bfb25a52189196ee2b1086.tar.xz | |
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt | 1586 |
1 files changed, 796 insertions, 790 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 4e27b0ea0..5265a0ac0 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,123 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.902619 # Number of seconds simulated -sim_ticks 2902619131000 # Number of ticks simulated -final_tick 2902619131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.902845 # Number of seconds simulated +sim_ticks 2902845442000 # Number of ticks simulated +final_tick 2902845442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 783857 # Simulator instruction rate (inst/s) -host_op_rate 945096 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20223090080 # Simulator tick rate (ticks/s) -host_mem_usage 560080 # Number of bytes of host memory used -host_seconds 143.53 # Real time elapsed on the host -sim_insts 112507011 # Number of instructions simulated -sim_ops 135649580 # Number of ops (including micro ops) simulated +host_inst_rate 666753 # Simulator instruction rate (inst/s) +host_op_rate 803907 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17201244826 # Simulator tick rate (ticks/s) +host_mem_usage 558784 # Number of bytes of host memory used +host_seconds 168.76 # Real time elapsed on the host +sim_insts 112519801 # Number of instructions simulated +sim_ops 135665611 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1190564 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9003364 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1190500 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8985828 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10195464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1190564 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1190564 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5259520 # Number of bytes written to this memory +system.physmem.bytes_read::total 10177864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1190500 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1190500 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7575744 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory -system.physmem.bytes_written::total 7595380 # Number of bytes written to this memory +system.physmem.bytes_written::total 7593268 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27056 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141197 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 27055 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140923 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168277 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 82180 # Number of write requests responded to by this memory +system.physmem.num_reads::total 168002 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118371 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122785 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122752 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 410169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3101807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 410115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3095524 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3512505 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 410169 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 410169 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1811991 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3506168 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 410115 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 410115 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2609765 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6037 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 798705 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2616733 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1811991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2615802 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2609765 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 410169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3107844 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 799036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6129238 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168277 # Number of read requests accepted -system.physmem.writeReqs 122785 # Number of write requests accepted -system.physmem.readBursts 168277 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122785 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10758080 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11648 # Total number of bytes read from write queue -system.physmem.bytesWritten 7609472 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10195464 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7595380 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 182 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4505 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9709 # Per bank write bursts -system.physmem.perBankRdBursts::1 9253 # Per bank write bursts -system.physmem.perBankRdBursts::2 10215 # Per bank write bursts -system.physmem.perBankRdBursts::3 10266 # Per bank write bursts -system.physmem.perBankRdBursts::4 18988 # Per bank write bursts -system.physmem.perBankRdBursts::5 10225 # Per bank write bursts -system.physmem.perBankRdBursts::6 10580 # Per bank write bursts -system.physmem.perBankRdBursts::7 10353 # Per bank write bursts -system.physmem.perBankRdBursts::8 9698 # Per bank write bursts -system.physmem.perBankRdBursts::9 9938 # Per bank write bursts -system.physmem.perBankRdBursts::10 9924 # Per bank write bursts -system.physmem.perBankRdBursts::11 8855 # Per bank write bursts -system.physmem.perBankRdBursts::12 9985 # Per bank write bursts -system.physmem.perBankRdBursts::13 10410 # Per bank write bursts -system.physmem.perBankRdBursts::14 9933 # Per bank write bursts -system.physmem.perBankRdBursts::15 9763 # Per bank write bursts -system.physmem.perBankWrBursts::0 7210 # Per bank write bursts -system.physmem.perBankWrBursts::1 6831 # Per bank write bursts -system.physmem.perBankWrBursts::2 8029 # Per bank write bursts -system.physmem.perBankWrBursts::3 7890 # Per bank write bursts -system.physmem.perBankWrBursts::4 7400 # Per bank write bursts -system.physmem.perBankWrBursts::5 7418 # Per bank write bursts -system.physmem.perBankWrBursts::6 7750 # Per bank write bursts -system.physmem.perBankWrBursts::7 7625 # Per bank write bursts -system.physmem.perBankWrBursts::8 7363 # Per bank write bursts -system.physmem.perBankWrBursts::9 7566 # Per bank write bursts -system.physmem.perBankWrBursts::10 7503 # Per bank write bursts -system.physmem.perBankWrBursts::11 6751 # Per bank write bursts -system.physmem.perBankWrBursts::12 7436 # Per bank write bursts -system.physmem.perBankWrBursts::13 7741 # Per bank write bursts -system.physmem.perBankWrBursts::14 7284 # Per bank write bursts -system.physmem.perBankWrBursts::15 7101 # Per bank write bursts +system.physmem.bw_total::cpu.inst 410115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3101561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6121970 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168002 # Number of read requests accepted +system.physmem.writeReqs 158976 # Number of write requests accepted +system.physmem.readBursts 168002 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 158976 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10744064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue +system.physmem.bytesWritten 9803776 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10177864 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9911604 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5765 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4503 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9689 # Per bank write bursts +system.physmem.perBankRdBursts::1 9233 # Per bank write bursts +system.physmem.perBankRdBursts::2 10196 # Per bank write bursts +system.physmem.perBankRdBursts::3 10261 # Per bank write bursts +system.physmem.perBankRdBursts::4 18984 # Per bank write bursts +system.physmem.perBankRdBursts::5 10217 # Per bank write bursts +system.physmem.perBankRdBursts::6 10550 # Per bank write bursts +system.physmem.perBankRdBursts::7 10349 # Per bank write bursts +system.physmem.perBankRdBursts::8 9691 # Per bank write bursts +system.physmem.perBankRdBursts::9 9930 # Per bank write bursts +system.physmem.perBankRdBursts::10 9906 # Per bank write bursts +system.physmem.perBankRdBursts::11 8846 # Per bank write bursts +system.physmem.perBankRdBursts::12 9937 # Per bank write bursts +system.physmem.perBankRdBursts::13 10409 # Per bank write bursts +system.physmem.perBankRdBursts::14 9928 # Per bank write bursts +system.physmem.perBankRdBursts::15 9750 # Per bank write bursts +system.physmem.perBankWrBursts::0 9383 # Per bank write bursts +system.physmem.perBankWrBursts::1 8873 # Per bank write bursts +system.physmem.perBankWrBursts::2 10202 # Per bank write bursts +system.physmem.perBankWrBursts::3 10003 # Per bank write bursts +system.physmem.perBankWrBursts::4 9293 # Per bank write bursts +system.physmem.perBankWrBursts::5 9372 # Per bank write bursts +system.physmem.perBankWrBursts::6 9902 # Per bank write bursts +system.physmem.perBankWrBursts::7 9747 # Per bank write bursts +system.physmem.perBankWrBursts::8 9662 # Per bank write bursts +system.physmem.perBankWrBursts::9 9936 # Per bank write bursts +system.physmem.perBankWrBursts::10 9764 # Per bank write bursts +system.physmem.perBankWrBursts::11 9057 # Per bank write bursts +system.physmem.perBankWrBursts::12 9756 # Per bank write bursts +system.physmem.perBankWrBursts::13 9847 # Per bank write bursts +system.physmem.perBankWrBursts::14 9332 # Per bank write bursts +system.physmem.perBankWrBursts::15 9055 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 2902618754500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2902845065500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 158705 # Read request sizes (log2) +system.physmem.readPktSize::6 158430 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118404 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 571 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 256 # What read queue length does an incoming req see +system.physmem.writePktSize::6 154595 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 167074 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 244 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -162,157 +159,153 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58554 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 313.684599 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.640199 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.584074 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21469 36.67% 36.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14640 25.00% 61.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5516 9.42% 71.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3473 5.93% 77.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2278 3.89% 80.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1576 2.69% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 999 1.71% 85.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1064 1.82% 87.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7539 12.88% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58554 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5863 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.669452 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 558.899894 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5861 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 9728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 10886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 10725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 60629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 338.910027 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.312314 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 353.501529 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21458 35.39% 35.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14532 23.97% 59.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5550 9.15% 68.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3471 5.72% 74.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2318 3.82% 78.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1576 2.60% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1018 1.68% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1077 1.78% 84.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9629 15.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60629 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6199 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.078561 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 543.579220 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6197 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5863 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5863 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.279379 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.638132 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.466375 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5064 86.37% 86.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 42 0.72% 87.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 33 0.56% 87.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 216 3.68% 91.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 215 3.67% 95.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 12 0.20% 95.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 16 0.27% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.12% 95.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 25 0.43% 96.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 3 0.05% 96.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.10% 96.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.07% 96.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 164 2.80% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.07% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.05% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 2 0.03% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 13 0.22% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.03% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 5 0.09% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.05% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.14% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5863 # Writes before turning the bus around for reads -system.physmem.totQLat 1491102500 # Total ticks spent queuing -system.physmem.totMemAccLat 4642883750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 840475000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8870.59 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6199 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6199 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.711082 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.355367 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.633562 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 5127 82.71% 82.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 245 3.95% 86.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 162 2.61% 89.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 57 0.92% 90.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 142 2.29% 92.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 31 0.50% 92.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 44 0.71% 93.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 53 0.85% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 77 1.24% 95.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 20 0.32% 96.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 101 1.63% 97.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 12 0.19% 97.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 30 0.48% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 13 0.21% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 38 0.61% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 11 0.18% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 15 0.24% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.03% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 3 0.05% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 2 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 3 0.05% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 2 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6199 # Writes before turning the bus around for reads +system.physmem.totQLat 1496514000 # Total ticks spent queuing +system.physmem.totMemAccLat 4644189000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 839380000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8914.40 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27620.59 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s +system.physmem.avgMemAccLat 27664.40 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.70 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.38 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.62 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.41 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.72 # Average write queue length when enqueuing -system.physmem.readRowHits 138436 # Number of row buffer hits during reads -system.physmem.writeRowHits 90002 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.68 # Row buffer hit rate for writes -system.physmem.avgGap 9972510.17 # Average gap between requests -system.physmem.pageHitRate 79.59 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2755210874500 # Time in different power states -system.physmem.memoryStateTime::REF 96924620000 # Time in different power states +system.physmem.avgWrQLen 27.52 # Average write queue length when enqueuing +system.physmem.readRowHits 138272 # Number of row buffer hits during reads +system.physmem.writeRowHits 122158 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.73 # Row buffer hit rate for writes +system.physmem.avgGap 8877799.32 # Average gap between requests +system.physmem.pageHitRate 81.11 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2755332461750 # Time in different power states +system.physmem.memoryStateTime::REF 96932160000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 50483546000 # Time in different power states +system.physmem.memoryStateTime::ACT 50580729750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 226731960 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 215936280 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 123712875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 117822375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 698794200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 612339000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 389791440 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 380667600 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 189584556720 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 189584556720 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 86730297120 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 85558991580 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1665488607000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1666516068000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1943242491315 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1942986381555 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.480387 # Core power per rank (mW) -system.physmem.averagePower::1 669.392153 # Core power per rank (mW) +system.physmem.actEnergy::0 234216360 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 224138880 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 127796625 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 122298000 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 697936200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 611488800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 497502000 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 495130320 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 189599304960 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 189599304960 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 86744243025 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 85632450615 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1665611854500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1666587111000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1943512853670 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1943271922575 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.521448 # Core power per rank (mW) +system.physmem.averagePower::1 669.438449 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -355,25 +348,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24532671 # DTB read hits -system.cpu.dtb.read_misses 8148 # DTB read misses -system.cpu.dtb.write_hits 19614515 # DTB write hits +system.cpu.dtb.read_hits 24536392 # DTB read hits +system.cpu.dtb.read_misses 8144 # DTB read misses +system.cpu.dtb.write_hits 19617454 # DTB write hits system.cpu.dtb.write_misses 1410 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 4273 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 1630 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24540819 # DTB read accesses -system.cpu.dtb.write_accesses 19615925 # DTB write accesses +system.cpu.dtb.read_accesses 24544536 # DTB read accesses +system.cpu.dtb.write_accesses 19618864 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44147186 # DTB hits -system.cpu.dtb.misses 9558 # DTB misses -system.cpu.dtb.accesses 44156744 # DTB accesses +system.cpu.dtb.hits 44153846 # DTB hits +system.cpu.dtb.misses 9554 # DTB misses +system.cpu.dtb.accesses 44163400 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -395,7 +388,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 115605918 # ITB inst hits +system.cpu.itb.inst_hits 115618887 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -412,38 +405,38 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115610680 # ITB inst accesses -system.cpu.itb.hits 115605918 # DTB hits +system.cpu.itb.inst_accesses 115623649 # ITB inst accesses +system.cpu.itb.hits 115618887 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 115610680 # DTB accesses -system.cpu.numCycles 5805238262 # number of cpu cycles simulated +system.cpu.itb.accesses 115623649 # DTB accesses +system.cpu.numCycles 5805690884 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112507011 # Number of instructions committed -system.cpu.committedOps 135649580 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119948946 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses -system.cpu.num_func_calls 9898964 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15236406 # number of instructions that are conditional controls -system.cpu.num_int_insts 119948946 # number of integer instructions -system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218165471 # number of times the integer registers were read -system.cpu.num_int_register_writes 82686622 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read +system.cpu.committedInsts 112519801 # Number of instructions committed +system.cpu.committedOps 135665611 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119963928 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 11290 # Number of float alu accesses +system.cpu.num_func_calls 9899743 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15237612 # number of instructions that are conditional controls +system.cpu.num_int_insts 119963928 # number of integer instructions +system.cpu.num_fp_insts 11290 # number of float instructions +system.cpu.num_int_register_reads 218192496 # number of times the integer registers were read +system.cpu.num_int_register_writes 82697523 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8578 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489970666 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51914345 # number of times the CC registers were written -system.cpu.num_mem_refs 45428250 # number of memory refs -system.cpu.num_load_insts 24855398 # Number of load instructions -system.cpu.num_store_insts 20572852 # Number of store instructions -system.cpu.num_idle_cycles 5386458042.024144 # Number of idle cycles -system.cpu.num_busy_cycles 418780219.975856 # Number of busy cycles -system.cpu.not_idle_fraction 0.072138 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.927862 # Percentage of idle cycles -system.cpu.Branches 25929462 # Number of branches fetched +system.cpu.num_cc_register_reads 490031044 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51919223 # number of times the CC registers were written +system.cpu.num_mem_refs 45435185 # number of memory refs +system.cpu.num_load_insts 24859277 # Number of load instructions +system.cpu.num_store_insts 20575908 # Number of store instructions +system.cpu.num_idle_cycles 5386811452.570145 # Number of idle cycles +system.cpu.num_busy_cycles 418879431.429856 # Number of busy cycles +system.cpu.not_idle_fraction 0.072150 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.927850 # Percentage of idle cycles +system.cpu.Branches 25931479 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93218062 67.17% 67.18% # Class of executed instruction -system.cpu.op_class::IntMult 114523 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93227451 67.17% 67.17% # Class of executed instruction +system.cpu.op_class::IntMult 114534 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -467,24 +460,24 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Cl system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 8475 0.01% 67.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 8511 0.01% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24855398 17.91% 85.18% # Class of executed instruction -system.cpu.op_class::MemWrite 20572852 14.82% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24859277 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20575908 14.83% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138771647 # Class of executed instruction +system.cpu.op_class::total 138788018 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 822746 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.850534 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43252602 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 823258 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.538332 # Average number of references to valid blocks. +system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 823273 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.850546 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43258722 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 823785 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.512151 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.850534 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.850546 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -493,88 +486,88 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177194888 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177194888 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23122389 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23122389 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18831358 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18831358 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392121 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392121 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443546 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443546 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460444 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460444 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41953747 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41953747 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42345868 # number of overall hits -system.cpu.dcache.overall_hits::total 42345868 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 402166 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 402166 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 299026 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 299026 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 119155 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 119155 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22691 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22691 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 177222055 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177222055 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23125535 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23125535 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18834160 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18834160 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 392158 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 392158 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443620 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443620 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460509 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460509 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41959695 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41959695 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42351853 # number of overall hits +system.cpu.dcache.overall_hits::total 42351853 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 402606 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 402606 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 299098 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 299098 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 119172 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 119172 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22698 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22698 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 701192 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 701192 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 820347 # number of overall misses -system.cpu.dcache.overall_misses::total 820347 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5900442000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5900442000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658351003 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11658351003 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 279152000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 279152000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 53002 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17558793003 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17558793003 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17558793003 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17558793003 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23524555 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23524555 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19130384 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19130384 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511276 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511276 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466237 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 466237 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460446 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460446 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42654939 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42654939 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43166215 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43166215 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017096 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.017096 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015631 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015631 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.233054 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.233054 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048668 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048668 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 701704 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 701704 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 820876 # number of overall misses +system.cpu.dcache.overall_misses::total 820876 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5915644250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5915644250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11659723253 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11659723253 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280150250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 280150250 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 150000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17575367503 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17575367503 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17575367503 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17575367503 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23528141 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23528141 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19133258 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19133258 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511330 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511330 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466318 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 466318 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460511 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460511 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42661399 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42661399 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43172729 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43172729 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017112 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.017112 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015632 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015632 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.233063 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.233063 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048675 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048675 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016439 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016439 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019004 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019004 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14671.657972 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14671.657972 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38987.750239 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38987.750239 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12302.322507 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12302.322507 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26501 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25041.348166 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25041.348166 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.104608 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21404.104608 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.016448 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016448 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.019014 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.019014 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14693.383233 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14693.383233 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38982.952922 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38982.952922 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12342.508150 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12342.508150 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25046.697045 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25046.697045 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21410.502321 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21410.502321 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked @@ -583,78 +576,78 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.757576 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 686230 # number of writebacks -system.cpu.dcache.writebacks::total 686230 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 627 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 627 # number of ReadReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14222 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14222 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 627 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 627 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 627 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 627 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 401539 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 401539 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299026 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299026 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 117004 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 117004 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8469 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8469 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 686473 # number of writebacks +system.cpu.dcache.writebacks::total 686473 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 636 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 636 # number of ReadReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14226 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14226 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 636 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 636 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 636 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 636 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 401970 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 401970 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299098 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299098 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 117021 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 117021 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8472 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8472 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 700565 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 700565 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 817569 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 817569 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5083326500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5083326500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002800997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002800997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411190000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411190000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99471250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99471250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 48998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086127497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16086127497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497317497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17497317497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791402750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791402750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221080750 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080750 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017069 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017069 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015631 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228847 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228847 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018165 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018165 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 701068 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 701068 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 818089 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 818089 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5096620250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5096620250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11004051747 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11004051747 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1414370750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1414370750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99646250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99646250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16100671997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16100671997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17515042747 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17515042747 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791399500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791399500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221078000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221078000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017085 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017085 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015632 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015632 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228856 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228856 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018168 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018168 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016424 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016424 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018940 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12659.608407 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12659.608407 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.465936 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.465936 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12061.040648 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12061.040648 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11745.335931 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11745.335931 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22961.648808 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22961.648808 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21401.640103 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21401.640103 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016433 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016433 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018949 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.018949 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12679.106028 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12679.106028 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36790.790132 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36790.790132 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12086.469523 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12086.469523 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11761.833097 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11761.833097 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22965.920563 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22965.920563 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21409.703280 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21409.703280 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -662,13 +655,13 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1699818 # number of replacements -system.cpu.icache.tags.tagsinuse 510.781939 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113905582 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1700330 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 66.990280 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1700967 # number of replacements +system.cpu.icache.tags.tagsinuse 510.782035 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 113917402 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1701479 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 66.951988 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 25181626250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.781939 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.782035 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997621 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.997621 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -677,44 +670,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 195 system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 117306254 # Number of tag accesses -system.cpu.icache.tags.data_accesses 117306254 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 113905582 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113905582 # 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miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014708 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014708 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014708 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014708 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13669.488560 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13669.488560 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13669.488560 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13669.488560 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13669.488560 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13669.488560 # average overall miss latency +system.cpu.icache.tags.tag_accesses 117320372 # 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number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23258305750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23258305750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23258305750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23258305750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23258305750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23258305750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 115618887 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 115618887 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 115618887 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 115618887 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 115618887 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 115618887 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014716 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014716 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014716 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014716 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014716 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014716 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13669.415687 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13669.415687 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13669.415687 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13669.415687 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13669.415687 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13669.415687 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -723,196 +716,196 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700336 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1700336 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1700336 # 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Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65261 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2131 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6951 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56138 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2127 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6954 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56136 # 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mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000985 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000540 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010609 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172995 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063318 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000985 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000540 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010609 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172995 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063318 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.439466 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.439466 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001003 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010603 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172890 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063283 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001003 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010603 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172890 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063283 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 66714.285714 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60233.882144 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62847.038799 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61289.493700 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10011.297904 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10011.297904 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56458.769025 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56458.769025 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60265.451774 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63809.880240 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61695.998677 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10058.458564 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10058.458564 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.475107 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.475107 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 66714.285714 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60233.882144 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57005.575064 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57369.049092 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60265.451774 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57088.613350 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57446.217834 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 66714.285714 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60233.882144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57005.575064 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57369.049092 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60265.451774 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57088.613350 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57446.217834 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1024,59 +1017,60 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2294825 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2294810 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2296418 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2296403 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 686230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2742 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 686473 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2738 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2744 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296284 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296284 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418692 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2456073 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12917 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24956 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5912638 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96806921 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 28416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205706201 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 52963 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3276132 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.011129 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.104904 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2740 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296360 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296360 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3420989 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2457362 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12875 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24821 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5916047 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108929528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96856201 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205828273 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 53126 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3278039 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.011122 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.104872 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3239673 98.89% 98.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 36459 1.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3241581 98.89% 98.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 36458 1.11% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3276132 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2353772500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3278039 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2354969500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2564911000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2566643750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1311851755 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1312602003 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17852250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 17845000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30195 # Transaction distribution system.iobus.trans_dist::ReadResp 30195 # Transaction distribution system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -1167,42 +1161,44 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347056142 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36805009 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36804505 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.133398 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.134557 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 298397241000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.133398 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.070837 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.070837 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 298397320000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.134557 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.070910 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.070910 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328122 # Number of tag accesses system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses system.iocache.ReadReq_misses::total 234 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28038377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28038377 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28038377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28038377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28038377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28038377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9588161260 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9588161260 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28034377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1213,104 +1209,114 @@ system.iocache.overall_accesses::realview.ide 234 system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 119822.123932 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119822.123932 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 119822.123932 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119822.123932 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 119822.123932 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119822.123932 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264690.847504 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264690.847504 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 55275 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7147 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.734014 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 36224 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 15869377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 15869377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2206856981 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2206856981 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 15869377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 15869377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 15869377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 15869377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7704503270 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7704503270 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 15865377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67817.850427 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67817.850427 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 67817.850427 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 67817.850427 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 67817.850427 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 67817.850427 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212690.571720 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212690.571720 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 70649 # Transaction distribution -system.membus.trans_dist::ReadResp 70649 # Transaction distribution +system.membus.trans_dist::ReadReq 70650 # Transaction distribution +system.membus.trans_dist::ReadResp 70650 # Transaction distribution system.membus.trans_dist::WriteReq 27618 # Transaction distribution system.membus.trans_dist::WriteResp 27618 # Transaction distribution -system.membus.trans_dist::Writeback 82180 # Transaction distribution +system.membus.trans_dist::Writeback 118371 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution -system.membus.trans_dist::ReadExReq 128451 # Transaction distribution -system.membus.trans_dist::ReadExResp 128451 # Transaction distribution +system.membus.trans_dist::ReadExReq 128452 # Transaction distribution +system.membus.trans_dist::ReadExResp 128452 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436476 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 616855 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436202 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543884 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 652771 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15471548 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635009 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17954305 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 219 # Total snoops (count) -system.membus.snoop_fanout::samples 281834 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15454012 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15617473 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20252929 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 498 # Total snoops (count) +system.membus.snoop_fanout::samples 318026 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 281834 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 318026 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 281834 # Request fanout histogram -system.membus.reqLayer0.occupancy 86774000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 318026 # Request fanout histogram +system.membus.reqLayer0.occupancy 86773500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1752500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1756500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1264017500 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1594856995 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1589715500 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 1594842247 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38339991 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38335495 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |