ARM: Update stats for IT and conditional branch changes

3 files changed, 82 insertions, 82 deletions

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index 064eb9907..cb6ee4aa9 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -189,7 +189,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 
 [system.iocache]
@@ -283,7 +283,7 @@ port=system.membus.master[2]
 
 [system.realview]
 type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
 intrctrl=system.intrctrl
 max_mem_size=268435456
 mem_start_addr=0
@@ -523,13 +523,16 @@ proc_id1=201327138
 system=system
 pio=system.iobus.master[1]
 
-[system.realview.rtc_fake]
-type=AmbaFake
-amba_id=266289
-ignore_access=false
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+gic=system.realview.gic
+int_delay=100000
+int_num=42
 pio_addr=268529664
 pio_latency=1000
 system=system
+time=Thu Jan  1 00:00:00 2009
 pio=system.iobus.master[23]
 
 [system.realview.sci_fake]
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
index c88a5bef6..1758a0df6 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
@@ -1,13 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar  9 2012 08:32:03
-gem5 started Mar  9 2012 08:33:32
+gem5 compiled Mar 17 2012 11:46:05
+gem5 started Mar 17 2012 16:35:38
 gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
-The currently selected ARM platforms doesn't support
- the amount of DRAM you've selected. Please try
- another platform
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index e62e718fc..2c94df23b 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -4,13 +4,13 @@ sim_seconds                                  2.591442                       # Nu
 sim_ticks                                2591441692000                       # Number of ticks simulated
 final_tick                               2591441692000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 886915                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1133159                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            38905818967                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 380156                       # Number of bytes of host memory used
-host_seconds                                    66.61                       # Real time elapsed on the host
-sim_insts                                    59075683                       # Number of instructions simulated
-sim_ops                                      75477515                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 879685                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1123921                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            38588641896                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 377580                       # Number of bytes of host memory used
+host_seconds                                    67.16                       # Real time elapsed on the host
+sim_insts                                    59075703                       # Number of instructions simulated
+sim_ops                                      75477535                       # Number of ops (including micro ops) simulated
 system.realview.nvmem.bytes_read                   20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read              20                       # Number of instructions bytes read from this memory
 system.realview.nvmem.bytes_written                 0                       # Number of bytes written to this memory
@@ -31,22 +31,22 @@ system.physmem.bw_inst_read                    366560                       # In
 system.physmem.bw_write                       3717742                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total                      55293438                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        117809                       # number of replacements
-system.l2c.tagsinuse                     24928.376904                       # Cycle average of tags in use
-system.l2c.total_refs                         1535240                       # Total number of references to valid blocks.
+system.l2c.tagsinuse                     24929.234619                       # Cycle average of tags in use
+system.l2c.total_refs                         1535239                       # Total number of references to valid blocks.
 system.l2c.sampled_refs                        146709                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         10.464525                       # Average number of references to valid blocks.
+system.l2c.avg_refs                         10.464518                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        14588.908220                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks        14588.908290                       # Average occupied blocks per requestor
 system.l2c.occ_blocks::cpu.dtb.walker        6.963925                       # Average occupied blocks per requestor
 system.l2c.occ_blocks::cpu.itb.walker        0.970411                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           5158.445831                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data           5173.088517                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           5159.303507                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           5173.088486                       # Average occupied blocks per requestor
 system.l2c.occ_percent::writebacks           0.222609                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu.dtb.walker       0.000106                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu.itb.walker       0.000015                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.078712                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst             0.078725                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu.data             0.078935                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.380377                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.380390                       # Average percentage of cache occupancy
 system.l2c.ReadReq_hits::cpu.dtb.walker          8825                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu.itb.walker          3670                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu.inst              837469                       # number of ReadReq hits
@@ -253,9 +253,9 @@ system.cf0.dma_write_bytes                          0                       # Nu
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     14970647                       # DTB read hits
+system.cpu.dtb.read_hits                     14970649                       # DTB read hits
 system.cpu.dtb.read_misses                       7343                       # DTB read misses
-system.cpu.dtb.write_hits                    11215605                       # DTB write hits
+system.cpu.dtb.write_hits                    11215606                       # DTB write hits
 system.cpu.dtb.write_misses                      2208                       # DTB write misses
 system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
@@ -266,13 +266,13 @@ system.cpu.dtb.align_faults                         0                       # Nu
 system.cpu.dtb.prefetch_faults                    183                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                       452                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 14977990                       # DTB read accesses
-system.cpu.dtb.write_accesses                11217813                       # DTB write accesses
+system.cpu.dtb.read_accesses                 14977992                       # DTB read accesses
+system.cpu.dtb.write_accesses                11217814                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          26186252                       # DTB hits
+system.cpu.dtb.hits                          26186255                       # DTB hits
 system.cpu.dtb.misses                            9551                       # DTB misses
-system.cpu.dtb.accesses                      26195803                       # DTB accesses
-system.cpu.itb.inst_hits                     60357722                       # ITB inst hits
+system.cpu.dtb.accesses                      26195806                       # DTB accesses
+system.cpu.itb.inst_hits                     60357742                       # ITB inst hits
 system.cpu.itb.inst_misses                       4471                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
@@ -289,49 +289,49 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 60362193                       # ITB inst accesses
-system.cpu.itb.hits                          60357722                       # DTB hits
+system.cpu.itb.inst_accesses                 60362213                       # ITB inst accesses
+system.cpu.itb.hits                          60357742                       # DTB hits
 system.cpu.itb.misses                            4471                       # DTB misses
-system.cpu.itb.accesses                      60362193                       # DTB accesses
+system.cpu.itb.accesses                      60362213                       # DTB accesses
 system.cpu.numCycles                       5182883384                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    59075683                       # Number of instructions committed
-system.cpu.committedOps                      75477515                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              68255270                       # Number of integer alu accesses
+system.cpu.committedInsts                    59075703                       # Number of instructions committed
+system.cpu.committedOps                      75477535                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              68255288                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  10269                       # Number of float alu accesses
 system.cpu.num_func_calls                     1975579                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      7801778                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     68255270                       # number of integer instructions
+system.cpu.num_conditional_control_insts      7643992                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     68255288                       # number of integer instructions
 system.cpu.num_fp_insts                         10269                       # number of float instructions
-system.cpu.num_int_register_reads           390835391                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           72984158                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           390835490                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           72984180                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                 7493                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                2780                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      27351734                       # number of memory refs
-system.cpu.num_load_insts                    15632521                       # Number of load instructions
-system.cpu.num_store_insts                   11719213                       # Number of store instructions
-system.cpu.num_idle_cycles               4574345772.482235                       # Number of idle cycles
-system.cpu.num_busy_cycles               608537611.517765                       # Number of busy cycles
+system.cpu.num_mem_refs                      27351737                       # number of memory refs
+system.cpu.num_load_insts                    15632523                       # Number of load instructions
+system.cpu.num_store_insts                   11719214                       # Number of store instructions
+system.cpu.num_idle_cycles               4574345726.482235                       # Number of idle cycles
+system.cpu.num_busy_cycles               608537657.517765                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.117413                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.882587                       # Percentage of idle cycles
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                    82953                       # number of quiesce instructions executed
 system.cpu.icache.replacements                 852971                       # number of replacements
 system.cpu.icache.tagsinuse                510.943281                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 59504239                       # Total number of references to valid blocks.
+system.cpu.icache.total_refs                 59504259                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                 853483                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  69.719302                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle            18512998000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.avg_refs                  69.719325                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle            18513021000                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.occ_blocks::cpu.inst     510.943281                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.997936                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.997936                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     59504239                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        59504239                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      59504239                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         59504239                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     59504239                       # number of overall hits
-system.cpu.icache.overall_hits::total        59504239                       # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst     59504259                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        59504259                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      59504259                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         59504259                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     59504259                       # number of overall hits
+system.cpu.icache.overall_hits::total        59504259                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst       853483                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total        853483                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst       853483                       # number of demand (read+write) misses
@@ -344,12 +344,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst  12547128000
 system.cpu.icache.demand_miss_latency::total  12547128000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst  12547128000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total  12547128000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     60357722                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     60357722                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     60357722                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     60357722                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     60357722                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     60357722                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst     60357742                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     60357742                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     60357742                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     60357742                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     60357742                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     60357742                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014140                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.014140                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.014140                       # miss rate for overall accesses
@@ -393,25 +393,25 @@ system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 626903                       # number of replacements
 system.cpu.dcache.tagsinuse                511.875592                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 23615096                       # Total number of references to valid blocks.
+system.cpu.dcache.total_refs                 23615099                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                 627415                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  37.638718                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  37.638722                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              660309000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.occ_blocks::cpu.data     511.875592                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.999757                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.999757                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     13170367                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13170367                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      9958094                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        9958094                       # number of WriteReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data     13170369                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13170369                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      9958095                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        9958095                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data       236142                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total       236142                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data       247592                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total       247592                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      23128461                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         23128461                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     23128461                       # number of overall hits
-system.cpu.dcache.overall_hits::total        23128461                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data      23128464                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         23128464                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     23128464                       # number of overall hits
+system.cpu.dcache.overall_hits::total        23128464                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data       368563                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total        368563                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data       250302                       # number of WriteReq misses
@@ -432,18 +432,18 @@ system.cpu.dcache.demand_miss_latency::cpu.data  15398067500
 system.cpu.dcache.demand_miss_latency::total  15398067500                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data  15398067500                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total  15398067500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     13538930                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13538930                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10208396                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10208396                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data     13538932                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     13538932                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10208397                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10208397                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247593                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total       247593                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data       247592                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total       247592                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     23747326                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     23747326                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     23747326                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     23747326                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     23747329                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     23747329                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     23747329                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     23747329                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.027222                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024519                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046249                       # miss rate for LoadLockedReq accesses