diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
| commit | 74553c7d3fc5430752c0c08f2b319a99fb7ed632 (patch) | |
| tree | 79b2a309fff0edaf1ef3e9aa62656904c3351650 /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing | |
| parent | 3bc4ecdcb4785a976a1c3fd463bf7052b8415d8b (diff) | |
| download | gem5-74553c7d3fc5430752c0c08f2b319a99fb7ed632.tar.xz | |
stats: Update the stats to reflect bus and memory changes
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt | 1713 |
1 files changed, 1120 insertions, 593 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 4975edc6e..934a4cb6c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,129 +1,129 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.603674 # Number of seconds simulated -sim_ticks 2603674284000 # Number of ticks simulated -final_tick 2603674284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.615622 # Number of seconds simulated +sim_ticks 2615622384000 # Number of ticks simulated +final_tick 2615622384000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 271279 # Simulator instruction rate (inst/s) -host_op_rate 345198 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11733407598 # Simulator tick rate (ticks/s) -host_mem_usage 403640 # Number of bytes of host memory used -host_seconds 221.90 # Real time elapsed on the host -sim_insts 60197457 # Number of instructions simulated -sim_ops 76600355 # Number of ops (including micro ops) simulated +host_inst_rate 264818 # Simulator instruction rate (inst/s) +host_op_rate 336993 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11506330329 # Simulator tick rate (ticks/s) +host_mem_usage 396436 # Number of bytes of host memory used +host_seconds 227.32 # Real time elapsed on the host +sim_insts 60198587 # Number of instructions simulated +sim_ops 76605405 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9050192 # Number of bytes read from this memory -system.physmem.bytes_read::total 132439216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3677632 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093200 # Number of bytes read from this memory +system.physmem.bytes_read::total 132481840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3709760 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6693704 # Number of bytes written to this memory +system.physmem.bytes_written::total 6725832 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494095 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57463 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142115 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494761 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57965 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811481 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47119332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 270817 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3475931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50866276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 270817 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 270817 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1412478 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1158391 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2570868 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1412478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47119332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 270817 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4634322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53437145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494095 # Total number of read requests seen -system.physmem.writeReqs 811481 # Total number of write requests seen -system.physmem.cpureqs 213992 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 991622080 # Total number of bytes read from memory -system.physmem.bytesWritten 51934784 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132439216 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6693704 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 974844 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 967900 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 967764 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 968566 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 968387 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 967635 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 967737 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 968249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 968100 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 967668 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 967710 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 968007 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 968101 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 967570 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 967434 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 968087 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50753 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50356 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50308 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51002 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50784 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50139 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50212 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50710 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51142 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50724 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51058 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50650 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50587 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51214 # Track writes on a per bank basis +system.physmem.num_writes::total 811983 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46904092 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 269458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3476496 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50650216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 269458 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269458 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1418309 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1153099 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2571408 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1418309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46904092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 269458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4629595 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53221624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494761 # Total number of read requests seen +system.physmem.writeReqs 811983 # Total number of write requests seen +system.physmem.cpureqs 215166 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 991664704 # Total number of bytes read from memory +system.physmem.bytesWritten 51966912 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 132481840 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6725832 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 301 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4516 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 968108 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 967904 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 967765 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 967946 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 974722 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 968494 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 967971 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 967832 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 968523 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 968301 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 967958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 967809 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 967930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 967629 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 967885 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 967683 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 49010 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50853 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50913 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51127 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51430 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51246 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51368 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50878 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50797 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 50871 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50522 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50825 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 50676 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2603669924000 # Total gap between requests +system.physmem.totGap 2615618000000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6652 # Categorize read packet sizes system.physmem.readPktSize::3 15335424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152019 # Categorize read packet sizes +system.physmem.readPktSize::6 152685 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 57463 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1115862 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 960938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 976049 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3645924 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2755202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2757935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2724600 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 64133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 62351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 112886 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 163253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 112534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10838 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 10625 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 10165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 93 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57965 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1126555 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 973164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1018253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3775658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2831038 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2826406 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2774250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 21901 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 19136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 31670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 43534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 30921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 5697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 5598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5184 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 40 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -139,59 +139,340 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 341488215750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 436408620750 # Sum of mem lat for all requests -system.physmem.totBusLat 77468795000 # Total cycles spent in databus access -system.physmem.totBankLat 17451610000 # Total cycles spent in bank access -system.physmem.avgQLat 22040.37 # Average queueing delay per request -system.physmem.avgBankLat 1126.36 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 38567 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 27059.676926 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2495.376643 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 33105.439598 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-127 5489 14.23% 14.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-191 3331 8.64% 22.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-255 2176 5.64% 28.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-319 1697 4.40% 32.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-383 1162 3.01% 35.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-447 1046 2.71% 38.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-511 828 2.15% 40.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-575 748 1.94% 42.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-639 582 1.51% 44.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-703 509 1.32% 45.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-767 411 1.07% 46.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-831 479 1.24% 47.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-895 285 0.74% 48.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-959 248 0.64% 49.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-1023 187 0.48% 49.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1087 239 0.62% 50.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1151 141 0.37% 50.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1215 137 0.36% 51.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1279 106 0.27% 51.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1343 105 0.27% 51.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1407 92 0.24% 51.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1471 151 0.39% 52.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1535 970 2.52% 54.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1599 203 0.53% 55.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1663 135 0.35% 55.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1727 110 0.29% 55.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1791 91 0.24% 56.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1855 77 0.20% 56.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1919 66 0.17% 56.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1983 47 0.12% 56.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2047 51 0.13% 56.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2111 64 0.17% 56.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2175 37 0.10% 57.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2239 25 0.06% 57.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2303 18 0.05% 57.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2367 25 0.06% 57.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2431 26 0.07% 57.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2495 13 0.03% 57.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2559 25 0.06% 57.39% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38975 1 0.00% 60.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39999 2 0.01% 60.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42303 1 0.00% 60.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42559 2 0.01% 60.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43071 1 0.00% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43583 1 0.00% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45119 1 0.00% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45631 1 0.00% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46143 1 0.00% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47423 1 0.00% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48191 1 0.00% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49215 2 0.01% 60.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49664-49727 2 0.01% 60.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50239 1 0.00% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51263 1 0.00% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52480-52543 1 0.00% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52992-53055 1 0.00% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56320-56383 3 0.01% 60.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57088-57151 1 0.00% 60.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59392-59455 1 0.00% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60416-60479 2 0.01% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61440-61503 1 0.00% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63488-63551 2 0.01% 60.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63808-63871 1 0.00% 60.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64512-64575 1 0.00% 60.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65087 19 0.05% 60.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65088-65151 6 0.02% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65152-65215 2 0.01% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65343 6 0.02% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65344-65407 6 0.02% 60.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65408-65471 14 0.04% 60.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65535 6 0.02% 60.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65599 14789 38.35% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::71360-71423 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73984-74047 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::83008-83071 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::85504-85567 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::93120-93183 1 0.00% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::97152-97215 1 0.00% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::97408-97471 1 0.00% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::100672-100735 1 0.00% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::103680-103743 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::104768-104831 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::106432-106495 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::109760-109823 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::110848-110911 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::110912-110975 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::114240-114303 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::115328-115391 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::116992-117055 1 0.00% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::120320-120383 1 0.00% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::121408-121471 1 0.00% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::121472-121535 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::124416-124479 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::127552-127615 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128640-128703 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130176-130239 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130368-130431 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130432-130495 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130496-130559 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130624-130687 1 0.00% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130688-130751 1 0.00% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130880-130943 1 0.00% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131135 328 0.85% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::136576-136639 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::161408-161471 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::190336-190399 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196032-196095 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196608-196671 2 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38567 # Bytes accessed per row activation +system.physmem.totQLat 306544443250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 400266823250 # Sum of mem lat for all requests +system.physmem.totBusLat 77472300000 # Total cycles spent in databus access +system.physmem.totBankLat 16250080000 # Total cycles spent in bank access +system.physmem.avgQLat 19784.13 # Average queueing delay per request +system.physmem.avgBankLat 1048.77 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28166.74 # Average memory access latency -system.physmem.avgRdBW 380.85 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 25832.90 # Average memory access latency +system.physmem.avgRdBW 379.13 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 19.87 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 50.65 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.13 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 12.40 # Average write queue length over time -system.physmem.readRowHits 15418728 # Number of row buffer hits during reads -system.physmem.writeRowHits 794030 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes -system.physmem.avgGap 159679.73 # Average gap between requests +system.physmem.busUtil 3.12 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 10.80 # Average write queue length over time +system.physmem.readRowHits 15469403 # Number of row buffer hits during reads +system.physmem.writeRowHits 798459 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 98.33 # Row buffer hit rate for writes +system.physmem.avgGap 160401.00 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -204,34 +485,248 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54138467 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16546589 # Transaction distribution +system.membus.trans_dist::ReadResp 16546589 # Transaction distribution +system.membus.trans_dist::WriteReq 763368 # Transaction distribution +system.membus.trans_dist::WriteResp 763368 # Transaction distribution +system.membus.trans_dist::Writeback 57965 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution +system.membus.trans_dist::ReadExReq 132246 # Transaction distribution +system.membus.trans_dist::ReadExResp 132246 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893707 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280555 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 32564555 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34951403 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16524280 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18922393 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 139207672 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 141605785 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141605785 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1206150500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 17904777500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer3.occupancy 3613000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4945376509 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 34635651750 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.iobus.throughput 47817981 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16518751 # Transaction distribution +system.iobus.trans_dist::ReadResp 16518751 # Transaction distribution +system.iobus.trans_dist::WriteReq 8166 # Transaction distribution +system.iobus.trans_dist::WriteResp 8166 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33053834 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 125073781 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 125073781 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374820000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 30670848000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14995645 # DTB read hits -system.cpu.dtb.read_misses 7332 # DTB read misses -system.cpu.dtb.write_hits 11230857 # DTB write hits -system.cpu.dtb.write_misses 2203 # DTB write misses +system.cpu.dtb.read_hits 14996055 # DTB read hits +system.cpu.dtb.read_misses 7342 # DTB read misses +system.cpu.dtb.write_hits 11230429 # DTB write hits +system.cpu.dtb.write_misses 2216 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15002977 # DTB read accesses -system.cpu.dtb.write_accesses 11233060 # DTB write accesses +system.cpu.dtb.read_accesses 15003397 # DTB read accesses +system.cpu.dtb.write_accesses 11232645 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226502 # DTB hits -system.cpu.dtb.misses 9535 # DTB misses -system.cpu.dtb.accesses 26236037 # DTB accesses -system.cpu.itb.inst_hits 61491397 # ITB inst hits +system.cpu.dtb.hits 26226484 # DTB hits +system.cpu.dtb.misses 9558 # DTB misses +system.cpu.dtb.accesses 26236042 # DTB accesses +system.cpu.itb.inst_hits 61492425 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -248,79 +743,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61495868 # ITB inst accesses -system.cpu.itb.hits 61491397 # DTB hits +system.cpu.itb.inst_accesses 61496896 # ITB inst accesses +system.cpu.itb.hits 61492425 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61495868 # DTB accesses -system.cpu.numCycles 5207348568 # number of cpu cycles simulated +system.cpu.itb.accesses 61496896 # DTB accesses +system.cpu.numCycles 5231244768 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60197457 # Number of instructions committed -system.cpu.committedOps 76600355 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68868122 # Number of integer alu accesses +system.cpu.committedInsts 60198587 # Number of instructions committed +system.cpu.committedOps 76605405 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68872209 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2139722 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7947784 # number of instructions that are conditional controls -system.cpu.num_int_insts 68868122 # number of integer instructions +system.cpu.num_func_calls 2140451 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7948368 # number of instructions that are conditional controls +system.cpu.num_int_insts 68872209 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394755172 # number of times the integer registers were read -system.cpu.num_int_register_writes 74176013 # number of times the integer registers were written +system.cpu.num_int_register_reads 394776354 # number of times the integer registers were read +system.cpu.num_int_register_writes 74181797 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27393871 # number of memory refs -system.cpu.num_load_insts 15659652 # Number of load instructions -system.cpu.num_store_insts 11734219 # Number of store instructions -system.cpu.num_idle_cycles 4579092042.576241 # Number of idle cycles -system.cpu.num_busy_cycles 628256525.423759 # Number of busy cycles -system.cpu.not_idle_fraction 0.120648 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.879352 # Percentage of idle cycles +system.cpu.num_mem_refs 27393915 # number of memory refs +system.cpu.num_load_insts 15660071 # Number of load instructions +system.cpu.num_store_insts 11733844 # Number of store instructions +system.cpu.num_idle_cycles 4582065338.612248 # Number of idle cycles +system.cpu.num_busy_cycles 649179429.387752 # Number of busy cycles +system.cpu.not_idle_fraction 0.124097 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.875903 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed -system.cpu.icache.replacements 855484 # number of replacements -system.cpu.icache.tagsinuse 510.979435 # Cycle average of tags in use -system.cpu.icache.total_refs 60635401 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 855996 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.836080 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 18713179000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.979435 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.998007 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.998007 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60635401 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60635401 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60635401 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60635401 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60635401 # number of overall hits -system.cpu.icache.overall_hits::total 60635401 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 855996 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 855996 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 855996 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 855996 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 855996 # number of overall misses -system.cpu.icache.overall_misses::total 855996 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11568776000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11568776000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11568776000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11568776000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11568776000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11568776000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61491397 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61491397 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61491397 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61491397 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61491397 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61491397 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013921 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13514.988388 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13514.988388 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13514.988388 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13514.988388 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13514.988388 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13514.988388 # average overall miss latency +system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed +system.cpu.icache.replacements 856250 # number of replacements +system.cpu.icache.tagsinuse 510.885364 # Cycle average of tags in use +system.cpu.icache.total_refs 60635663 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 856762 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 70.773054 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 19768699000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.885364 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.997823 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.997823 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 60635663 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60635663 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60635663 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60635663 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60635663 # number of overall hits +system.cpu.icache.overall_hits::total 60635663 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856762 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856762 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856762 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856762 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856762 # number of overall misses +system.cpu.icache.overall_misses::total 856762 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11759087500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11759087500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11759087500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11759087500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11759087500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11759087500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61492425 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61492425 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61492425 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61492425 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61492425 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61492425 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13725.033907 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13725.033907 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13725.033907 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13725.033907 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13725.033907 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13725.033907 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -329,174 +824,174 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999829 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999829 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13195118 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13195118 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9973036 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9973036 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236277 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236277 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247678 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247678 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23168154 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23168154 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23168154 # 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Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 650249000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.879114 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999764 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999764 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13195840 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13195840 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9972724 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9972724 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236345 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236345 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247797 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247797 # 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miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14601.844185 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14601.844185 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42080.679961 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42080.679961 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13870.601589 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13870.601589 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25719.022479 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25719.022479 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25719.022479 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25719.022479 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -681,54 +1176,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 596040 # number of writebacks -system.cpu.dcache.writebacks::total 596040 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368785 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368785 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250522 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250522 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11402 # 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number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12028168500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12028168500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12028168500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12028168500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182082624500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182082624500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18709226000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18709226000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200791850500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 200791850500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027189 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027189 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024504 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024504 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046035 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046035 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12165.646650 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12165.646650 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30103.785296 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30103.785296 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11656.463778 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11656.463778 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19421.980536 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19421.980536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19421.980536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19421.980536 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 595512 # number of writebacks +system.cpu.dcache.writebacks::total 595512 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368347 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368347 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250279 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250279 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11453 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11453 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 618626 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 618626 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 618626 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 618626 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4641851500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4641851500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10031352500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10031352500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135954000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135954000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14673204000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14673204000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14673204000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14673204000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050723500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050723500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234076500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234076500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284800000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284800000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027156 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027156 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024482 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024482 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046219 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046219 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026007 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026007 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12601.844185 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12601.844185 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40080.679961 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40080.679961 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11870.601589 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11870.601589 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23719.022479 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23719.022479 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23719.022479 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23719.022479 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -736,6 +1231,38 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 53002965 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2454953 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2454953 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 595512 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2911 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2911 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247368 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1725126 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5750616 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 12461 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 27468 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7515671 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54754292 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 83665829 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 14140 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 34916 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 138469177 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 138469177 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 166564 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3009252000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1291764000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2507996500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 18739000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -750,10 +1277,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199377224257 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1199377224257 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199377224257 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1199377224257 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1470128900250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1470128900250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1470128900250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1470128900250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |