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| author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2013-01-07 13:05:52 -0500 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2013-01-07 13:05:52 -0500 |
| commit | 5fb00e1df6b2b7d9db472d0c25765263ed1b839f (patch) | |
| tree | 2f94ca554d9f92d1fe737ed98931856e43b52f6a /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr | |
| parent | e09e9fa279dec86b171b5e3efeb7057fa0d21cc9 (diff) | |
| download | gem5-5fb00e1df6b2b7d9db472d0c25765263ed1b839f.tar.xz | |
tests: Add CPU switching tests
This changeset adds a set of tests that stress the CPU switching
code. It adds the following test configurations:
* tsunami-switcheroo-full -- Alpha system (atomic, timing, O3)
* realview-switcheroo-atomic -- ARM system (atomic<->atomic)
* realview-switcheroo-timing -- ARM system (timing<->timing)
* realview-switcheroo-o3 -- ARM system (O3<->O3)
* realview-switcheroo-full -- ARM system (atomic, timing, O3)
Reference data is provided for the 10.linux-boot test case. All of the
tests trigger a CPU switch once per millisecond during the boot
process.
The in-order CPU model was not included in any of the tests as it does
not support CPU handover.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr')
| -rwxr-xr-x | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr new file mode 100755 index 000000000..083c63715 --- /dev/null +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr @@ -0,0 +1,22 @@ +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: The clidr register always reports 0 caches. +warn: clidr LoUIS field of 0b001 to match current ARM implementations. +warn: The csselr register isn't implemented. +warn: The ccsidr register isn't implemented and always reads as 0. +warn: instruction 'mcr bpiallis' unimplemented +warn: instruction 'mcr icialluis' unimplemented +warn: instruction 'mcr dccimvac' unimplemented +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented +hack: be nice to actually delete the event here +warn: LCD dual screen mode not supported +warn: instruction 'mcr icialluis' unimplemented +warn: instruction 'mcr bpiallis' unimplemented +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR |