diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-11-03 10:14:42 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-11-03 10:14:42 -0600 |
| commit | ae82551496155588786751a3a92191069488d7f3 (patch) | |
| tree | e4521fdada5b41c67f3ba02e5ea058350364c33d /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt | |
| parent | 2c2c3a4ce98480a4b14a72ceb6e43e268e7a1aee (diff) | |
| download | gem5-ae82551496155588786751a3a92191069488d7f3.tar.xz | |
tests: Update stats no match.
Bootloader I had on my sytem was an older version with a couple of
instruction differences.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt | 820 |
1 files changed, 410 insertions, 410 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 863689702..b1c7d16c5 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -1,93 +1,93 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.783853 # Number of seconds simulated -sim_ticks 2783853461500 # Number of ticks simulated -final_tick 2783853461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.783854 # Number of seconds simulated +sim_ticks 2783854177000 # Number of ticks simulated +final_tick 2783854177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1402368 # Simulator instruction rate (inst/s) -host_op_rate 1707157 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27344724772 # Simulator tick rate (ticks/s) -host_mem_usage 555568 # Number of bytes of host memory used -host_seconds 101.81 # Real time elapsed on the host -sim_insts 142769281 # Number of instructions simulated -sim_ops 173798567 # Number of ops (including micro ops) simulated +host_inst_rate 1241693 # Simulator instruction rate (inst/s) +host_op_rate 1511561 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24211403286 # Simulator tick rate (ticks/s) +host_mem_usage 555676 # Number of bytes of host memory used +host_seconds 114.98 # Real time elapsed on the host +sim_insts 142771179 # Number of instructions simulated +sim_ops 173800939 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 727076 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4668128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 726948 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4668448 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 483904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5677444 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 484032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5677124 # Number of bytes read from this memory system.physmem.bytes_read::total 11558024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 727076 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 483904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 726948 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 484032 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6521088 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6521152 # Number of bytes written to this memory system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8856948 # Number of bytes written to this memory +system.physmem.bytes_written::total 8857012 # Number of bytes written to this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 19814 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73458 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 19812 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73463 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7561 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 88711 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7563 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 88706 # Number of read requests responded to by this memory system.physmem.num_reads::total 189567 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 101892 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 101893 # Number of write requests responded to by this memory system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142497 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142498 # Number of write requests responded to by this memory system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 115 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 261176 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1676858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 261130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1676973 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 173825 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2039419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4151808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 261176 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 173825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 173871 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2039304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4151807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 261130 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 173871 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2342468 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2342491 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6292 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3181542 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2342468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3181565 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2342491 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 115 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 261176 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1683150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 261130 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1683265 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 173825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2039422 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7333350 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 74230 # Transaction distribution -system.membus.trans_dist::ReadResp 74230 # Transaction distribution +system.physmem.bw_total::cpu1.inst 173871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2039307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7333371 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 74229 # Transaction distribution +system.membus.trans_dist::ReadResp 74229 # Transaction distribution system.membus.trans_dist::WriteReq 27560 # Transaction distribution system.membus.trans_dist::WriteResp 27560 # Transaction distribution -system.membus.trans_dist::Writeback 101892 # Transaction distribution +system.membus.trans_dist::Writeback 101893 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution @@ -96,48 +96,48 @@ system.membus.trans_dist::UpgradeResp 4509 # Tr system.membus.trans_dist::ReadExReq 146085 # Transaction distribution system.membus.trans_dist::ReadExResp 146085 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 498776 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 606180 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 498777 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 606179 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 679108 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 679107 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18095676 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18258695 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18095740 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18258755 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20592391 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20592451 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 322845 # Request fanout histogram +system.membus.snoop_fanout::samples 322846 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 322845 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 322846 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 322845 # Request fanout histogram +system.membus.snoop_fanout::total 322846 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 110021 # number of replacements -system.l2c.tags.tagsinuse 65155.315266 # Cycle average of tags in use -system.l2c.tags.total_refs 2731077 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 65155.315046 # Cycle average of tags in use +system.l2c.tags.total_refs 2731069 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 175302 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 15.579269 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 15.579223 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48893.451407 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48893.450806 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924325 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000096 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5044.249806 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4729.238472 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5044.246169 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4729.238625 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.978702 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4020.297746 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2464.174711 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4020.301933 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2464.174390 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.746055 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy @@ -157,143 +157,143 @@ system.l2c.tags.age_task_id_blocks_1024::3 10700 # system.l2c.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26229754 # Number of tag accesses -system.l2c.tags.data_accesses 26229754 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4715 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2286 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 833389 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 246771 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4988 # number of ReadReq hits +system.l2c.tags.tag_accesses 26229699 # Number of tag accesses +system.l2c.tags.data_accesses 26229699 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4718 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2285 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 833258 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 246713 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 4981 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 2429 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 847748 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 258725 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2201051 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 682262 # number of Writeback hits -system.l2c.Writeback_hits::total 682262 # number of Writeback hits +system.l2c.ReadReq_hits::cpu1.inst 847891 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 258771 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2201046 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 682259 # number of Writeback hits +system.l2c.Writeback_hits::total 682259 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 72309 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 78732 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 151041 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4715 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2286 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 833389 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 319080 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4988 # number of demand (read+write) hits +system.l2c.ReadExReq_hits::cpu0.data 72299 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 78743 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 151042 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4718 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 2285 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 833258 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 319012 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 4981 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 2429 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 847748 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 337457 # number of demand (read+write) hits -system.l2c.demand_hits::total 2352092 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4715 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2286 # number of overall hits -system.l2c.overall_hits::cpu0.inst 833389 # number of overall hits -system.l2c.overall_hits::cpu0.data 319080 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4988 # number of overall hits +system.l2c.demand_hits::cpu1.inst 847891 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 337514 # number of demand (read+write) hits +system.l2c.demand_hits::total 2352088 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4718 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 2285 # number of overall hits +system.l2c.overall_hits::cpu0.inst 833258 # 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number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 7563 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 89670 # number of demand (read+write) misses system.l2c.demand_misses::total 181759 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 10797 # number of overall misses -system.l2c.overall_misses::cpu0.data 73717 # number of overall misses +system.l2c.overall_misses::cpu0.inst 10795 # number of overall misses +system.l2c.overall_misses::cpu0.data 73723 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu1.inst 7561 # number of overall misses -system.l2c.overall_misses::cpu1.data 89676 # number of overall misses +system.l2c.overall_misses::cpu1.inst 7563 # number of overall misses +system.l2c.overall_misses::cpu1.data 89670 # number of overall misses system.l2c.overall_misses::total 181759 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4720 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 2287 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 844186 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 256522 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 4990 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4723 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 2286 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 844053 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 256463 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 4983 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 2429 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 855309 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 264503 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2234946 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 682262 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 682262 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1260 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1496 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 855454 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 264550 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2234941 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 682259 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 682259 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1261 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1495 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 136275 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 162630 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 298905 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4720 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 2287 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 844186 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 392797 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 4990 # number of demand (read+write) accesses +system.l2c.ReadExReq_accesses::cpu0.data 136272 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 162634 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 298906 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4723 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 2286 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 844053 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 392735 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 4983 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 2429 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 855309 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 427133 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2533851 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4720 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 2287 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 844186 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 392797 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 4990 # number of overall (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 855454 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 427184 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2533847 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4723 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 2286 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 844053 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 392735 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 4983 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 2429 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 855309 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 427133 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2533851 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 855454 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 427184 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2533847 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000437 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.012790 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.038012 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.012789 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.038017 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.008840 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.008841 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.021845 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.015166 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990476 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989305 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990484 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989298 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.469389 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.515883 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.494686 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.469451 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.515827 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.494684 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000437 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.012790 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.187672 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.012789 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.187717 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.008840 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.209949 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.008841 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.209910 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.071732 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000437 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.012790 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.187672 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.012789 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.187717 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.008840 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.209949 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.008841 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.209910 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.071732 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -303,8 +303,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 101892 # number of writebacks -system.l2c.writebacks::total 101892 # number of writebacks +system.l2c.writebacks::writebacks 101893 # number of writebacks +system.l2c.writebacks::total 101893 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -343,28 +343,28 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 2291806 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2291806 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2291797 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2291797 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 682262 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 682259 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298905 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298905 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3417070 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2444902 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20772 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41576 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5924320 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108804860 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96323083 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41544 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83152 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205252639 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadExReq 298906 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 298906 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3417092 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2444877 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20768 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41564 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5924301 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96322187 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83128 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205252475 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 36632 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3272100 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 3272090 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 5.011144 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0.104975 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -373,12 +373,12 @@ system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3235636 98.89% 98.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3235626 98.89% 98.89% # Request fanout histogram system.toL2Bus.snoop_fanout::6 36464 1.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3272100 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3272090 # Request fanout histogram system.iobus.trans_dist::ReadReq 30171 # Transaction distribution system.iobus.trans_dist::ReadResp 30171 # Transaction distribution system.iobus.trans_dist::WriteReq 59016 # Transaction distribution @@ -457,25 +457,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 15997245 # DTB read hits -system.cpu0.dtb.read_misses 4798 # DTB read misses -system.cpu0.dtb.write_hits 11281299 # DTB write hits -system.cpu0.dtb.write_misses 897 # DTB write misses -system.cpu0.dtb.flush_tlb 2812 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 15997157 # DTB read hits +system.cpu0.dtb.read_misses 4809 # DTB read misses +system.cpu0.dtb.write_hits 11281332 # DTB write hits +system.cpu0.dtb.write_misses 894 # DTB write misses +system.cpu0.dtb.flush_tlb 2813 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3224 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3232 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 779 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 770 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 202 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 16002043 # DTB read accesses -system.cpu0.dtb.write_accesses 11282196 # DTB write accesses +system.cpu0.dtb.read_accesses 16001966 # DTB read accesses +system.cpu0.dtb.write_accesses 11282226 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 27278544 # DTB hits -system.cpu0.dtb.misses 5695 # DTB misses -system.cpu0.dtb.accesses 27284239 # DTB accesses +system.cpu0.dtb.hits 27278489 # DTB hits +system.cpu0.dtb.misses 5703 # DTB misses +system.cpu0.dtb.accesses 27284192 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -497,55 +497,55 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 74797989 # ITB inst hits +system.cpu0.itb.inst_hits 74798311 # ITB inst hits system.cpu0.itb.inst_misses 2590 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2812 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 2813 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1905 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1907 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 74800579 # ITB inst accesses -system.cpu0.itb.hits 74797989 # DTB hits +system.cpu0.itb.inst_accesses 74800901 # ITB inst accesses +system.cpu0.itb.hits 74798311 # DTB hits system.cpu0.itb.misses 2590 # DTB misses -system.cpu0.itb.accesses 74800579 # DTB accesses -system.cpu0.numCycles 5536445370 # number of cpu cycles simulated +system.cpu0.itb.accesses 74800901 # DTB accesses +system.cpu0.numCycles 5536444793 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72639024 # Number of instructions committed -system.cpu0.committedOps 87981151 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 77491342 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5273 # Number of float alu accesses -system.cpu0.num_func_calls 8694279 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 9459647 # number of instructions that are conditional controls -system.cpu0.num_int_insts 77491342 # number of integer instructions -system.cpu0.num_fp_insts 5273 # number of float instructions -system.cpu0.num_int_register_reads 144069707 # number of times the integer registers were read -system.cpu0.num_int_register_writes 54447285 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4051 # number of times the floating registers were read +system.cpu0.committedInsts 72639683 # Number of instructions committed +system.cpu0.committedOps 87981695 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 77491900 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5289 # Number of float alu accesses +system.cpu0.num_func_calls 8694354 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 9459791 # number of instructions that are conditional controls +system.cpu0.num_int_insts 77491900 # number of integer instructions +system.cpu0.num_fp_insts 5289 # number of float instructions +system.cpu0.num_int_register_reads 144070444 # number of times the integer registers were read +system.cpu0.num_int_register_writes 54447556 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4067 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1224 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 268877072 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 31833969 # number of times the CC registers were written -system.cpu0.num_mem_refs 27909499 # number of memory refs -system.cpu0.num_load_insts 16164843 # Number of load instructions -system.cpu0.num_store_insts 11744656 # Number of store instructions -system.cpu0.num_idle_cycles 5353619097.982533 # Number of idle cycles -system.cpu0.num_busy_cycles 182826272.017466 # Number of busy cycles -system.cpu0.not_idle_fraction 0.033022 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.966978 # Percentage of idle cycles -system.cpu0.Branches 18600717 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2187 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 61776214 68.83% 68.83% # Class of executed instruction -system.cpu0.op_class::IntMult 59687 0.07% 68.90% # Class of executed instruction +system.cpu0.num_cc_register_reads 268879109 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 31834194 # number of times the CC registers were written +system.cpu0.num_mem_refs 27909453 # number of memory refs +system.cpu0.num_load_insts 16164742 # Number of load instructions +system.cpu0.num_store_insts 11744711 # Number of store instructions +system.cpu0.num_idle_cycles 5353616970.490369 # Number of idle cycles +system.cpu0.num_busy_cycles 182827822.509631 # Number of busy cycles +system.cpu0.not_idle_fraction 0.033023 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.966977 # Percentage of idle cycles +system.cpu0.Branches 18600859 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2188 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 61776837 68.83% 68.83% # Class of executed instruction +system.cpu0.op_class::IntMult 59680 0.07% 68.90% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction @@ -569,27 +569,27 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.90% # Cl system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4413 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4414 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::MemRead 16164843 18.01% 86.91% # Class of executed instruction -system.cpu0.op_class::MemWrite 11744656 13.09% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 16164742 18.01% 86.91% # Class of executed instruction +system.cpu0.op_class::MemWrite 11744711 13.09% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 89752000 # Class of executed instruction +system.cpu0.op_class::total 89752572 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3080 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 1698994 # number of replacements +system.cpu0.icache.tags.replacements 1699006 # number of replacements system.cpu0.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 145339246 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1699506 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 85.518525 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7831492000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.122338 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.541342 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888911 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110432 # Average percentage of cache occupancy +system.cpu0.icache.tags.total_refs 145341254 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 85.519102 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.121642 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.542037 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888909 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110434 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id @@ -597,43 +597,43 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 77 system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 148738270 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 148738270 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 73955669 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 71383577 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 145339246 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 73955669 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 71383577 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 145339246 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 73955669 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 71383577 # number of overall hits -system.cpu0.icache.overall_hits::total 145339246 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 844195 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 855317 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1699512 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 844195 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 855317 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1699512 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 844195 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 855317 # number of overall misses -system.cpu0.icache.overall_misses::total 1699512 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 74799864 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 72238894 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 147038758 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 74799864 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 72238894 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 147038758 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 74799864 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 72238894 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 147038758 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011286 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011840 # miss rate for ReadReq accesses +system.cpu0.icache.tags.tag_accesses 148740302 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 148740302 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 73956125 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 71385129 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 145341254 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 73956125 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 71385129 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 145341254 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 73956125 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 71385129 # number of overall hits +system.cpu0.icache.overall_hits::total 145341254 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 844062 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 855462 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1699524 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 844062 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 855462 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1699524 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 844062 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 855462 # number of overall misses +system.cpu0.icache.overall_misses::total 1699524 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 74800187 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 72240591 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 147040778 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 74800187 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 72240591 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 147040778 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 74800187 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 72240591 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 147040778 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011284 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011842 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011286 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011840 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011284 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011842 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011286 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011840 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011284 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011842 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -644,105 +644,105 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 819402 # number of replacements +system.cpu0.dcache.tags.replacements 819391 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 53782968 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 65.595865 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 23054000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.832873 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.164301 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929361 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070633 # Average percentage of cache occupancy +system.cpu0.dcache.tags.total_refs 53783615 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 819903 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 65.597534 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.830642 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.166532 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929357 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070638 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 219231522 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 219231522 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15305372 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 14822853 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 30128225 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10894245 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 11445267 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 22339512 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185732 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209303 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 395035 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 234999 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222317 # number of LoadLockedReq hits +system.cpu0.dcache.tags.tag_accesses 219234055 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 219234055 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15305331 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 14823339 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 30128670 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 10894284 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 11445424 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 22339708 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185757 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209284 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 395041 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 234994 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222322 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 457316 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236700 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223422 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236693 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223429 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 26199617 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 26268120 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 52467737 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 26385349 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 26477423 # number of overall hits -system.cpu0.dcache.overall_hits::total 52862772 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 197486 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 198842 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 396328 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 137535 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 164126 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 301661 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54372 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61696 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 116068 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4664 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3965 # number of LoadLockedReq misses +system.cpu0.dcache.demand_hits::cpu0.data 26199615 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 26268763 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 52468378 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 26385372 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 26478047 # number of overall hits +system.cpu0.dcache.overall_hits::total 52863419 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 197455 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 198864 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 396319 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 137533 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 164129 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 301662 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54345 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61720 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 116065 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4663 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3966 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 8629 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 335021 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 362968 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 697989 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 389393 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 424664 # number of overall misses -system.cpu0.dcache.overall_misses::total 814057 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 15502858 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 15021695 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 30524553 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 11031780 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 11609393 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 22641173 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240104 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 270999 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511103 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239663 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226282 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 334988 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 362993 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 697981 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 389333 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 424713 # number of overall misses +system.cpu0.dcache.overall_misses::total 814046 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 15502786 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 15022203 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 30524989 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 11031817 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 11609553 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 22641370 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240102 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 271004 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 511106 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239657 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226288 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236700 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223424 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236693 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223431 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 26534638 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 26631088 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 53165726 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 26774742 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 26902087 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 53676829 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012739 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013237 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.012984 # miss rate for ReadReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 26534603 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 26631756 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 53166359 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 26774705 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 26902760 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 53677465 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012737 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013238 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012467 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014137 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226452 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227661 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227093 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019461 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017522 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226341 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227746 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227086 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019457 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017526 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.018519 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000009 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012626 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013629 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.013129 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014543 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015786 # miss rate for overall accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012625 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013630 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014541 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015787 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -752,8 +752,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 682262 # number of writebacks -system.cpu0.dcache.writebacks::total 682262 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 682259 # number of writebacks +system.cpu0.dcache.writebacks::total 682259 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -778,25 +778,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 15526476 # DTB read hits -system.cpu1.dtb.read_misses 5406 # DTB read misses -system.cpu1.dtb.write_hits 11842298 # DTB write hits -system.cpu1.dtb.write_misses 791 # DTB write misses -system.cpu1.dtb.flush_tlb 2818 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 15527003 # DTB read hits +system.cpu1.dtb.read_misses 5395 # DTB read misses +system.cpu1.dtb.write_hits 11842462 # DTB write hits +system.cpu1.dtb.write_misses 794 # DTB write misses +system.cpu1.dtb.flush_tlb 2817 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3194 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 3188 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 917 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 923 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 243 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 15531882 # DTB read accesses -system.cpu1.dtb.write_accesses 11843089 # DTB write accesses +system.cpu1.dtb.read_accesses 15532398 # DTB read accesses +system.cpu1.dtb.write_accesses 11843256 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 27368774 # DTB hits -system.cpu1.dtb.misses 6197 # DTB misses -system.cpu1.dtb.accesses 27374971 # DTB accesses +system.cpu1.dtb.hits 27369465 # DTB hits +system.cpu1.dtb.misses 6189 # DTB misses +system.cpu1.dtb.accesses 27375654 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -818,55 +818,55 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 72236782 # ITB inst hits -system.cpu1.itb.inst_misses 3052 # ITB inst misses +system.cpu1.itb.inst_hits 72238481 # ITB inst hits +system.cpu1.itb.inst_misses 3051 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2818 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 2817 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2023 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2021 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 72239834 # ITB inst accesses -system.cpu1.itb.hits 72236782 # DTB hits -system.cpu1.itb.misses 3052 # DTB misses -system.cpu1.itb.accesses 72239834 # DTB accesses -system.cpu1.numCycles 88012648 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 72241532 # ITB inst accesses +system.cpu1.itb.hits 72238481 # DTB hits +system.cpu1.itb.misses 3051 # DTB misses +system.cpu1.itb.accesses 72241532 # DTB accesses +system.cpu1.numCycles 88014935 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 70130257 # Number of instructions committed -system.cpu1.committedOps 85817416 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 75667160 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6211 # Number of float alu accesses -system.cpu1.num_func_calls 8179026 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 9270368 # number of instructions that are conditional controls -system.cpu1.num_int_insts 75667160 # number of integer instructions -system.cpu1.num_fp_insts 6211 # number of float instructions -system.cpu1.num_int_register_reads 140982352 # number of times the integer registers were read -system.cpu1.num_int_register_writes 52729123 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4721 # number of times the floating registers were read +system.cpu1.committedInsts 70131496 # Number of instructions committed +system.cpu1.committedOps 85819244 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 75668739 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6195 # Number of float alu accesses +system.cpu1.num_func_calls 8179428 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 9270456 # number of instructions that are conditional controls +system.cpu1.num_int_insts 75668739 # number of integer instructions +system.cpu1.num_fp_insts 6195 # number of float instructions +system.cpu1.num_int_register_reads 140985899 # number of times the integer registers were read +system.cpu1.num_int_register_writes 52730443 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4705 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 261962982 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 30529174 # number of times the CC registers were written -system.cpu1.num_mem_refs 28028313 # number of memory refs -system.cpu1.num_load_insts 15690218 # Number of load instructions -system.cpu1.num_store_insts 12338095 # Number of store instructions -system.cpu1.num_idle_cycles 85358107.940046 # Number of idle cycles -system.cpu1.num_busy_cycles 2654540.059954 # Number of busy cycles +system.cpu1.num_cc_register_reads 261968424 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 30529611 # number of times the CC registers were written +system.cpu1.num_mem_refs 28028993 # number of memory refs +system.cpu1.num_load_insts 15690755 # Number of load instructions +system.cpu1.num_store_insts 12338238 # Number of store instructions +system.cpu1.num_idle_cycles 85360290.427990 # Number of idle cycles +system.cpu1.num_busy_cycles 2654644.572010 # Number of busy cycles system.cpu1.not_idle_fraction 0.030161 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.969839 # Percentage of idle cycles -system.cpu1.Branches 17795350 # Number of branches fetched -system.cpu1.op_class::No_OpClass 150 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 59373450 67.88% 67.88% # Class of executed instruction -system.cpu1.op_class::IntMult 57194 0.07% 67.95% # Class of executed instruction +system.cpu1.Branches 17795920 # Number of branches fetched +system.cpu1.op_class::No_OpClass 149 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 59374689 67.88% 67.88% # Class of executed instruction +system.cpu1.op_class::IntMult 57198 0.07% 67.95% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 67.95% # Class of executed instruction @@ -890,24 +890,24 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.95% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4156 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4155 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::MemRead 15690218 17.94% 85.89% # Class of executed instruction -system.cpu1.op_class::MemWrite 12338095 14.11% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 15690755 17.94% 85.89% # Class of executed instruction +system.cpu1.op_class::MemWrite 12338238 14.11% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 87463263 # Class of executed instruction +system.cpu1.op_class::total 87465184 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909886 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909891 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 227409698009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909886 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.909891 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id |