stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee

1 files changed, 86 insertions, 5 deletions

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
index db738381c..5b86ad370 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  2.783854                       # Nu
 sim_ticks                                2783853866500                       # Number of ticks simulated
 final_tick                               2783853866500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1657563                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2017817                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            32320507686                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 622988                       # Number of bytes of host memory used
-host_seconds                                    86.13                       # Real time elapsed on the host
+host_inst_rate                                1399722                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1703936                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            27292901384                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 623636                       # Number of bytes of host memory used
+host_seconds                                   102.00                       # Real time elapsed on the host
 sim_insts                                   142770436                       # Number of instructions simulated
 sim_ops                                     173800089                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu0.dtb.walker          320                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.inst           724196                       # Number of bytes read from this memory
@@ -68,6 +69,7 @@ system.physmem.bw_total::cpu1.inst             173434                       # To
 system.physmem.bw_total::cpu1.data            2034732                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             345                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total                7324797                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
@@ -80,6 +82,9 @@ system.realview.nvmem.bw_inst_read::cpu0.inst            7
 system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               7                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
@@ -87,6 +92,7 @@ system.cf0.dma_write_full_pages                   540                       # Nu
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -116,6 +122,7 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.cpu0.dtb.walker.walks                     5701                       # Table walker walks requested
 system.cpu0.dtb.walker.walksShort                5701                       # Table walker walks initiated with short descriptors
 system.cpu0.dtb.walker.walkWaitTime::samples         5701                       # Table walker wait (enqueue to first request) latency
@@ -155,6 +162,7 @@ system.cpu0.dtb.inst_accesses                       0                       # IT
 system.cpu0.dtb.hits                         27278258                       # DTB hits
 system.cpu0.dtb.misses                           5701                       # DTB misses
 system.cpu0.dtb.accesses                     27283959                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -184,6 +192,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.cpu0.itb.walker.walks                     2590                       # Table walker walks requested
 system.cpu0.itb.walker.walksShort                2590                       # Table walker walks initiated with short descriptors
 system.cpu0.itb.walker.walkWaitTime::samples         2590                       # Table walker wait (enqueue to first request) latency
@@ -223,6 +232,21 @@ system.cpu0.itb.inst_accesses                74801066                       # IT
 system.cpu0.itb.hits                         74798476                       # DTB hits
 system.cpu0.itb.misses                           2590                       # DTB misses
 system.cpu0.itb.accesses                     74801066                       # DTB accesses
+system.cpu0.numPwrStateTransitions               3056                       # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples         1528                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean    1733162653.613220                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev   24573206654.114037                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows         1469     96.14%     96.14% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10           53      3.47%     99.61% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            1      0.07%     99.67% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            1      0.07%     99.74% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11            1      0.07%     99.80% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            3      0.20%    100.00% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::min_value            1                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 499984036900                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total           1528                       # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON   135581331779                       # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 2648272534721                       # Cumulative time (in ticks) in various power states
 system.cpu0.numCycles                      5536444785                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
@@ -285,6 +309,7 @@ system.cpu0.op_class::MemWrite               11744373     13.09%    100.00% # Cl
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::total                  89752341                       # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.cpu0.dcache.tags.replacements           819388                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          511.997174                       # Cycle average of tags in use
 system.cpu0.dcache.tags.total_refs           53783378                       # Total number of references to valid blocks.
@@ -303,6 +328,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2           30
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu0.dcache.tags.tag_accesses        219233092                       # Number of tag accesses
 system.cpu0.dcache.tags.data_accesses       219233092                       # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.cpu0.dcache.ReadReq_hits::cpu0.data     15305418                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::cpu1.data     14823075                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total       30128493                       # number of ReadReq hits
@@ -393,6 +419,7 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.writebacks::writebacks       682241                       # number of writebacks
 system.cpu0.dcache.writebacks::total           682241                       # number of writebacks
+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.cpu0.icache.tags.replacements          1698997                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.663679                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs          145340473                       # Total number of references to valid blocks.
@@ -412,6 +439,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::3            5
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu0.icache.tags.tag_accesses        148739503                       # Number of tag accesses
 system.cpu0.icache.tags.data_accesses       148739503                       # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.cpu0.icache.ReadReq_hits::cpu0.inst     73956240                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::cpu1.inst     71384233                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::total      145340473                       # number of ReadReq hits
@@ -456,6 +484,7 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.writebacks::writebacks      1698997                       # number of writebacks
 system.cpu0.icache.writebacks::total          1698997                       # number of writebacks
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -485,6 +514,7 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.cpu1.dtb.walker.walks                     6190                       # Table walker walks requested
 system.cpu1.dtb.walker.walksShort                6190                       # Table walker walks initiated with short descriptors
 system.cpu1.dtb.walker.walkWaitTime::samples         6190                       # Table walker wait (enqueue to first request) latency
@@ -524,6 +554,7 @@ system.cpu1.dtb.inst_accesses                       0                       # IT
 system.cpu1.dtb.hits                         27369436                       # DTB hits
 system.cpu1.dtb.misses                           6190                       # DTB misses
 system.cpu1.dtb.accesses                     27375626                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -553,6 +584,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.cpu1.itb.walker.walks                     3051                       # Table walker walks requested
 system.cpu1.itb.walker.walksShort                3051                       # Table walker walks initiated with short descriptors
 system.cpu1.itb.walker.walkWaitTime::samples         3051                       # Table walker wait (enqueue to first request) latency
@@ -592,6 +624,20 @@ system.cpu1.itb.inst_accesses                72240577                       # IT
 system.cpu1.itb.hits                         72237526                       # DTB hits
 system.cpu1.itb.misses                           3051                       # DTB misses
 system.cpu1.itb.accesses                     72240577                       # DTB accesses
+system.cpu1.numPwrStateTransitions               3092                       # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples         1546                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean    1765528734.857697                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev   61147535730.449074                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows         1529     98.90%     98.90% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10           14      0.91%     99.81% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            1      0.06%     99.87% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11            1      0.06%     99.94% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::overflows            1      0.06%    100.00% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::min_value            1                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 2395080450001                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total           1546                       # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON    54346442410                       # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 2729507424090                       # Cumulative time (in ticks) in various power states
 system.cpu1.numCycles                        88014282                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
@@ -654,6 +700,7 @@ system.cpu1.op_class::MemWrite               12338512     14.11%    100.00% # Cl
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::total                  87464517                       # Class of executed instruction
+system.iobus.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.iobus.trans_dist::ReadReq                30164                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30164                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59002                       # Transaction distribution
@@ -704,6 +751,7 @@ system.iobus.pkt_size_system.bridge.master::total       159061
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321152                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321152                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480213                       # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.iocache.tags.replacements                36430                       # number of replacements
 system.iocache.tags.tagsinuse                0.909889                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
@@ -718,6 +766,7 @@ system.iocache.tags.age_task_id_blocks_1023::3           16
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
 system.iocache.tags.tag_accesses               328176                       # Number of tag accesses
 system.iocache.tags.data_accesses              328176                       # Number of data accesses
+system.iocache.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.iocache.ReadReq_misses::realview.ide          240                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              240                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
@@ -750,6 +799,7 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.l2c.tags.replacements                   109908                       # number of replacements
 system.l2c.tags.tagsinuse                65155.315514                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    4528029                       # Total number of references to valid blocks.
@@ -785,6 +835,7 @@ system.l2c.tags.occ_task_id_percent::1023     0.000061                       # P
 system.l2c.tags.occ_task_id_percent::1024     0.996048                       # Percentage of cache occupancy per task id
 system.l2c.tags.tag_accesses                 40604397                       # Number of tag accesses
 system.l2c.tags.data_accesses                40604397                       # Number of data accesses
+system.l2c.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.l2c.ReadReq_hits::cpu0.dtb.walker         4717                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.itb.walker         2285                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.dtb.walker         4983                       # number of ReadReq hits
@@ -947,6 +998,7 @@ system.membus.snoop_filter.hit_multi_requests          488
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq               40087                       # Transaction distribution
 system.membus.trans_dist::ReadResp              74196                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27546                       # Transaction distribution
@@ -989,12 +1041,21 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::total              434811                       # Request fanout histogram
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
 system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
 system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
 system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -1026,16 +1087,36 @@ system.realview.ethernet.totalRxOrn                 0                       # to
 system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
 system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.realview.ethernet.droppedPackets             0                       # number of packets dropped
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.toL2Bus.snoop_filter.tot_requests      5060315                       # Total number of requests made to the snoop filter.
 system.toL2Bus.snoop_filter.hit_single_requests      2540903                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_requests        39264                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.snoop_filter.tot_snoops            422                       # Total number of snoops made to the snoop filter.
 system.toL2Bus.snoop_filter.hit_single_snoops          422                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783853866500                       # Cumulative time (in ticks) in various power states
 system.toL2Bus.trans_dist::ReadReq              71253                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadResp           2291775                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27546                       # Transaction distribution