diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-09-16 09:14:31 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-09-16 09:14:31 +0100 |
| commit | ada0e2f02fb3a30d01f62eb124a1d374be0b8ed5 (patch) | |
| tree | 82c5b4db42b6ade0e4eeed758be629c57e2f5f60 /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt | |
| parent | 1ecc3628a8fe24d8ed189ee23ca41f2b385b3d8e (diff) | |
| download | gem5-ada0e2f02fb3a30d01f62eb124a1d374be0b8ed5.tar.xz | |
tests, arm: Make switcheroo and checkpoint tests functional
Switcheroo and checkpoint tests should generally be considered to be
successful if they run to completion. Remove all reference output
files from the switcheroo and checkopint tests to make them purely
functional.
Change-Id: I70b47853bd662b7a33716d9e0d2154b16077f9dc
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt | 1156 |
1 files changed, 0 insertions, 1156 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt deleted file mode 100644 index 5223c911e..000000000 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ /dev/null @@ -1,1156 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 2.783855 # Number of seconds simulated -sim_ticks 2783854715000 # Number of ticks simulated -final_tick 2783854715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 808320 # Simulator instruction rate (inst/s) -host_op_rate 984000 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15761202711 # Simulator tick rate (ticks/s) -host_mem_usage 583272 # Number of bytes of host memory used -host_seconds 176.63 # Real time elapsed on the host -sim_insts 142771202 # Number of instructions simulated -sim_ops 173801044 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 724388 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4660832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 482624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5663620 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11532936 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 724388 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 482624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8840512 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8858036 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 19772 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73344 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7541 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 88495 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189175 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138133 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142514 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 260210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1674237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 173365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2034452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4142794 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 260210 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 173365 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3175637 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6292 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3181932 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3175637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 260210 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1680529 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 173365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2034455 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7324726 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 5701 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 5701 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 5701 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 5701 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 5701 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3071 65.62% 65.62% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1609 34.38% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4680 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5701 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5701 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4680 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4680 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 10381 # Table walker requests started/completed, data/inst -system.cpu0.dtb.inst_hits 0 # ITB inst hits -system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 15995747 # DTB read hits -system.cpu0.dtb.read_misses 4808 # DTB read misses -system.cpu0.dtb.write_hits 11281650 # DTB write hits -system.cpu0.dtb.write_misses 893 # DTB write misses -system.cpu0.dtb.flush_tlb 2813 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3166 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 769 # Number of TLB faults due to prefetch -system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 202 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 16000555 # DTB read accesses -system.cpu0.dtb.write_accesses 11282543 # DTB write accesses -system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 27277397 # DTB hits -system.cpu0.dtb.misses 5701 # DTB misses -system.cpu0.dtb.accesses 27283098 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 2588 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2588 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2588 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2588 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2588 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1363 72.73% 72.73% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 511 27.27% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 1874 # Table walker page sizes translated -system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2588 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2588 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1874 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1874 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4462 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 74790987 # ITB inst hits -system.cpu0.itb.inst_misses 2588 # ITB inst misses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2813 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1841 # Number of entries that have been flushed from TLB -system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 74793575 # ITB inst accesses -system.cpu0.itb.hits 74790987 # DTB hits -system.cpu0.itb.misses 2588 # DTB misses -system.cpu0.itb.accesses 74793575 # DTB accesses -system.cpu0.numPwrStateTransitions 3054 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1527 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1734298234.726916 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 24581216487.655636 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1468 96.14% 96.14% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 53 3.47% 99.61% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.07% 99.67% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.07% 99.74% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.07% 99.80% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 3 0.20% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1527 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 135581310572 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2648273404428 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 5536440740 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3080 # number of quiesce instructions executed -system.cpu0.committedInsts 72632991 # Number of instructions committed -system.cpu0.committedOps 87975246 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 77486299 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5273 # Number of float alu accesses -system.cpu0.num_func_calls 8693335 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 9458955 # number of instructions that are conditional controls -system.cpu0.num_int_insts 77486299 # number of integer instructions -system.cpu0.num_fp_insts 5273 # number of float instructions -system.cpu0.num_int_register_reads 144060688 # number of times the integer registers were read -system.cpu0.num_int_register_writes 54442960 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4051 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1224 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 268859447 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 31831121 # number of times the CC registers were written -system.cpu0.num_mem_refs 27908365 # number of memory refs -system.cpu0.num_load_insts 16163327 # Number of load instructions -system.cpu0.num_store_insts 11745038 # Number of store instructions -system.cpu0.num_idle_cycles 5353619045.925056 # Number of idle cycles -system.cpu0.num_busy_cycles 182821694.074943 # Number of busy cycles -system.cpu0.not_idle_fraction 0.033022 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.966978 # Percentage of idle cycles -system.cpu0.Branches 18598975 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2188 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 61771234 68.83% 68.83% # Class of executed instruction -system.cpu0.op_class::IntMult 59679 0.07% 68.90% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4413 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::MemRead 16163327 18.01% 86.91% # Class of executed instruction -system.cpu0.op_class::MemWrite 11745038 13.09% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 89745879 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 819387 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 53783711 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 819899 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 65.597971 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.709270 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.287904 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929120 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070875 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 219234419 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 219234419 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 15303909 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 14824794 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 30128703 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10894549 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 11445218 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 22339767 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185793 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209252 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 395045 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235001 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222316 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 457317 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236699 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223423 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 26198458 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 26270012 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 52468470 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 26384251 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 26479264 # number of overall hits -system.cpu0.dcache.overall_hits::total 52863515 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 197405 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 198906 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 396311 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 137584 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 164078 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 301662 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54365 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61704 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 116069 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4662 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3966 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8628 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 334989 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 362984 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 697973 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 389354 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 424688 # number of overall misses -system.cpu0.dcache.overall_misses::total 814042 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 15501314 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 15023700 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 30525014 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 11032133 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 11609296 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 22641429 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240158 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 270956 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511114 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239663 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226282 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236699 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223425 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 26533447 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 26632996 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 53166443 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 26773605 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 26903952 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 53677557 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012735 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013239 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012471 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014133 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226372 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227727 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227090 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019452 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017527 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.018517 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000009 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012625 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013629 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014542 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015785 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.015165 # miss rate for overall accesses -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 682362 # number of writebacks -system.cpu0.dcache.writebacks::total 682362 # number of writebacks -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1698988 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 145341295 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1699500 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 85.520032 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7831497000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.113855 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.549824 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888894 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110449 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 148740307 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 148740307 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 73948641 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 71392654 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 145341295 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 73948641 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 71392654 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 145341295 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 73948641 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 71392654 # number of overall hits -system.cpu0.icache.overall_hits::total 145341295 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 844220 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 855286 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1699506 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 844220 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 855286 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1699506 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 844220 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 855286 # number of overall misses -system.cpu0.icache.overall_misses::total 1699506 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 74792861 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 72247940 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 147040801 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 74792861 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 72247940 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 147040801 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 74792861 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 72247940 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 147040801 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011287 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011838 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011287 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011838 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011287 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011838 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1698988 # number of writebacks -system.cpu0.icache.writebacks::total 1698988 # number of writebacks -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 6189 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6189 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 6189 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6189 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6189 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walksPending::samples 1000002000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1000002000 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1000002000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3697 73.27% 73.27% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1349 26.73% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5046 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6189 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6189 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5046 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5046 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 11235 # Table walker requests started/completed, data/inst -system.cpu1.dtb.inst_hits 0 # ITB inst hits -system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 15528433 # DTB read hits -system.cpu1.dtb.read_misses 5402 # DTB read misses -system.cpu1.dtb.write_hits 11842197 # DTB write hits -system.cpu1.dtb.write_misses 787 # DTB write misses -system.cpu1.dtb.flush_tlb 2817 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3134 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 916 # Number of TLB faults due to prefetch -system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 243 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 15533835 # DTB read accesses -system.cpu1.dtb.write_accesses 11842984 # DTB write accesses -system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 27370630 # DTB hits -system.cpu1.dtb.misses 6189 # DTB misses -system.cpu1.dtb.accesses 27376819 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 3051 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3051 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walkWaitTime::samples 3051 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3051 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3051 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1721 81.56% 81.56% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 389 18.44% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2110 # Table walker page sizes translated -system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3051 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3051 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2110 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2110 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 5161 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 72245830 # ITB inst hits -system.cpu1.itb.inst_misses 3051 # ITB inst misses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2817 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1961 # Number of entries that have been flushed from TLB -system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 72248881 # ITB inst accesses -system.cpu1.itb.hits 72245830 # DTB hits -system.cpu1.itb.misses 3051 # DTB misses -system.cpu1.itb.accesses 72248881 # DTB accesses -system.cpu1.numPwrStateTransitions 3094 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 1547 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1764387509.755010 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 61127772689.263474 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1530 98.90% 98.90% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 14 0.90% 99.81% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.06% 99.87% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.06% 99.94% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 1 0.06% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 2395080486501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 1547 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 54347237409 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2729507477591 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 88023752 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 70138211 # Number of instructions committed -system.cpu1.committedOps 85825798 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 75674492 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6211 # Number of float alu accesses -system.cpu1.num_func_calls 8180529 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 9271265 # number of instructions that are conditional controls -system.cpu1.num_int_insts 75674492 # number of integer instructions -system.cpu1.num_fp_insts 6211 # number of float instructions -system.cpu1.num_int_register_reads 140982518 # number of times the integer registers were read -system.cpu1.num_int_register_writes 52735108 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4721 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 261988380 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 30532586 # number of times the CC registers were written -system.cpu1.num_mem_refs 28030145 # number of memory refs -system.cpu1.num_load_insts 15692181 # Number of load instructions -system.cpu1.num_store_insts 12337964 # Number of store instructions -system.cpu1.num_idle_cycles 85368728.542814 # Number of idle cycles -system.cpu1.num_busy_cycles 2655023.457186 # Number of busy cycles -system.cpu1.not_idle_fraction 0.030163 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.969837 # Percentage of idle cycles -system.cpu1.Branches 17797845 # Number of branches fetched -system.cpu1.op_class::No_OpClass 149 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 59380337 67.88% 67.89% # Class of executed instruction -system.cpu1.op_class::IntMult 57194 0.07% 67.95% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4156 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::MemRead 15692181 17.94% 85.89% # Class of executed instruction -system.cpu1.op_class::MemWrite 12337964 14.11% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 87471981 # Class of executed instruction -system.iobus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 30164 # Transaction distribution -system.iobus.trans_dist::ReadResp 30164 # Transaction distribution -system.iobus.trans_dist::WriteReq 59002 # Transaction distribution -system.iobus.trans_dist::WriteResp 59002 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909890 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 227410176509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909890 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328176 # Number of tag accesses -system.iocache.tags.data_accesses 328176 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses -system.iocache.ReadReq_misses::total 240 # number of ReadReq misses -system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36464 # number of demand (read+write) misses -system.iocache.demand_misses::total 36464 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36464 # number of overall misses -system.iocache.overall_misses::total 36464 # number of overall misses -system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36464 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36464 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36464 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36464 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 109906 # number of replacements -system.l2c.tags.tagsinuse 65246.862245 # Cycle average of tags in use -system.l2c.tags.total_refs 4830712 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 175332 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 27.551799 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 71491095000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.924122 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999998 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5146.889475 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 28219.641429 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.978701 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4023.136773 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 27850.291746 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000075 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.078535 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.430598 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.061388 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.424962 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995588 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65419 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9745 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55478 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.998215 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 40281361 # Number of tag accesses -system.l2c.tags.data_accesses 40281361 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 3721 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1793 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 3957 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1933 # number of ReadReq hits -system.l2c.ReadReq_hits::total 11404 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 682362 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 682362 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1666989 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1666989 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 1257 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1489 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2746 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 73078 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 79712 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 152790 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 833454 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 847737 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1681191 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 246679 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 258766 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 505445 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 3721 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1793 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 833454 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 319757 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 3957 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1933 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 847737 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 338478 # number of demand (read+write) hits -system.l2c.demand_hits::total 2350830 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 3721 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1793 # number of overall hits -system.l2c.overall_hits::cpu0.inst 833454 # number of overall hits -system.l2c.overall_hits::cpu0.data 319757 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 3957 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1933 # number of overall hits -system.l2c.overall_hits::cpu1.inst 847737 # number of overall hits -system.l2c.overall_hits::cpu1.data 338478 # number of overall hits -system.l2c.overall_hits::total 2350830 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::total 8 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 9 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63244 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 82873 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 146117 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 10757 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 7541 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 9753 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 5810 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 15563 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 10757 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 72997 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 7541 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 88683 # number of demand (read+write) misses -system.l2c.demand_misses::total 179986 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 10757 # number of overall misses -system.l2c.overall_misses::cpu0.data 72997 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu1.inst 7541 # number of overall misses -system.l2c.overall_misses::cpu1.data 88683 # number of overall misses -system.l2c.overall_misses::total 179986 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 3726 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 1794 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 3959 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1933 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 11412 # number of ReadReq accesses(hits+misses) -system.l2c.WritebackDirty_accesses::writebacks 682362 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 682362 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 1666989 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 1666989 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1262 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1493 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2755 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 136322 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 162585 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 844211 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 855278 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1699489 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 256432 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 264576 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 3726 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 1794 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 844211 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 392754 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 3959 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1933 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 855278 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 427161 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2530816 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 3726 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 1794 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 844211 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 392754 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 3959 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1933 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 855278 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 427161 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2530816 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001342 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000557 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000505 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.000701 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.003962 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.002679 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.003267 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.463931 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.509721 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.488838 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.012742 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.008817 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.038033 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021960 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.029871 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001342 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000557 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.012742 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.185859 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000505 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.008817 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.207610 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.071118 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001342 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000557 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.012742 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.185859 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000505 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.008817 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.207610 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.071118 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 101943 # number of writebacks -system.l2c.writebacks::total 101943 # number of writebacks -system.membus.snoop_filter.tot_requests 362797 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 151017 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 488 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 40087 # Transaction distribution -system.membus.trans_dist::ReadResp 74196 # Transaction distribution -system.membus.trans_dist::WriteReq 27546 # Transaction distribution -system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::WritebackDirty 138133 # Transaction distribution -system.membus.trans_dist::CleanEvict 8203 # Transaction distribution -system.membus.trans_dist::UpgradeReq 130 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 145996 # Transaction distribution -system.membus.trans_dist::ReadExResp 145996 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34109 # Transaction distribution -system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 497806 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 605166 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 714524 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18091580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18254553 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20586073 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 430430 # Request fanout histogram -system.membus.snoop_fanout::mean 0.012836 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.112567 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 424905 98.72% 98.72% # Request fanout histogram -system.membus.snoop_fanout::1 5525 1.28% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 430430 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks -system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks -system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks -system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks -system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks -system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks -system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks -system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5060294 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2540892 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 71240 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2291754 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 682362 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1698988 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 137025 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2757 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1699506 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5116044 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581953 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20756 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41550 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7760303 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 217539704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96328481 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41512 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83100 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 313992797 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 115320 # Total snoops (count) -system.toL2Bus.snoopTraffic 6540928 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 5254491 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.018785 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.135764 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5155787 98.12% 98.12% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 98704 1.88% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5254491 # Request fanout histogram - ----------- End Simulation Statistics ---------- |