diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
| commit | 84f138ba96201431513eb2ae5f847389ac731aa2 (patch) | |
| tree | 3aee721699295c85e4e0c2d3d4a6bb27595bfabd /tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic | |
| parent | a288c94387b110112461ff5686fa727a43ddbe9c (diff) | |
| download | gem5-84f138ba96201431513eb2ae5f847389ac731aa2.tar.xz | |
stats: update references
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic')
4 files changed, 815 insertions, 540 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini index 146e24737..b01510cd2 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini @@ -12,11 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/dist/m5/system/binaries/boot_emm.arm +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -29,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -41,10 +42,14 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= thermal_components= @@ -61,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -89,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/m5/system/disks/linux-aarch32-ael.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -107,6 +117,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -125,6 +136,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -146,12 +161,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -170,8 +190,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -194,9 +219,14 @@ walker=system.cpu0.dstage2_mmu.stage2_tlb.walker [system.cpu0.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.dtb] @@ -210,9 +240,14 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.toL2Bus.slave[3] @@ -223,12 +258,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -247,8 +287,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -306,9 +351,14 @@ walker=system.cpu0.istage2_mmu.stage2_tlb.walker [system.cpu0.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.itb] @@ -322,9 +372,14 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.toL2Bus.slave[2] @@ -339,6 +394,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -357,6 +413,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -388,9 +448,14 @@ walker=system.cpu1.dstage2_mmu.stage2_tlb.walker [system.cpu1.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.dtb] @@ -404,9 +469,14 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.isa] @@ -459,9 +529,14 @@ walker=system.cpu1.istage2_mmu.stage2_tlb.walker [system.cpu1.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.itb] @@ -475,9 +550,14 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.tracer] @@ -508,9 +588,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -524,12 +609,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -548,8 +638,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -560,12 +655,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -584,8 +684,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 @@ -593,10 +698,15 @@ size=4194304 type=CoherentXBar children=badaddr_responder snoop_filter clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=system.membus.snoop_filter snoop_response_latency=4 @@ -610,11 +720,16 @@ slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.io [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -637,11 +752,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=2147483648:2415919103 port=system.membus.master[5] @@ -656,10 +776,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -740,14 +865,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -756,13 +886,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -843,10 +978,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -926,17 +1066,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -962,13 +1107,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -976,14 +1126,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -1069,14 +1224,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1085,13 +1245,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -1100,13 +1265,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -1114,11 +1284,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1132,11 +1307,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1150,12 +1330,17 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] @@ -1223,10 +1408,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -1235,11 +1425,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -1249,21 +1444,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=16 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=0 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -1273,12 +1478,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -1287,10 +1497,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -1300,12 +1515,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -1315,26 +1535,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -1343,10 +1573,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -1354,10 +1589,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -1365,21 +1605,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1393,11 +1643,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -1408,11 +1663,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -1420,10 +1680,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] @@ -1439,10 +1704,15 @@ port=3456 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr index cf30e237d..2db4f78f6 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr @@ -1,6 +1,8 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: Not doing anything for miscreg ACTLR warn: Not doing anything for write of miscreg ACTLR @@ -22,6 +24,7 @@ warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: ClockedObject: Already in the requested power state, request ignored warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout index 9158d2404..38ea1453e 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:45:42 -gem5 started Jan 21 2016 14:46:19 -gem5 executing on zizzer, pid 20712 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:38:22 +gem5 executing on e108600-lin, pid 23073 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index cb49bb6de..a93197b72 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -1,75 +1,75 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.783854 # Number of seconds simulated -sim_ticks 2783853866500 # Number of ticks simulated -final_tick 2783853866500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.783855 # Number of seconds simulated +sim_ticks 2783854715000 # Number of ticks simulated +final_tick 2783854715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 812896 # Simulator instruction rate (inst/s) -host_op_rate 989570 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15850505887 # Simulator tick rate (ticks/s) -host_mem_usage 582360 # Number of bytes of host memory used -host_seconds 175.63 # Real time elapsed on the host -sim_insts 142770436 # Number of instructions simulated -sim_ops 173800089 # Number of ops (including micro ops) simulated +host_inst_rate 659084 # Simulator instruction rate (inst/s) +host_op_rate 802329 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12851282769 # Simulator tick rate (ticks/s) +host_mem_usage 578036 # Number of bytes of host memory used +host_seconds 216.62 # Real time elapsed on the host +sim_insts 142771202 # Number of instructions simulated +sim_ops 173801044 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 724196 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4660192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 724388 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4660832 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 482816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5664388 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 482624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5663620 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11533064 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 724196 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 482816 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 11532936 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 724388 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 482624 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8840576 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 8840512 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8858100 # Number of bytes written to this memory +system.physmem.bytes_written::total 8858036 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 19769 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73334 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 19772 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73344 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7544 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 88507 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7541 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 88495 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189177 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138134 # Number of write requests responded to by this memory +system.physmem.num_reads::total 189175 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138133 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142515 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142514 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 115 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 260142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1674007 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 260210 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1674237 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 173434 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2034729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 173365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2034452 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4142841 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 260142 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 173434 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4142794 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 260210 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 173365 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3175661 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3175637 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6292 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3181956 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3175661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3181932 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3175637 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 115 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 260142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1680299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 260210 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1680529 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 173434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2034732 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 173365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2034455 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7324797 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states +system.physmem.bw_total::total 7324726 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -82,9 +82,9 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 7 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -92,7 +92,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -122,7 +122,7 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cpu0.dtb.walker.walks 5701 # Table walker walks requested system.cpu0.dtb.walker.walksShort 5701 # Table walker walks initiated with short descriptors system.cpu0.dtb.walker.walkWaitTime::samples 5701 # Table walker wait (enqueue to first request) latency @@ -131,8 +131,8 @@ system.cpu0.dtb.walker.walkWaitTime::total 5701 # system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3076 65.73% 65.73% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1604 34.27% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::4K 3071 65.62% 65.62% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1609 34.38% 100.00% # Table walker page sizes translated system.cpu0.dtb.walker.walkPageSizes::total 4680 # Table walker page sizes translated system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5701 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -143,26 +143,26 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4680 system.cpu0.dtb.walker.walkRequestOrigin::total 10381 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 15997246 # DTB read hits -system.cpu0.dtb.read_misses 4805 # DTB read misses -system.cpu0.dtb.write_hits 11281012 # DTB write hits -system.cpu0.dtb.write_misses 896 # DTB write misses +system.cpu0.dtb.read_hits 15995747 # DTB read hits +system.cpu0.dtb.read_misses 4808 # DTB read misses +system.cpu0.dtb.write_hits 11281650 # DTB write hits +system.cpu0.dtb.write_misses 893 # DTB write misses system.cpu0.dtb.flush_tlb 2813 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3167 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3166 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 769 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 202 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 16002051 # DTB read accesses -system.cpu0.dtb.write_accesses 11281908 # DTB write accesses +system.cpu0.dtb.read_accesses 16000555 # DTB read accesses +system.cpu0.dtb.write_accesses 11282543 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 27278258 # DTB hits +system.cpu0.dtb.hits 27277397 # DTB hits system.cpu0.dtb.misses 5701 # DTB misses -system.cpu0.dtb.accesses 27283959 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.accesses 27283098 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -192,27 +192,27 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 2590 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2590 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2590 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2590 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2590 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 2588 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2588 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2588 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2588 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2588 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1367 72.87% 72.87% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 509 27.13% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 1876 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 1363 72.73% 72.73% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 511 27.27% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1874 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2590 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2590 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2588 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2588 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1876 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1876 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4466 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 74798476 # ITB inst hits -system.cpu0.itb.inst_misses 2590 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1874 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1874 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4462 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 74790987 # ITB inst hits +system.cpu0.itb.inst_misses 2588 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -221,62 +221,62 @@ system.cpu0.itb.flush_tlb 2813 # Nu system.cpu0.itb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1843 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1841 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 74801066 # ITB inst accesses -system.cpu0.itb.hits 74798476 # DTB hits -system.cpu0.itb.misses 2590 # DTB misses -system.cpu0.itb.accesses 74801066 # DTB accesses -system.cpu0.numPwrStateTransitions 3056 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1528 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1733162653.613220 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 24573206654.114037 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1469 96.14% 96.14% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 74793575 # ITB inst accesses +system.cpu0.itb.hits 74790987 # DTB hits +system.cpu0.itb.misses 2588 # DTB misses +system.cpu0.itb.accesses 74793575 # DTB accesses +system.cpu0.numPwrStateTransitions 3054 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1527 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1734298234.726916 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 24581216487.655636 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1468 96.14% 96.14% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1000-5e+10 53 3.47% 99.61% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.07% 99.67% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.07% 99.74% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.07% 99.80% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 3 0.20% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1528 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 135581331779 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2648272534721 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 5536444785 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::total 1527 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 135581310572 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2648273404428 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 5536440740 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3080 # number of quiesce instructions executed -system.cpu0.committedInsts 72639773 # Number of instructions committed -system.cpu0.committedOps 87981470 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 77491639 # Number of integer alu accesses +system.cpu0.committedInsts 72632991 # Number of instructions committed +system.cpu0.committedOps 87975246 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 77486299 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5273 # Number of float alu accesses -system.cpu0.num_func_calls 8694385 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 9459738 # number of instructions that are conditional controls -system.cpu0.num_int_insts 77491639 # number of integer instructions +system.cpu0.num_func_calls 8693335 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 9458955 # number of instructions that are conditional controls +system.cpu0.num_int_insts 77486299 # number of integer instructions system.cpu0.num_fp_insts 5273 # number of float instructions -system.cpu0.num_int_register_reads 144056693 # number of times the integer registers were read -system.cpu0.num_int_register_writes 54447639 # number of times the integer registers were written +system.cpu0.num_int_register_reads 144047578 # number of times the integer registers were read +system.cpu0.num_int_register_writes 54442960 # number of times the integer registers were written system.cpu0.num_fp_register_reads 4051 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1224 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 268878195 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 31834253 # number of times the CC registers were written -system.cpu0.num_mem_refs 27909194 # number of memory refs -system.cpu0.num_load_insts 16164821 # Number of load instructions -system.cpu0.num_store_insts 11744373 # Number of store instructions -system.cpu0.num_idle_cycles 5353617701.078379 # Number of idle cycles -system.cpu0.num_busy_cycles 182827083.921621 # Number of busy cycles +system.cpu0.num_cc_register_reads 268859447 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 31831121 # number of times the CC registers were written +system.cpu0.num_mem_refs 27908365 # number of memory refs +system.cpu0.num_load_insts 16163327 # Number of load instructions +system.cpu0.num_store_insts 11745038 # Number of store instructions +system.cpu0.num_idle_cycles 5353619045.925056 # Number of idle cycles +system.cpu0.num_busy_cycles 182821694.074943 # Number of busy cycles system.cpu0.not_idle_fraction 0.033022 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.966978 # Percentage of idle cycles -system.cpu0.Branches 18600825 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2187 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 61776865 68.83% 68.83% # Class of executed instruction -system.cpu0.op_class::IntMult 59682 0.07% 68.90% # Class of executed instruction +system.cpu0.Branches 18598975 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2188 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 61771234 68.83% 68.83% # Class of executed instruction +system.cpu0.op_class::IntMult 59679 0.07% 68.90% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction @@ -304,113 +304,113 @@ system.cpu0.op_class::SimdFloatMisc 4413 0.00% 68.90% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::MemRead 16164821 18.01% 86.91% # Class of executed instruction -system.cpu0.op_class::MemWrite 11744373 13.09% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 16163327 18.01% 86.91% # Class of executed instruction +system.cpu0.op_class::MemWrite 11745038 13.09% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 89752341 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 819388 # number of replacements +system.cpu0.op_class::total 89745879 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 819387 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 53783378 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 819900 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 65.597485 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 53783711 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 819899 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 65.597971 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.830508 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.166666 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929356 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070638 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.709270 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.287904 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929120 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070875 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 219233092 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 219233092 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 15305418 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 14823075 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 30128493 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10893995 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 11445651 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 22339646 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185752 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209291 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 395043 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 234995 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222321 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 457316 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236694 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223428 # number of StoreCondReq hits +system.cpu0.dcache.tags.tag_accesses 219234419 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 219234419 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 15303909 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 14824794 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 30128703 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 10894549 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 11445217 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 22339766 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185793 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209252 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 395045 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235001 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222316 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 457317 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236699 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223423 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 26199413 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 26268726 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 52468139 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 26385165 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 26478017 # number of overall hits -system.cpu0.dcache.overall_hits::total 52863182 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 197452 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 198861 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 396313 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 137507 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 164158 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 301665 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54352 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61713 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 116065 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4663 # number of LoadLockedReq misses +system.cpu0.dcache.demand_hits::cpu0.data 26198458 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 26270011 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 52468469 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 26384251 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 26479263 # number of overall hits +system.cpu0.dcache.overall_hits::total 52863514 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 197405 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 198906 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 396311 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 137584 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 164079 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 301663 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54365 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61704 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 116069 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4662 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3966 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8629 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8628 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 334959 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 363019 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 697978 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 389311 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 424732 # number of overall misses +system.cpu0.dcache.demand_misses::cpu0.data 334989 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 362985 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 697974 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 389354 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 424689 # number of overall misses system.cpu0.dcache.overall_misses::total 814043 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 15502870 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 15021936 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 30524806 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 11031502 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 11609809 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 22641311 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240104 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 271004 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511108 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239658 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226287 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu0.data 15501314 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 15023700 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 30525014 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 11032133 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 11609296 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 22641429 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240158 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 270956 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 511114 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239663 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226282 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236694 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223430 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236699 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223425 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 26534372 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 26631745 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 53166117 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 26774476 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 26902749 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 53677225 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012736 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013238 # miss rate for ReadReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 26533447 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 26632996 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 53166443 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 26773605 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 26903952 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 53677557 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012735 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013239 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012465 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014140 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226369 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227720 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227085 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019457 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017526 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.018519 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012471 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014133 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226372 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227727 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227090 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019452 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017527 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.018517 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000009 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012624 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013631 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012625 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013629 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014540 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015788 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014542 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015785 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.015165 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,17 +419,17 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.writebacks::writebacks 682241 # number of writebacks system.cpu0.dcache.writebacks::total 682241 # number of writebacks -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1698997 # number of replacements +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1698988 # number of replacements system.cpu0.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 145340473 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1699509 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 85.519096 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.121595 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.542085 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888909 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110434 # Average percentage of cache occupancy +system.cpu0.icache.tags.total_refs 145341295 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1699500 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 85.520032 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7831497000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.113855 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.549824 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888894 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110449 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id @@ -437,44 +437,44 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 77 system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 148739503 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 148739503 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 73956240 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 71384233 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 145340473 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 73956240 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 71384233 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 145340473 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 73956240 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 71384233 # number of overall hits -system.cpu0.icache.overall_hits::total 145340473 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 844112 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 855403 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1699515 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 844112 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 855403 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1699515 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 844112 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 855403 # number of overall misses -system.cpu0.icache.overall_misses::total 1699515 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 74800352 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 72239636 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 147039988 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 74800352 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 72239636 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 147039988 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 74800352 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 72239636 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 147039988 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011285 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011841 # miss rate for ReadReq accesses +system.cpu0.icache.tags.tag_accesses 148740307 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 148740307 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 73948641 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 71392654 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 145341295 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 73948641 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 71392654 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 145341295 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 73948641 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 71392654 # number of overall hits +system.cpu0.icache.overall_hits::total 145341295 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 844220 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 855286 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1699506 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 844220 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 855286 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1699506 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 844220 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 855286 # number of overall misses +system.cpu0.icache.overall_misses::total 1699506 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 74792861 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 72247940 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 147040801 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 74792861 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 72247940 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 147040801 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 74792861 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 72247940 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 147040801 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011287 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011838 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011285 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011841 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011287 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011838 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011285 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011841 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011287 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011838 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -482,9 +482,9 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1698997 # number of writebacks -system.cpu0.icache.writebacks::total 1698997 # number of writebacks -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.writebacks::writebacks 1698988 # number of writebacks +system.cpu0.icache.writebacks::total 1698988 # number of writebacks +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -514,47 +514,47 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 6190 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6190 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 6190 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6190 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6190 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 6189 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6189 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 6189 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6189 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6189 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walksPending::samples 1000002000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000002000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000002000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3698 73.27% 73.27% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::4K 3697 73.27% 73.27% # Table walker page sizes translated system.cpu1.dtb.walker.walkPageSizes::1M 1349 26.73% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5047 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6190 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::total 5046 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6189 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6190 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5047 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6189 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5046 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5047 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 11237 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5046 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 11235 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 15526731 # DTB read hits -system.cpu1.dtb.read_misses 5394 # DTB read misses -system.cpu1.dtb.write_hits 11842705 # DTB write hits -system.cpu1.dtb.write_misses 796 # DTB write misses +system.cpu1.dtb.read_hits 15528433 # DTB read hits +system.cpu1.dtb.read_misses 5402 # DTB read misses +system.cpu1.dtb.write_hits 11842197 # DTB write hits +system.cpu1.dtb.write_misses 787 # DTB write misses system.cpu1.dtb.flush_tlb 2817 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3135 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 3134 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 922 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 916 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 243 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 15532125 # DTB read accesses -system.cpu1.dtb.write_accesses 11843501 # DTB write accesses +system.cpu1.dtb.read_accesses 15533835 # DTB read accesses +system.cpu1.dtb.write_accesses 11842984 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 27369436 # DTB hits -system.cpu1.dtb.misses 6190 # DTB misses -system.cpu1.dtb.accesses 27375626 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 27370630 # DTB hits +system.cpu1.dtb.misses 6189 # DTB misses +system.cpu1.dtb.accesses 27376819 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -584,7 +584,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 3051 # Table walker walks requested system.cpu1.itb.walker.walksShort 3051 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walkWaitTime::samples 3051 # Table walker wait (enqueue to first request) latency @@ -603,7 +603,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2110 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2110 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 5161 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 72237526 # ITB inst hits +system.cpu1.itb.inst_hits 72245830 # ITB inst hits system.cpu1.itb.inst_misses 3051 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -620,54 +620,54 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 72240577 # ITB inst accesses -system.cpu1.itb.hits 72237526 # DTB hits +system.cpu1.itb.inst_accesses 72248881 # ITB inst accesses +system.cpu1.itb.hits 72245830 # DTB hits system.cpu1.itb.misses 3051 # DTB misses -system.cpu1.itb.accesses 72240577 # DTB accesses -system.cpu1.numPwrStateTransitions 3092 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 1546 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1765528734.857697 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 61147535730.449074 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1529 98.90% 98.90% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 14 0.91% 99.81% # Distribution of time spent in the clock gated state +system.cpu1.itb.accesses 72248881 # DTB accesses +system.cpu1.numPwrStateTransitions 3094 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 1547 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1764387509.755010 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 61127772689.263474 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1530 98.90% 98.90% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 14 0.90% 99.81% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.06% 99.87% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.06% 99.94% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::overflows 1 0.06% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 2395080450001 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 1546 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 54346442410 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2729507424090 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 88014282 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 2395080486501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 1547 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 54347237409 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2729507477591 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 88023752 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 70130663 # Number of instructions committed -system.cpu1.committedOps 85818619 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 75668279 # Number of integer alu accesses +system.cpu1.committedInsts 70138211 # Number of instructions committed +system.cpu1.committedOps 85825798 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 75674492 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6211 # Number of float alu accesses -system.cpu1.num_func_calls 8179291 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 9270395 # number of instructions that are conditional controls -system.cpu1.num_int_insts 75668279 # number of integer instructions +system.cpu1.num_func_calls 8180529 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 9271265 # number of instructions that are conditional controls +system.cpu1.num_int_insts 75674492 # number of integer instructions system.cpu1.num_fp_insts 6211 # number of float instructions -system.cpu1.num_int_register_reads 140970750 # number of times the integer registers were read -system.cpu1.num_int_register_writes 52729833 # number of times the integer registers were written +system.cpu1.num_int_register_reads 140981630 # number of times the integer registers were read +system.cpu1.num_int_register_writes 52735108 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4721 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 261966626 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 30529225 # number of times the CC registers were written -system.cpu1.num_mem_refs 28028988 # number of memory refs -system.cpu1.num_load_insts 15690476 # Number of load instructions -system.cpu1.num_store_insts 12338512 # Number of store instructions -system.cpu1.num_idle_cycles 85359668.730648 # Number of idle cycles -system.cpu1.num_busy_cycles 2654613.269352 # Number of busy cycles -system.cpu1.not_idle_fraction 0.030161 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.969839 # Percentage of idle cycles -system.cpu1.Branches 17795727 # Number of branches fetched -system.cpu1.op_class::No_OpClass 150 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 59374032 67.88% 67.88% # Class of executed instruction -system.cpu1.op_class::IntMult 57191 0.07% 67.95% # Class of executed instruction +system.cpu1.num_cc_register_reads 261988380 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 30532586 # number of times the CC registers were written +system.cpu1.num_mem_refs 28030145 # number of memory refs +system.cpu1.num_load_insts 15692181 # Number of load instructions +system.cpu1.num_store_insts 12337964 # Number of store instructions +system.cpu1.num_idle_cycles 85368728.542814 # Number of idle cycles +system.cpu1.num_busy_cycles 2655023.457186 # Number of busy cycles +system.cpu1.not_idle_fraction 0.030163 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.969837 # Percentage of idle cycles +system.cpu1.Branches 17797845 # Number of branches fetched +system.cpu1.op_class::No_OpClass 149 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 59380337 67.88% 67.89% # Class of executed instruction +system.cpu1.op_class::IntMult 57194 0.07% 67.95% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 67.95% # Class of executed instruction @@ -691,16 +691,16 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.95% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4156 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::MemRead 15690476 17.94% 85.89% # Class of executed instruction -system.cpu1.op_class::MemWrite 12338512 14.11% 100.00% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4156 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::MemRead 15692181 17.94% 85.89% # Class of executed instruction +system.cpu1.op_class::MemWrite 12337964 14.11% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 87464517 # Class of executed instruction -system.iobus.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states +system.cpu1.op_class::total 87471981 # Class of executed instruction +system.iobus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -751,14 +751,14 @@ system.iobus.pkt_size_system.bridge.master::total 159061 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909889 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909890 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 227409732009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909889 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 227410176509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.909890 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -766,7 +766,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328176 # Number of tag accesses system.iocache.tags.data_accesses 328176 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses system.iocache.ReadReq_misses::total 240 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -799,29 +799,29 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 109908 # number of replacements -system.l2c.tags.tagsinuse 65155.315514 # Cycle average of tags in use -system.l2c.tags.total_refs 4528029 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 175189 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 25.846537 # Average number of references to valid blocks. +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 109906 # number of replacements +system.l2c.tags.tagsinuse 65155.312233 # Cycle average of tags in use +system.l2c.tags.total_refs 4527993 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 175187 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 25.846627 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48764.089063 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924325 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48764.096462 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924324 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000096 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5143.111803 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4734.405961 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.978702 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4025.485403 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2484.320162 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5146.050132 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4729.659368 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.978701 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4022.536499 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2489.066650 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.744081 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.078478 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.072241 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.078522 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.072169 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.061424 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.037908 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.061379 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.037980 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 65277 # Occupied blocks per task id @@ -833,156 +833,156 @@ system.l2c.tags.age_task_id_blocks_1024::3 10699 # system.l2c.tags.age_task_id_blocks_1024::4 50642 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 40604397 # Number of tag accesses -system.l2c.tags.data_accesses 40604397 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 4717 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2285 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4983 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2429 # number of ReadReq hits -system.l2c.ReadReq_hits::total 14414 # number of ReadReq hits +system.l2c.tags.tag_accesses 40604073 # Number of tag accesses +system.l2c.tags.data_accesses 40604073 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.l2c.ReadReq_hits::cpu0.dtb.walker 4711 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2279 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 4978 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 2423 # number of ReadReq hits +system.l2c.ReadReq_hits::total 14391 # number of ReadReq hits system.l2c.WritebackDirty_hits::writebacks 682241 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 682241 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1666994 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1666994 # number of WritebackClean hits +system.l2c.WritebackClean_hits::writebacks 1666989 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1666989 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 72274 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 78858 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 72332 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 78800 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 151132 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 833349 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 847851 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1681200 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 246710 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 258734 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 505444 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4717 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2285 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 833349 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 318984 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4983 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2429 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 847851 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 337592 # number of demand (read+write) hits -system.l2c.demand_hits::total 2352190 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4717 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2285 # number of overall hits -system.l2c.overall_hits::cpu0.inst 833349 # number of overall hits -system.l2c.overall_hits::cpu0.data 318984 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4983 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2429 # number of overall hits -system.l2c.overall_hits::cpu1.inst 847851 # number of overall hits -system.l2c.overall_hits::cpu1.data 337592 # number of overall hits -system.l2c.overall_hits::total 2352190 # number of overall hits +system.l2c.ReadCleanReq_hits::cpu0.inst 833454 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 847737 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1681191 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 246679 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 258766 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 505445 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4711 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 2279 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 833454 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 319011 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 4978 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 2423 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 847737 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 337566 # number of demand (read+write) hits +system.l2c.demand_hits::total 2352159 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4711 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 2279 # number of overall hits +system.l2c.overall_hits::cpu0.inst 833454 # number of overall hits +system.l2c.overall_hits::cpu0.data 319011 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 4978 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 2423 # number of overall hits +system.l2c.overall_hits::cpu1.inst 847737 # number of overall hits +system.l2c.overall_hits::cpu1.data 337566 # number of overall hits +system.l2c.overall_hits::total 2352159 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::total 8 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1248 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1480 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1250 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1478 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2728 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63973 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 83804 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 147777 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 10754 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 7544 # number of ReadCleanReq misses +system.l2c.ReadExReq_misses::cpu0.data 63990 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 83785 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 147775 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 10757 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 7541 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 9757 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 5806 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 9753 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 5810 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::total 15563 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 10754 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 73730 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 10757 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 73743 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 7544 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 89610 # number of demand (read+write) misses -system.l2c.demand_misses::total 181646 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 7541 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 89595 # number of demand (read+write) misses +system.l2c.demand_misses::total 181644 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 10754 # number of overall misses -system.l2c.overall_misses::cpu0.data 73730 # number of overall misses +system.l2c.overall_misses::cpu0.inst 10757 # number of overall misses +system.l2c.overall_misses::cpu0.data 73743 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu1.inst 7544 # number of overall misses -system.l2c.overall_misses::cpu1.data 89610 # number of overall misses -system.l2c.overall_misses::total 181646 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4722 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 2286 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 4985 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 2429 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 14422 # number of ReadReq accesses(hits+misses) +system.l2c.overall_misses::cpu1.inst 7541 # number of overall misses +system.l2c.overall_misses::cpu1.data 89595 # number of overall misses +system.l2c.overall_misses::total 181644 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4716 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 2280 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 4980 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 2423 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 14399 # number of ReadReq accesses(hits+misses) system.l2c.WritebackDirty_accesses::writebacks 682241 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackDirty_accesses::total 682241 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 1666994 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 1666994 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1260 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1496 # number of UpgradeReq accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 1666989 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 1666989 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1262 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1494 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 136247 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 162662 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 298909 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 844103 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 855395 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1699498 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 256467 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 264540 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 521007 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4722 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 2286 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 844103 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 392714 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 4985 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 2429 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 855395 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 427202 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2533836 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4722 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 2286 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 844103 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 392714 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 4985 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 2429 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 855395 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 427202 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2533836 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000437 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.000555 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990476 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989305 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 136322 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 162585 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 844211 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 855278 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1699489 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 256432 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 264576 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4716 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 2280 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 844211 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 392754 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 4980 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 2423 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 855278 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 427161 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2533803 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4716 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 2280 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 844211 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 392754 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 4980 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 2423 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 855278 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 427161 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2533803 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001060 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000439 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000402 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.000556 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990491 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989290 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.469537 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.515203 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.494388 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.012740 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.008819 # miss rate for ReadCleanReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.469403 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.515330 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.494385 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.012742 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.008817 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.038044 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021948 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.038033 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021960 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::total 0.029871 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000437 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.012740 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.187745 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.008819 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.209760 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001060 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000439 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.012742 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.187759 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000402 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.008817 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.209745 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.071688 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000437 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.012740 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.187745 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.008819 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.209760 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001060 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000439 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.012742 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.187759 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000402 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.008817 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.209745 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.071688 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -990,72 +990,73 @@ system.l2c.blocked::no_mshrs 0 # nu system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 101944 # number of writebacks -system.l2c.writebacks::total 101944 # number of writebacks -system.membus.snoop_filter.tot_requests 367178 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 155396 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.writebacks::writebacks 101943 # number of writebacks +system.l2c.writebacks::total 101943 # number of writebacks +system.membus.snoop_filter.tot_requests 367174 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 155394 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 488 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 40087 # Transaction distribution system.membus.trans_dist::ReadResp 74196 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::WritebackDirty 138134 # Transaction distribution -system.membus.trans_dist::CleanEvict 8204 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138133 # Transaction distribution +system.membus.trans_dist::CleanEvict 8203 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution -system.membus.trans_dist::ReadExReq 145998 # Transaction distribution -system.membus.trans_dist::ReadExResp 145998 # Transaction distribution +system.membus.trans_dist::ReadExReq 145996 # Transaction distribution +system.membus.trans_dist::ReadExResp 145996 # Transaction distribution system.membus.trans_dist::ReadSharedReq 34109 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 506566 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 613926 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 506560 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 613920 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723278 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18091772 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18254745 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18091580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18254553 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20586265 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20586073 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 434811 # Request fanout histogram +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 434807 # Request fanout histogram system.membus.snoop_fanout::mean 0.012707 # Request fanout histogram system.membus.snoop_fanout::stdev 0.112006 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 429286 98.73% 98.73% # Request fanout histogram +system.membus.snoop_fanout::0 429282 98.73% 98.73% # Request fanout histogram system.membus.snoop_fanout::1 5525 1.27% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 434811 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 434807 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1087,71 +1088,72 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5060315 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2540903 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 39264 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 5060295 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2540893 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783853866500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 71253 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2291775 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 71240 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2291754 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 682241 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1698997 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 137147 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1698988 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 137146 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298909 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298909 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1699515 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 521007 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5116071 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581958 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20768 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41564 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7760361 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 217540856 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96320801 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83128 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 313986321 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 115322 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5254527 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.018786 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.135767 # Request fanout histogram +system.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1699506 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5116044 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581955 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20756 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41550 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7760305 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 217539704 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96320737 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41512 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83100 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 313985053 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 115320 # Total snoops (count) +system.toL2Bus.snoopTraffic 6540928 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 5254492 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.018785 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.135764 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5155817 98.12% 98.12% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 98710 1.88% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5155788 98.12% 98.12% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 98704 1.88% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5254527 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5254492 # Request fanout histogram ---------- End Simulation Statistics ---------- |