diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt | 5078 |
1 files changed, 2639 insertions, 2439 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 2d0abc648..cd0cb8f17 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,172 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.398431 # Number of seconds simulated -sim_ticks 47398431268500 # Number of ticks simulated -final_tick 47398431268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.410782 # Number of seconds simulated +sim_ticks 47410781652000 # Number of ticks simulated +final_tick 47410781652000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 671569 # Simulator instruction rate (inst/s) -host_op_rate 790318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37657329129 # Simulator tick rate (ticks/s) -host_mem_usage 861000 # Number of bytes of host memory used -host_seconds 1258.68 # Real time elapsed on the host -sim_insts 845288376 # Number of instructions simulated -sim_ops 994755388 # Number of ops (including micro ops) simulated +host_inst_rate 787433 # Simulator instruction rate (inst/s) +host_op_rate 926573 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41969003911 # Simulator tick rate (ticks/s) +host_mem_usage 699232 # Number of bytes of host memory used +host_seconds 1129.66 # Real time elapsed on the host +sim_insts 889532971 # Number of instructions simulated +sim_ops 1046714541 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 36416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 41984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 768052 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7936536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 44723840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 83456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 97984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 589368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 8667104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 21031552 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 441920 # Number of bytes read from this memory -system.physmem.bytes_read::total 84418212 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 768052 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 589368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1357420 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65101248 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 154432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 156800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3551860 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 14084888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 14587840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 66560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 59904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2809592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 8562400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 11943680 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 428992 # Number of bytes read from this memory +system.physmem.bytes_read::total 56406948 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3551860 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2809592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6361452 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 74353408 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 65122064 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 569 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 656 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 52408 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 124030 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 698810 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1304 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1531 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9297 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 135438 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 328618 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6905 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1359566 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1017207 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 74374224 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2413 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2450 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 95905 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 220098 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 227935 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1040 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 936 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 43988 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 133802 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 186620 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6703 # Number of read requests responded to by this memory +system.physmem.num_reads::total 921890 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1161772 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019810 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 886 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 16204 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 167443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 943572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2067 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 12434 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 182856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 443718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1781034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 16204 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 12434 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 28639 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1373490 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1164375 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 74917 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 297082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 307690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 180600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 251919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9048 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1189749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 74917 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59261 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 134177 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1568281 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1373929 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1373490 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 886 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 16204 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 167882 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 943572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2067 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 12434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 182856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 443718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3154963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1359566 # Number of read requests accepted -system.physmem.writeReqs 1139623 # Number of write requests accepted -system.physmem.readBursts 1359566 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1139623 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 86962304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 49920 # Total number of bytes read from write queue -system.physmem.bytesWritten 72439488 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 84418212 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 72790096 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 780 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7732 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 85004 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 81504 # Per bank write bursts -system.physmem.perBankRdBursts::1 94599 # Per bank write bursts -system.physmem.perBankRdBursts::2 79086 # Per bank write bursts -system.physmem.perBankRdBursts::3 89082 # Per bank write bursts -system.physmem.perBankRdBursts::4 90127 # Per bank write bursts -system.physmem.perBankRdBursts::5 94039 # Per bank write bursts -system.physmem.perBankRdBursts::6 78740 # Per bank write bursts -system.physmem.perBankRdBursts::7 79772 # Per bank write bursts -system.physmem.perBankRdBursts::8 80197 # Per bank write bursts -system.physmem.perBankRdBursts::9 124149 # Per bank write bursts -system.physmem.perBankRdBursts::10 71869 # Per bank write bursts -system.physmem.perBankRdBursts::11 83577 # Per bank write bursts -system.physmem.perBankRdBursts::12 73174 # Per bank write bursts -system.physmem.perBankRdBursts::13 83519 # Per bank write bursts -system.physmem.perBankRdBursts::14 78794 # Per bank write bursts -system.physmem.perBankRdBursts::15 76558 # Per bank write bursts -system.physmem.perBankWrBursts::0 70549 # Per bank write bursts -system.physmem.perBankWrBursts::1 76959 # Per bank write bursts -system.physmem.perBankWrBursts::2 69527 # Per bank write bursts -system.physmem.perBankWrBursts::3 76268 # Per bank write bursts -system.physmem.perBankWrBursts::4 71760 # Per bank write bursts -system.physmem.perBankWrBursts::5 76111 # Per bank write bursts -system.physmem.perBankWrBursts::6 67646 # Per bank write bursts -system.physmem.perBankWrBursts::7 68141 # Per bank write bursts -system.physmem.perBankWrBursts::8 69345 # Per bank write bursts -system.physmem.perBankWrBursts::9 72887 # Per bank write bursts -system.physmem.perBankWrBursts::10 65485 # Per bank write bursts -system.physmem.perBankWrBursts::11 73987 # Per bank write bursts -system.physmem.perBankWrBursts::12 65828 # Per bank write bursts -system.physmem.perBankWrBursts::13 73935 # Per bank write bursts -system.physmem.perBankWrBursts::14 66021 # Per bank write bursts -system.physmem.perBankWrBursts::15 67418 # Per bank write bursts +system.physmem.bw_write::total 1568720 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1568281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 74917 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 297521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 307690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 180600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 251919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2758469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 921890 # Number of read requests accepted +system.physmem.writeReqs 1829645 # Number of write requests accepted +system.physmem.readBursts 921890 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1829645 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 58978368 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 22592 # Total number of bytes read from write queue +system.physmem.bytesWritten 116660480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 56406948 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 116951504 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 353 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6803 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 114603 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 54393 # Per bank write bursts +system.physmem.perBankRdBursts::1 56084 # Per bank write bursts +system.physmem.perBankRdBursts::2 54659 # Per bank write bursts +system.physmem.perBankRdBursts::3 58883 # Per bank write bursts +system.physmem.perBankRdBursts::4 54974 # Per bank write bursts +system.physmem.perBankRdBursts::5 58047 # Per bank write bursts +system.physmem.perBankRdBursts::6 51881 # Per bank write bursts +system.physmem.perBankRdBursts::7 58759 # Per bank write bursts +system.physmem.perBankRdBursts::8 52533 # Per bank write bursts +system.physmem.perBankRdBursts::9 95950 # Per bank write bursts +system.physmem.perBankRdBursts::10 53815 # Per bank write bursts +system.physmem.perBankRdBursts::11 56993 # Per bank write bursts +system.physmem.perBankRdBursts::12 52328 # Per bank write bursts +system.physmem.perBankRdBursts::13 55917 # Per bank write bursts +system.physmem.perBankRdBursts::14 52932 # Per bank write bursts +system.physmem.perBankRdBursts::15 53389 # Per bank write bursts +system.physmem.perBankWrBursts::0 113787 # Per bank write bursts +system.physmem.perBankWrBursts::1 117144 # Per bank write bursts +system.physmem.perBankWrBursts::2 115098 # Per bank write bursts +system.physmem.perBankWrBursts::3 118536 # Per bank write bursts +system.physmem.perBankWrBursts::4 116769 # Per bank write bursts +system.physmem.perBankWrBursts::5 120895 # Per bank write bursts +system.physmem.perBankWrBursts::6 109520 # Per bank write bursts +system.physmem.perBankWrBursts::7 112924 # Per bank write bursts +system.physmem.perBankWrBursts::8 111914 # Per bank write bursts +system.physmem.perBankWrBursts::9 117541 # Per bank write bursts +system.physmem.perBankWrBursts::10 111832 # Per bank write bursts +system.physmem.perBankWrBursts::11 116807 # Per bank write bursts +system.physmem.perBankWrBursts::12 108182 # Per bank write bursts +system.physmem.perBankWrBursts::13 109739 # Per bank write bursts +system.physmem.perBankWrBursts::14 110202 # Per bank write bursts +system.physmem.perBankWrBursts::15 111930 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 47398428076000 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 47410778671000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1316329 # Read request sizes (log2) +system.physmem.readPktSize::6 878653 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1137020 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 566894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 282234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 134057 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 101972 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 67644 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 58693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 53670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 46721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 35916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1955 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 709 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 75 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1827042 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 652905 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 75815 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 40303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 29162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 25818 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 22543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 19321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2492 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see @@ -188,158 +188,182 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 16911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 22466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 30737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 39170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 50283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 58139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 68202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 72051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 76579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 76851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 78478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 78341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 80363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 74556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 75992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 78312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 75395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 11828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 7611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 648906 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 245.646870 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 142.183985 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 295.195613 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 325424 50.15% 50.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 135792 20.93% 71.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 50411 7.77% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 26706 4.12% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22287 3.43% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 16108 2.48% 88.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10950 1.69% 90.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 13619 2.10% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 47609 7.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 648906 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 58676 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.156827 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 139.787244 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 58673 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 54841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 74169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 96317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 106970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 112981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 116642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 107891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 106380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 108843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 109894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 108607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 105867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 106408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 98436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 96529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 94372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 91211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 6 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1000117 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 175.617981 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 106.594305 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 248.236984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 645970 64.59% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 191036 19.10% 83.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 45051 4.50% 88.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21747 2.17% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15328 1.53% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10644 1.06% 92.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8285 0.83% 93.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7295 0.73% 94.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 54761 5.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1000117 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 87721 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 10.505238 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 108.849756 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 87718 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-25599 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 58676 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 58676 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.290119 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.850822 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.308232 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 54948 93.65% 93.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 970 1.65% 95.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 598 1.02% 96.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 219 0.37% 96.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 626 1.07% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 147 0.25% 98.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 195 0.33% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 132 0.22% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 184 0.31% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 81 0.14% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 205 0.35% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 24 0.04% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 63 0.11% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 38 0.06% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 129 0.22% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 15 0.03% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 27 0.05% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 11 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 19 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 8 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 11 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 6 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 58676 # Writes before turning the bus around for reads -system.physmem.totQLat 69966976258 # Total ticks spent queuing -system.physmem.totMemAccLat 95444213758 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6793930000 # Total ticks spent in databus transfers -system.physmem.avgQLat 51492.27 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 87721 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 87721 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.779745 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.605058 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.125024 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 56948 64.92% 64.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 16031 18.27% 83.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 6972 7.95% 91.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 3738 4.26% 95.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 1084 1.24% 96.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 357 0.41% 97.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 239 0.27% 97.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 271 0.31% 97.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 649 0.74% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 108 0.12% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 85 0.10% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 76 0.09% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 135 0.15% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 76 0.09% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 51 0.06% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 73 0.08% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 134 0.15% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 41 0.05% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 31 0.04% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 49 0.06% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 179 0.20% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 16 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 31 0.04% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 14 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 43 0.05% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 12 0.01% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 20 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 30 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 97 0.11% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 18 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 14 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 10 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 13 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 11 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 6 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 6 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 14 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 12 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 4 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 87721 # Writes before turning the bus around for reads +system.physmem.totQLat 32913462781 # Total ticks spent queuing +system.physmem.totMemAccLat 50192281531 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4607685000 # Total ticks spent in databus transfers +system.physmem.avgQLat 35715.83 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 70242.27 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.83 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.53 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.78 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 54465.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.46 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.47 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing -system.physmem.readRowHits 1114788 # Number of row buffer hits during reads -system.physmem.writeRowHits 726958 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 64.23 # Row buffer hit rate for writes -system.physmem.avgGap 18965523.65 # Average gap between requests -system.physmem.pageHitRate 73.95 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 45538400789750 # Time in different power states -system.physmem.memoryStateTime::REF 1582737780000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 277292625250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2564850960 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 2340878400 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1399472250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1277265000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 5358202200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 5240320800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 3738707280 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3595790880 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3095835097680 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3095835097680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1171174509540 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1161726671475 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 27411712647750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 27420000225000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 31691783487660 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 31690016249235 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.625157 # Core power per rank (mW) -system.physmem.averagePower::1 668.587872 # Core power per rank (mW) +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing +system.physmem.readRowHits 687654 # Number of row buffer hits during reads +system.physmem.writeRowHits 1056585 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.96 # Row buffer hit rate for writes +system.physmem.avgGap 17230665.31 # Average gap between requests +system.physmem.pageHitRate 63.56 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3832851960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2091337875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3491865000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5991881040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3096641673840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1200455054145 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27393437346750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31705942010610 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.749637 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45570820980751 # Time in different power states +system.physmem_0.memoryStateTime::REF 1583150140000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 256810103749 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3728032560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2034144750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3696084600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5819992560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3096641673840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1191404828700 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27401376141000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31704700898010 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.723459 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45584059811251 # Time in different power states +system.physmem_1.memoryStateTime::REF 1583150140000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 243570222499 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -373,6 +397,14 @@ system.cf0.dma_write_full_pages 1670 # Nu system.cf0.dma_write_bytes 6842880 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1673 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -394,27 +426,74 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 107972 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 107972 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9276 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 83163 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 107963 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 107963 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 107963 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 92448 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 17595.764614 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 15306.328665 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 15454.252367 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 91009 98.44% 98.44% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1235 1.34% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 66 0.07% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 55 0.06% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 65 0.07% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 92448 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples -2398441544 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.163884 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.370170 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -2005375084 83.61% 83.61% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -393066460 16.39% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total -2398441544 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 83163 89.97% 89.97% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 9276 10.03% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 92439 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 107972 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 107972 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 92439 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 92439 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 200411 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 74706058 # DTB read hits -system.cpu0.dtb.read_misses 64792 # DTB read misses -system.cpu0.dtb.write_hits 67192400 # DTB write hits -system.cpu0.dtb.write_misses 21129 # DTB write misses +system.cpu0.dtb.read_hits 83792624 # DTB read hits +system.cpu0.dtb.read_misses 78614 # DTB read misses +system.cpu0.dtb.write_hits 76883618 # DTB write hits +system.cpu0.dtb.write_misses 29358 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 33482 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 38297 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 3817 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4651 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 8375 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 74770850 # DTB read accesses -system.cpu0.dtb.write_accesses 67213529 # DTB write accesses +system.cpu0.dtb.perms_faults 10679 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 83871238 # DTB read accesses +system.cpu0.dtb.write_accesses 76912976 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 141898458 # DTB hits -system.cpu0.dtb.misses 85921 # DTB misses -system.cpu0.dtb.accesses 141984379 # DTB accesses +system.cpu0.dtb.hits 160676242 # DTB hits +system.cpu0.dtb.misses 107972 # DTB misses +system.cpu0.dtb.accesses 160784214 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -436,201 +515,236 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 397874920 # ITB inst hits -system.cpu0.itb.inst_misses 49120 # ITB inst misses +system.cpu0.itb.walker.walks 64255 # Table walker walks requested +system.cpu0.itb.walker.walksLong 64255 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 637 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58227 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 64255 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 64255 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 64255 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 58864 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 20635.902164 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 17664.674655 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 19771.927470 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 57276 97.30% 97.30% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1371 2.33% 99.63% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 47 0.08% 99.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 91 0.15% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 53 0.09% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 19 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 58864 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples -673300296 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -673300296 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total -673300296 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 58227 98.92% 98.92% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 637 1.08% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 58864 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 64255 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 64255 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 58864 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 58864 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 123119 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 448595101 # ITB inst hits +system.cpu0.itb.inst_misses 64255 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 23760 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26739 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 397924040 # ITB inst accesses -system.cpu0.itb.hits 397874920 # DTB hits -system.cpu0.itb.misses 49120 # DTB misses -system.cpu0.itb.accesses 397924040 # DTB accesses -system.cpu0.numCycles 94796862537 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 448659356 # ITB inst accesses +system.cpu0.itb.hits 448595101 # DTB hits +system.cpu0.itb.misses 64255 # DTB misses +system.cpu0.itb.accesses 448659356 # DTB accesses +system.cpu0.numCycles 94821563304 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 397643174 # Number of instructions committed -system.cpu0.committedOps 466635553 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 429030148 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 322477 # Number of float alu accesses -system.cpu0.num_func_calls 23930039 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 59901605 # number of instructions that are conditional controls -system.cpu0.num_int_insts 429030148 # number of integer instructions -system.cpu0.num_fp_insts 322477 # number of float instructions -system.cpu0.num_int_register_reads 621630892 # number of times the integer registers were read -system.cpu0.num_int_register_writes 340702516 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 547437 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 211832 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 102593685 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 102325899 # number of times the CC registers were written -system.cpu0.num_mem_refs 141893093 # number of memory refs -system.cpu0.num_load_insts 74704433 # Number of load instructions -system.cpu0.num_store_insts 67188660 # Number of store instructions -system.cpu0.num_idle_cycles 93886429062.298019 # Number of idle cycles -system.cpu0.num_busy_cycles 910433474.701981 # Number of busy cycles -system.cpu0.not_idle_fraction 0.009604 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.990396 # Percentage of idle cycles -system.cpu0.Branches 88352328 # Number of branches fetched -system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 323823287 69.35% 69.35% # Class of executed instruction -system.cpu0.op_class::IntMult 1114929 0.24% 69.59% # Class of executed instruction -system.cpu0.op_class::IntDiv 56737 0.01% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 22377 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::MemRead 74704433 16.00% 85.61% # Class of executed instruction -system.cpu0.op_class::MemWrite 67188660 14.39% 100.00% # Class of executed instruction +system.cpu0.committedInsts 448345930 # Number of instructions committed +system.cpu0.committedOps 527651436 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 484594714 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 558267 # Number of float alu accesses +system.cpu0.num_func_calls 26890258 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 68074268 # number of instructions that are conditional controls +system.cpu0.num_int_insts 484594714 # number of integer instructions +system.cpu0.num_fp_insts 558267 # number of float instructions +system.cpu0.num_int_register_reads 706750752 # number of times the integer registers were read +system.cpu0.num_int_register_writes 384547382 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 893879 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 490056 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 117567828 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 117277075 # number of times the CC registers were written +system.cpu0.num_mem_refs 160668093 # number of memory refs +system.cpu0.num_load_insts 83788812 # Number of load instructions +system.cpu0.num_store_insts 76879281 # Number of store instructions +system.cpu0.num_idle_cycles 93729284290.716034 # Number of idle cycles +system.cpu0.num_busy_cycles 1092279013.283977 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011519 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988481 # Percentage of idle cycles +system.cpu0.Branches 100174256 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 365953478 69.32% 69.32% # Class of executed instruction +system.cpu0.op_class::IntMult 1186010 0.22% 69.54% # Class of executed instruction +system.cpu0.op_class::IntDiv 57830 0.01% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 78277 0.01% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::MemRead 83788812 15.87% 85.44% # Class of executed instruction +system.cpu0.op_class::MemWrite 76879281 14.56% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 466910423 # Class of executed instruction +system.cpu0.op_class::total 527943731 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5105 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 4859280 # number of replacements -system.cpu0.dcache.tags.tagsinuse 480.680410 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 136835586 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 4859789 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.156693 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 3644536500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.680410 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938829 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.938829 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 406 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 9 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 288671468 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 288671468 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 69599952 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 69599952 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 63413457 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 63413457 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 173858 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 173858 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 133135 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 133135 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1596886 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1596886 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1561841 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1561841 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 133013409 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 133013409 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 133187267 # number of overall hits -system.cpu0.dcache.overall_hits::total 133187267 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2622769 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 2622769 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1185607 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1185607 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 553155 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 553155 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 697992 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 697992 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 145021 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 145021 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 178721 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 178721 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3808376 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3808376 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4361531 # number of overall misses -system.cpu0.dcache.overall_misses::total 4361531 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36725560788 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 36725560788 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 18496940456 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 18496940456 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 11951080104 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 11951080104 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2007745317 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2007745317 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3807661334 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3807661334 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 927000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 927000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 55222501244 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 55222501244 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 55222501244 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 55222501244 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 72222721 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 72222721 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 64599064 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 64599064 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 727013 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 727013 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 831127 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 831127 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1741907 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1741907 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1740562 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1740562 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 136821785 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 136821785 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 137548798 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 137548798 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036315 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036315 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018353 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018353 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760860 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760860 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839814 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.839814 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083254 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083254 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.102680 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.102680 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027835 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.027835 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031709 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.031709 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14002.590693 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14002.590693 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15601.240931 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15601.240931 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 17122.087508 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 17122.087508 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13844.514360 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13844.514360 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21305.058354 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21305.058354 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 5474 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 5753925 # number of replacements +system.cpu0.dcache.tags.tagsinuse 509.684776 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 154679022 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5754435 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 26.879967 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 3644714000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 509.684776 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.995478 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.995478 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 327127592 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 327127592 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 77833401 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 77833401 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72535559 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 72535559 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 180949 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 180949 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 117408 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 117408 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1813577 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1813577 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1784599 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1784599 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 150368960 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 150368960 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 150549909 # number of overall hits +system.cpu0.dcache.overall_hits::total 150549909 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3079415 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3079415 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1439122 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1439122 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 698265 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 698265 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 782756 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 782756 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 172905 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 172905 # 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average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13677.300146 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -639,92 +753,92 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3276433 # number of writebacks -system.cpu0.dcache.writebacks::total 3276433 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 20828 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 20828 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21424 # 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number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3853276103 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2137000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2137000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 60374766761 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 60374766761 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 74608980433 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 74608980433 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2287793998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2287793998 # 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Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 800019748 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 800019748 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 393605012 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 393605012 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 393605012 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 393605012 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 393605012 # number of overall hits -system.cpu0.icache.overall_hits::total 393605012 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 4269908 # 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average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 7315.290733 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7315.290733 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 7315.290733 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011518 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011518 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011518 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8888.035572 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8888.035572 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8888.035572 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 45505774 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2657797 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 39900232 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 8744 # number of hwpf that were already in the prefetch queue -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 580 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 2938421 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 3808538 # number of hwpf spanning a virtual page -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 3291824 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16191.272385 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 9909292 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 3307923 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 2.995624 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 16044231500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 5217.724609 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 49.949148 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 58.574202 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 727.292976 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2667.900561 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7469.830889 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.318465 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003049 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003575 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.044390 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.162836 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.455922 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.988237 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8632 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 100 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7367 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 22 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 210 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1111 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 7012 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 277 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 77 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1042 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1532 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4604 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 127 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.526855 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006104 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.449646 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 215960486 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 215960486 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 166834 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 106498 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4104943 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2390641 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 6768916 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 3276433 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 3276433 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 610572 # number of WriteInvalidateReq hits -system.cpu0.l2cache.WriteInvalidateReq_hits::total 610572 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 75583 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 75583 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 31346 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 31346 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 814537 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 814537 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 166834 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 106498 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4104943 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3205178 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 7583453 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 166834 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 106498 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4104943 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3205178 # number of overall hits -system.cpu0.l2cache.overall_hits::total 7583453 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 9451 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7593 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 164965 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 871580 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1053589 # number of ReadReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 86357 # number of WriteInvalidateReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::total 86357 # number of WriteInvalidateReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 106896 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 106896 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 147374 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 147374 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 172967 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 172967 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 9451 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7593 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 164965 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1044547 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1226556 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 9451 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7593 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 164965 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1044547 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1226556 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 247144715 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 215825476 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 4449371565 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 25701723776 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 30614065532 # number of ReadReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 5651418353 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 5651418353 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2080242902 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 2080242902 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2994303005 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2994303005 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 855000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 855000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 6538293027 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 6538293027 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 247144715 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 215825476 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4449371565 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 32240016803 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 37152358559 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 247144715 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 215825476 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4449371565 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 32240016803 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 37152358559 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 176285 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 114091 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 4269908 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3262221 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 7822505 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 3276433 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 3276433 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 696929 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::total 696929 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 182479 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 182479 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 178720 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 178720 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 987504 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 987504 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 176285 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 114091 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 4269908 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 4249725 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 8810009 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 176285 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 114091 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 4269908 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 4249725 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 8810009 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.053612 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.066552 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.038634 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.267174 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.134687 # miss rate for ReadReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.123911 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.123911 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.585799 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.585799 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.824608 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.824608 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7865373 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7866135 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 648 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu0.l2cache.prefetcher.pfSpanPage 985913 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2427001 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16243.780061 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 11146490 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2442996 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 4.562631 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 4729494500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 7283.700781 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 78.630524 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 92.657228 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3931.432813 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3992.358247 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 865.000469 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.444562 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004799 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005655 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.239956 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.243674 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.052795 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.991442 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1466 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14457 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 31 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 296 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 826 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 313 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 23 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 41 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # 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mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.056539 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.099515 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242001 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.469001 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 21780.932052 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22395.109853 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22273.429726 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43752.426923 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 43752.426923 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 18274.092453 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 18274.092453 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16661.502488 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16661.502488 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13865.687238 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13865.687238 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 687000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 687000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29683.053592 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29683.053592 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 21780.932052 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 23590.654453 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23328.795643 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 21780.932052 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 23590.654453 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43752.426923 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37852.554233 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231978 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 26026.451805 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25072.510487 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49425.192319 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49425.192319 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 34326.997887 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34326.997887 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16986.530742 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16986.530742 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13741.236699 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13741.236699 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 214125 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 214125 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36924.550389 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36924.550389 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28227.276368 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26740.395420 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28227.276368 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49425.192319 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33232.542850 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1180,59 +1292,67 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 11465749 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 8074092 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 15773 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 15773 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3276433 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 4228803 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 811507 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 696929 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 407420 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 328722 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 423022 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1108208 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 995011 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 8626066 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 14109371 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 260774 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 426575 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 23422786 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 273446612 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 532438419 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 912728 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1410280 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 808208039 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 8581549 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 21569506 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.385644 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.486747 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 11541292 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9690709 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 15329 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 15329 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3895213 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1069383 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1166255 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 781481 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 444610 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 368177 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 498972 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1328849 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1215209 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 10420426 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16690518 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 351532 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 549297 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 28011773 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 330866132 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 630631769 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1276280 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1881728 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 964655909 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4194903 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 19756578 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.197801 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.398341 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 13251364 61.44% 61.44% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 8318142 38.56% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 15848715 80.22% 80.22% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 3907863 19.78% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 21569506 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 10644176370 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 19756578 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 12645685295 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 173370992 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 194485993 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 6459583336 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7813325558 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 6973558574 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8298663367 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 146771777 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 192341003 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 250366041 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 314436506 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1254,27 +1374,82 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 99527 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 99527 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9603 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 74573 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 99518 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.271308 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 67.169326 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 99516 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::18432-20479 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 99518 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 84185 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 16581.674289 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 15037.130908 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 10932.627488 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 81471 96.78% 96.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2185 2.60% 99.37% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 285 0.34% 99.71% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 159 0.19% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 19 0.02% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 14 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 18 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 4 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 15 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 84185 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1589468256 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.778279 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.415405 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -352419148 22.17% 22.17% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -1237049108 77.83% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1589468256 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 74574 88.59% 88.59% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 9603 11.41% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 84177 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 99527 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 99527 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84177 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84177 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 183704 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 84980512 # DTB read hits -system.cpu1.dtb.read_misses 74547 # DTB read misses -system.cpu1.dtb.write_hits 77969612 # DTB write hits -system.cpu1.dtb.write_misses 26781 # DTB write misses +system.cpu1.dtb.read_hits 83767099 # DTB read hits +system.cpu1.dtb.read_misses 74857 # DTB read misses +system.cpu1.dtb.write_hits 75685520 # DTB write hits +system.cpu1.dtb.write_misses 24670 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 37319 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 36584 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4156 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4104 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10210 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 85055059 # DTB read accesses -system.cpu1.dtb.write_accesses 77996393 # DTB write accesses +system.cpu1.dtb.perms_faults 9015 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 83841956 # DTB read accesses +system.cpu1.dtb.write_accesses 75710190 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 162950124 # DTB hits -system.cpu1.dtb.misses 101328 # DTB misses -system.cpu1.dtb.accesses 163051452 # DTB accesses +system.cpu1.dtb.hits 159452619 # DTB hits +system.cpu1.dtb.misses 99527 # DTB misses +system.cpu1.dtb.accesses 159552146 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1296,201 +1471,239 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 447940407 # ITB inst hits -system.cpu1.itb.inst_misses 68561 # ITB inst misses +system.cpu1.itb.walker.walks 55326 # Table walker walks requested +system.cpu1.itb.walker.walksLong 55326 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 571 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 49211 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 55326 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 55326 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 55326 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 49782 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 18533.691816 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 16693.913266 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 13345.941074 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 47101 94.61% 94.61% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 2168 4.35% 98.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 178 0.36% 99.33% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 248 0.50% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 12 0.02% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 16 0.03% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 24 0.05% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 6 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 18 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 3 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 49782 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1199136648 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1199136648 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1199136648 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 49211 98.85% 98.85% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 571 1.15% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 49782 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 55326 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 55326 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49782 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49782 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 105108 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 441493680 # ITB inst hits +system.cpu1.itb.inst_misses 55326 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26339 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25739 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 448008968 # ITB inst accesses -system.cpu1.itb.hits 447940407 # DTB hits -system.cpu1.itb.misses 68561 # DTB misses -system.cpu1.itb.accesses 448008968 # DTB accesses -system.cpu1.numCycles 94796862537 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 441549006 # ITB inst accesses +system.cpu1.itb.hits 441493680 # DTB hits +system.cpu1.itb.misses 55326 # DTB misses +system.cpu1.itb.accesses 441549006 # DTB accesses +system.cpu1.numCycles 94821563303 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 447645202 # Number of instructions committed -system.cpu1.committedOps 528119835 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 486291398 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 624474 # Number of float alu accesses -system.cpu1.num_func_calls 27450761 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 67545606 # number of instructions that are conditional controls -system.cpu1.num_int_insts 486291398 # number of integer instructions -system.cpu1.num_fp_insts 624474 # number of float instructions -system.cpu1.num_int_register_reads 698728829 # number of times the integer registers were read -system.cpu1.num_int_register_writes 384530758 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 985803 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 576512 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 114161169 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 113813296 # number of times the CC registers were written -system.cpu1.num_mem_refs 162934099 # number of memory refs -system.cpu1.num_load_insts 84972579 # Number of load instructions -system.cpu1.num_store_insts 77961520 # Number of store instructions -system.cpu1.num_idle_cycles 93770083152.566025 # Number of idle cycles -system.cpu1.num_busy_cycles 1026779384.433978 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010831 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989169 # Percentage of idle cycles -system.cpu1.Branches 100081816 # Number of branches fetched -system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 364276895 68.94% 68.94% # Class of executed instruction -system.cpu1.op_class::IntMult 1051011 0.20% 69.14% # Class of executed instruction -system.cpu1.op_class::IntDiv 60606 0.01% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 92495 0.02% 69.17% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.17% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.17% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.17% # Class of executed instruction -system.cpu1.op_class::MemRead 84972579 16.08% 85.25% # Class of executed instruction -system.cpu1.op_class::MemWrite 77961520 14.75% 100.00% # Class of executed instruction +system.cpu1.committedInsts 441187041 # Number of instructions committed +system.cpu1.committedOps 519063105 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 477531543 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 364386 # Number of float alu accesses +system.cpu1.num_func_calls 26570520 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 66815511 # number of instructions that are conditional controls +system.cpu1.num_int_insts 477531543 # number of integer instructions +system.cpu1.num_fp_insts 364386 # number of float instructions +system.cpu1.num_int_register_reads 690361032 # number of times the integer registers were read +system.cpu1.num_int_register_writes 378560518 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 602629 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 273816 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 113424708 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 113111436 # number of times the CC registers were written +system.cpu1.num_mem_refs 159443034 # number of memory refs +system.cpu1.num_load_insts 83763663 # Number of load instructions +system.cpu1.num_store_insts 75679371 # Number of store instructions +system.cpu1.num_idle_cycles 93795188251.508850 # Number of idle cycles +system.cpu1.num_busy_cycles 1026375051.491154 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010824 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989176 # Percentage of idle cycles +system.cpu1.Branches 98214896 # Number of branches fetched +system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 358777055 69.08% 69.08% # Class of executed instruction +system.cpu1.op_class::IntMult 1052972 0.20% 69.28% # Class of executed instruction +system.cpu1.op_class::IntDiv 61499 0.01% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 35293 0.01% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::MemRead 83763663 16.13% 85.43% # Class of executed instruction +system.cpu1.op_class::MemWrite 75679371 14.57% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 528415149 # Class of executed instruction +system.cpu1.op_class::total 519369853 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13701 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 5194711 # number of replacements -system.cpu1.dcache.tags.tagsinuse 457.134068 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 157559099 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5195223 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 30.327687 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8367548601000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.134068 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.892840 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.892840 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 331059949 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 331059949 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 79405575 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 79405575 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 74066119 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 74066119 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 191889 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 191889 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 197632 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 197632 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1669680 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1669680 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1654141 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1654141 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 153471694 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 153471694 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 153663583 # number of overall hits -system.cpu1.dcache.overall_hits::total 153663583 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2946837 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2946837 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1283113 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1283113 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 571898 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 571898 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 550709 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 550709 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 171203 # 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number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 6595698094 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2383654561 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2383654561 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3901847697 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3901847697 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1095500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1095500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 60528748887 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 60528748887 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 60528748887 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1840883 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1839669 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1839669 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 157701644 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 157701644 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 158465431 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 158465431 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035783 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017029 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.017029 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.748766 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.748766 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.735906 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.735906 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.093000 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.093000 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100849 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100849 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026822 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026822 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030302 # 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average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21031.044893 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 13999 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 4977655 # number of replacements +system.cpu1.dcache.tags.tagsinuse 421.597899 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 154271186 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4978165 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 30.989569 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8379002972500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.597899 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823433 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.823433 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 442 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 323862009 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 323862009 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 78232018 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 78232018 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 71864508 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 71864508 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 191698 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 191698 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 211446 # 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number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1966000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1966000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 59961592307 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 59961592307 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 59961592307 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 59961592307 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 81102062 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 81102062 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 73100357 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 73100357 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 766582 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 766582 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 680241 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 680241 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1874166 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1874166 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1872599 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1872599 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 154202419 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 154202419 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 154969001 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 154969001 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035388 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035388 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.016906 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.016906 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.749932 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.749932 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.689160 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.689160 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086146 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086146 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106476 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106476 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026627 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026627 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030205 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.030205 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13728.194596 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13728.194596 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16637.202260 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16637.202260 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 25851.783916 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 25851.783916 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14296.089593 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14296.089593 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21372.987346 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21372.987346 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14309.566044 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14309.566044 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12605.302976 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 12605.302976 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14603.788337 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14603.788337 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12810.179230 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 12810.179230 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1499,92 +1712,92 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3397427 # number of writebacks -system.cpu1.dcache.writebacks::total 3397427 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 14736 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 14736 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 407 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 407 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 48814 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 48814 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 15143 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 15143 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 15143 # 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number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 11612454284 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 5490664906 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 5490664906 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1373965707 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1373965707 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3521472303 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3521472303 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1037500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1037500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 51359578044 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 51359578044 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 62972032328 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 62972032328 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3972621225 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3972621225 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3807943973 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3807943973 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7780565198 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7780565198 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035604 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035604 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017023 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017023 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.748766 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.748766 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.735906 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.735906 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066484 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066484 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100849 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100849 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026726 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026726 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030207 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030207 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11822.914496 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11822.914496 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13014.360756 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13014.360756 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20305.114346 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20305.114346 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 9970.174640 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 9970.174640 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11226.218917 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11226.218917 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18980.813155 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18980.813155 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3230902 # number of writebacks +system.cpu1.dcache.writebacks::total 3230902 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 11797 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 11797 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 280 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 280 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 42800 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 42800 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 12077 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 12077 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 12077 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 12077 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2858247 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2858247 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1235569 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1235569 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 574884 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 574884 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 468795 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 468795 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 118652 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 118652 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199386 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 199386 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4093816 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4093816 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4668700 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4668700 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 33045194740 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 33045194740 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 18021373474 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 18021373474 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10397149259 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 10397149259 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11178014959 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11178014959 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1426804491 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1426804491 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3852246545 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3852246545 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1872000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1872000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 51066568214 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 51066568214 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 61463717473 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 61463717473 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4074474250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4074474250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3958410750 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3958410750 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8032885000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8032885000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035243 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035243 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016902 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.016902 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.749932 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.749932 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.689160 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.689160 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063309 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063309 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106476 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106476 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026548 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026548 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030127 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030127 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11561.350275 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11561.350275 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14585.485290 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14585.485290 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18085.647294 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18085.647294 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 23844.142875 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 23844.142875 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12025.119602 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12025.119602 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19320.546804 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19320.546804 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12185.511233 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12185.511233 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13155.611705 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13155.611705 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12474.075096 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12474.075096 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13165.060396 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13165.060396 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1592,59 +1805,59 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5786522 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.339295 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 442153368 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5787034 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 76.404142 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8367526246000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.339295 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969413 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969413 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 4937125 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.391317 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 436556038 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4937637 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 88.413960 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8378975635000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.391317 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969514 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969514 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 239 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 901667853 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 901667853 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 442153368 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 442153368 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 442153368 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 442153368 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 442153368 # number of overall hits -system.cpu1.icache.overall_hits::total 442153368 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5787039 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5787039 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5787039 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5787039 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5787039 # number of overall misses -system.cpu1.icache.overall_misses::total 5787039 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 50052191468 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 50052191468 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 50052191468 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 50052191468 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 50052191468 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 50052191468 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 447940407 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 447940407 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 447940407 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 447940407 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 447940407 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 447940407 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.012919 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.012919 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.012919 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.012919 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.012919 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.012919 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8649.015752 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8649.015752 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8649.015752 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8649.015752 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8649.015752 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8649.015752 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 887925002 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 887925002 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 436556038 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 436556038 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 436556038 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 436556038 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 436556038 # number of overall hits +system.cpu1.icache.overall_hits::total 436556038 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4937642 # 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miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10295.576387 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10295.576387 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10295.576387 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10295.576387 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10295.576387 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10295.576387 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1653,384 +1866,377 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # 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number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 41368714588 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 41368714588 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9075250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9075250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9075250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 9075250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.012919 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.012919 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.012919 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.012919 # 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mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8792.521537 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8792.521537 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8792.521537 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # 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Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6824.630764 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.216571 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003566 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004009 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.046289 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.151194 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.416542 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.838171 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8592 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 40 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 7474 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 93 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 541 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2721 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4842 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 395 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 15 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 810 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3409 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2963 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 229 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.524414 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002441 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.456177 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 249010603 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 249010603 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 204488 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 158918 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5602514 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2695724 # 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number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 29755594933 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 7736539648 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 7736539648 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2151571523 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2151571523 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2290441908 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2290441908 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1495999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1495999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 6293487581 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 6293487581 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 203741250 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 170362507 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 10812394931 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 25372226222 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 36558724910 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 203741250 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 170362507 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 10812394931 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 25372226222 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 29755594933 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 66314319843 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8087000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3880010250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3888097250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3784845500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3784845500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8087000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7664855750 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7672942750 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.041303 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.052181 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.099533 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.240390 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.153988 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.087836 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.087836 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.591620 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.591620 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.808666 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.808666 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.611609 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.611609 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.682408 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.682408 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.840661 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.840661 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.176371 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.176371 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.051364 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.057789 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026944 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.237888 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119344 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.051364 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.057789 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026944 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.237888 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.193226 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.193226 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.041303 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.052181 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.099533 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.229620 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.158158 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.041303 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.052181 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.099533 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.229620 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.370592 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21030.079325 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 22855.890509 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22639.849443 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25466.057437 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 25466.057437 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 15325.803477 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 15325.803477 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16571.950039 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16571.950039 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13824.139322 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13824.139322 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 201375 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 201375 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 27369.696466 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27369.696466 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21030.079325 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23632.313965 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23342.822566 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21030.079325 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23632.313965 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25466.057437 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24782.300723 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.222784 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 22345.362493 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22234.428550 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46551.597527 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46551.597527 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27079.147948 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 27079.147948 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16917.663474 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16917.663474 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13665.224287 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13665.224287 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 249333.166667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 249333.166667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30989.120825 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30989.120825 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24006.292202 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23371.034447 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24006.292202 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46551.597527 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30095.390338 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2040,65 +2246,66 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 13482596 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10019474 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 22090 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 22090 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3397427 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 3948207 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 669175 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 549365 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 394300 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 332875 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 429984 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1203009 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1101184 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11574298 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14922836 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 373561 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 511408 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 27382103 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 370370936 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 560535931 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1349320 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1724480 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 933980667 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 8332859 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 23404111 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.344949 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.475352 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 11132088 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9059631 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 23142 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 23142 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3230902 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 957658 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1110389 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 467130 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 407372 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 365584 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 452132 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1208854 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1057926 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9875504 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14402767 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 299311 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 504421 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 25082003 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 316009528 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 537745480 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1072416 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1728704 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 856556128 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4579678 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 18388489 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.234421 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.423637 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 15330876 65.51% 65.51% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 8073235 34.49% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 14077834 76.56% 76.56% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 4310655 23.44% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 23404111 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 11646725084 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 18388489 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 10772824519 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 158989494 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 181931492 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8682146940 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7414134377 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7623277083 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7417250282 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 205120292 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 165377004 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 296049290 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 288475000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40487 # Transaction distribution -system.iobus.trans_dist::ReadResp 40487 # Transaction distribution -system.iobus.trans_dist::WriteReq 137083 # Transaction distribution -system.iobus.trans_dist::WriteResp 30163 # Transaction distribution +system.iobus.trans_dist::ReadReq 40416 # Transaction distribution +system.iobus.trans_dist::ReadResp 40416 # Transaction distribution +system.iobus.trans_dist::WriteReq 136984 # Transaction distribution +system.iobus.trans_dist::WriteResp 30064 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106920 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48390 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48038 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2108,18 +2315,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29704 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231580 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231580 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123076 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231644 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231644 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 355140 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354800 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48058 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2129,18 +2336,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17645 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156518 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7351088 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7351088 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156137 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7351344 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7351344 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7509692 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36789000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7509567 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36527000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2160,7 +2367,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 22103000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 22064000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2168,71 +2375,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1044839337 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1044902599 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93320000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 93015000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179372271 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 179432954 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115786 # number of replacements -system.iocache.tags.tagsinuse 11.223287 # Cycle average of tags in use +system.iocache.tags.replacements 115804 # number of replacements +system.iocache.tags.tagsinuse 11.285754 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115802 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115820 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9123835798000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.412555 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.810732 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463285 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.238171 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.701455 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9175904776000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.836841 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.448912 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239803 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.465557 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705360 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1042467 # Number of tag accesses -system.iocache.tags.data_accesses 1042467 # Number of data accesses +system.iocache.tags.tag_accesses 1042755 # Number of tag accesses +system.iocache.tags.data_accesses 1042755 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8870 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8907 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8902 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8939 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106920 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106920 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8870 # number of demand (read+write) misses -system.iocache.demand_misses::total 8910 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8902 # number of demand (read+write) misses +system.iocache.demand_misses::total 8942 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8870 # number of overall misses -system.iocache.overall_misses::total 8910 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5627000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1958941092 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1964568092 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8902 # number of overall misses +system.iocache.overall_misses::total 8942 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1942659591 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1948366591 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28897474974 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28897474974 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5984000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1958941092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1964925092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5984000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1958941092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1964925092 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28987663054 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28987663054 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1942659591 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1948723591 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1942659591 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1948723591 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8870 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8907 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8902 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8939 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106920 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106920 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8870 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8910 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8902 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8942 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8870 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8910 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8902 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8942 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2246,55 +2453,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 152081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 220850.179481 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 220564.510161 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 218227.318692 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 217962.478018 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270271.932043 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270271.932043 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 149600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 220850.179481 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 220530.313356 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 149600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 220850.179481 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 220530.313356 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 225288 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271115.441957 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 271115.441957 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 218227.318692 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 217929.276560 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 218227.318692 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 217929.276560 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 228501 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27401 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27689 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.221890 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.252411 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106886 # number of writebacks -system.iocache.writebacks::total 106886 # number of writebacks +system.iocache.writebacks::writebacks 106887 # number of writebacks +system.iocache.writebacks::total 106887 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8870 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8907 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8902 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8939 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106920 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106920 # 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number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1483600613 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1479616613 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1483600613 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2308,567 +2515,560 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 100081.081081 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168835.976550 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 168550.366229 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166211.706695 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 165946.930641 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218267.054770 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218267.054770 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 97600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 168835.976550 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 168516.174186 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 97600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 168835.976550 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 168516.174186 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219111.821362 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219111.821362 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 166211.706695 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 165913.734399 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 166211.706695 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 165913.734399 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1310456 # number of replacements -system.l2c.tags.tagsinuse 64677.337118 # Cycle average of tags in use -system.l2c.tags.total_refs 7257968 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1373726 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 5.283418 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 5621833500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 9998.305247 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 56.991260 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 77.146603 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 791.679733 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4513.780403 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 23818.675732 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 150.211809 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 222.184258 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 784.998757 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 7219.989726 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17043.373589 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.152562 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000870 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.001177 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.012080 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.068875 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.363444 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002292 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003390 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.011978 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.110168 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.260061 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.986898 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 38915 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 205 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 24150 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 487 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 8729 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 29647 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 188 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 550 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5282 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 18136 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.593796 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003128 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.368500 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 74054042 # Number of tag accesses -system.l2c.tags.data_accesses 74054042 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5514 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4407 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 131001 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 549137 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1653135 # 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number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 7299 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 8593 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 15892 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 45918 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 59655 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 105573 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5514 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4407 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 131001 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 595055 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 1653135 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 7096 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6374 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 146834 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 667608 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 1853450 # number of demand (read+write) hits -system.l2c.demand_hits::total 5070474 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5514 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4407 # number of overall hits -system.l2c.overall_hits::cpu0.inst 131001 # number of overall hits -system.l2c.overall_hits::cpu0.data 595055 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 1653135 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 7096 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6374 # number of overall hits -system.l2c.overall_hits::cpu1.inst 146834 # number of overall hits -system.l2c.overall_hits::cpu1.data 667608 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 1853450 # 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number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 125698 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 698997 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1304 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1531 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 9213 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 137325 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 328949 # number of demand (read+write) misses -system.l2c.demand_misses::total 1313556 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 569 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 656 # number of overall misses -system.l2c.overall_misses::cpu0.inst 9314 # number of overall misses -system.l2c.overall_misses::cpu0.data 125698 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 698997 # 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Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1415378 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.902022 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 9445810500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 19768.926665 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 228.224478 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 327.605712 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4403.400979 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 13076.363837 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14280.609802 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 81.212634 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 119.963342 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2392.943065 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3574.441825 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 5977.605096 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.301650 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003482 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.004999 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.067191 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.199529 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.217905 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001239 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.001830 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.089341 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.154495 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.411296 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.229677 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.776063 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.521612 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.689229 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.584496 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.627511 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.605641 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.632847 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.638128 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.635412 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.589079 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.524669 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.562469 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.310833 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.349003 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102691 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.265836 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.443410 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.186815 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.208139 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.089341 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.206143 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.411296 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.250858 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.310833 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.349003 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102691 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.265836 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.443410 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.186815 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.208139 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.089341 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.206143 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.411296 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.250858 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70801.479758 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70176.265391 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 95099.746219 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 22466.608046 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20243.971628 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 21892.569988 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10081.122986 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10172.643319 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10127.734904 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10094.514924 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10170.084593 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10131.367291 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66785.676932 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63285.951301 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 65436.965728 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69412.984539 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67729.415418 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 90866.823975 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69412.984539 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67729.415418 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 90866.823975 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2883,58 +3083,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 1327465 # Transaction distribution -system.membus.trans_dist::ReadResp 1327465 # Transaction distribution -system.membus.trans_dist::WriteReq 37863 # Transaction distribution -system.membus.trans_dist::WriteResp 37863 # Transaction distribution -system.membus.trans_dist::Writeback 1017207 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 119813 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 119813 # Transaction distribution -system.membus.trans_dist::UpgradeReq 367379 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 281461 # Transaction distribution -system.membus.trans_dist::UpgradeResp 85028 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 87184 # Transaction distribution -system.membus.trans_dist::ReadExResp 72708 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123480 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 841910 # Transaction distribution +system.membus.trans_dist::ReadResp 841910 # Transaction distribution +system.membus.trans_dist::WriteReq 38471 # Transaction distribution +system.membus.trans_dist::WriteResp 38471 # Transaction distribution +system.membus.trans_dist::Writeback 1161772 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 665270 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 665270 # Transaction distribution +system.membus.trans_dist::UpgradeReq 386597 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 321242 # Transaction distribution +system.membus.trans_dist::UpgradeResp 114625 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 138806 # Transaction distribution +system.membus.trans_dist::ReadExResp 121371 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123076 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 22714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4395675 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4541961 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336541 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 336541 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4878502 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156518 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25442 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4847759 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4996369 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 336372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5332741 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156137 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 45428 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143082804 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 143284954 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14125504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14125504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 157410458 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 581037 # Total snoops (count) -system.membus.snoop_fanout::samples 3119395 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50884 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159245812 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 159453037 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14112640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14112640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 173565677 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 613627 # Total snoops (count) +system.membus.snoop_fanout::samples 3433927 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3119395 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3433927 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3119395 # Request fanout histogram -system.membus.reqLayer0.occupancy 101251489 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3433927 # Request fanout histogram +system.membus.reqLayer0.occupancy 100976496 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 55500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 19693498 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22065500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 11963097483 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 18062213474 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 12443113804 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 9212060141 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187409729 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 187637046 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2978,45 +3178,45 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 7096727 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7089473 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 37863 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 37863 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2477309 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 127465 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 20542 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 430421 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 297353 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 727774 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 228196 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 228196 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8832957 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8435767 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17268724 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 294458407 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 274483891 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 568942298 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1532220 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 10576474 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.010952 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.104077 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 4185645 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4178412 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38471 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38471 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2302237 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 921111 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 814190 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 436280 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 333774 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 770054 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 100 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 280654 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 280654 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7279651 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5709072 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 12988723 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 243910125 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 179631296 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 423541421 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1593139 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8378399 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.013829 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.116780 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 10460641 98.90% 98.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115833 1.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 8262536 98.62% 98.62% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115863 1.38% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 10576474 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 15316484616 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8378399 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 16938572035 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 7440499 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 7678500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 16737915607 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 11018810399 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 16438547163 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 9692180196 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |