diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:50:15 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:50:15 -0500 |
| commit | 29cd50e14e0709c28200bcbdbc08c1093ba300d7 (patch) | |
| tree | ce3db836e947d154cbd0e4d7e1959f7617a7cc0c /tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual | |
| parent | 7a0bf814b6eb2db57f37977a0cca6c442f957d68 (diff) | |
| download | gem5-29cd50e14e0709c28200bcbdbc08c1093ba300d7.tar.xz | |
arm, tests: Add 64-bit ARM regression tests
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual')
4 files changed, 4530 insertions, 0 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini new file mode 100644 index 000000000..bc3129ffa --- /dev/null +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini @@ -0,0 +1,1569 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=true +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxArmSystem +children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain +atags_addr=134217728 +boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64 +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 +boot_release_addr=65528 +cache_line_size=64 +clk_domain=system.clk_domain +dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb +early_kernel_symbols=false +enable_context_switch_stats_dump=false +eventq_index=0 +flags_addr=469827632 +gic_cpu_addr=738205696 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false +init_param=0 +kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 +kernel_addr_check=true +load_addr_mask=268435455 +load_offset=2147483648 +machine_type=VExpress_EMM64 +mem_mode=timing +mem_ranges=2147483648:2415919103 +memories=system.physmem system.realview.nvmem system.realview.vram +multi_proc=true +num_work_ids=16 +panic_on_oops=true +panic_on_panic=true +phys_addr_range_64=40 +readfile=/work/gem5.latest/tests/halt.sh +reset_addr_64=0 +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.bridge] +type=Bridge +clk_domain=system.clk_domain +delay=50000 +eventq_index=0 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +req_size=16 +resp_size=16 +master=system.iobus.slave[0] +slave=system.membus.master[0] + +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +eventq_index=0 +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +eventq_index=0 +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +eventq_index=0 +image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img +read_only=true + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu0] +type=TimingSimpleCPU +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu +dtb=system.cpu0.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +isa=system.cpu0.isa +istage2_mmu=system.cpu0.istage2_mmu +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu0.tracer +workload= +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=6 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu0.dcache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=16 +cpu_side=system.cpu0.dcache_port +mem_side=system.cpu0.toL2Bus.slave[1] + +[system.cpu0.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu0.toL2Bus.slave[5] + +[system.cpu0.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu0.toL2Bus.slave[3] + +[system.cpu0.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=1 +is_top_level=true +max_miss_count=0 +mshrs=2 +prefetch_on_access=false +prefetcher=Null +response_latency=1 +sequential_access=false +size=32768 +system=system +tags=system.cpu0.icache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.cpu0.toL2Bus.slave[0] + +[system.cpu0.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=1 +sequential_access=false +size=32768 + +[system.cpu0.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu0.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu0.toL2Bus.slave[4] + +[system.cpu0.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu0.toL2Bus.slave[2] + +[system.cpu0.l2cache] +type=BaseCache +children=prefetcher tags +addr_ranges=0:18446744073709551615 +assoc=16 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=12 +is_top_level=false +max_miss_count=0 +mshrs=16 +prefetch_on_access=true +prefetcher=system.cpu0.l2cache.prefetcher +response_latency=12 +sequential_access=false +size=1048576 +system=system +tags=system.cpu0.l2cache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.toL2Bus.master[0] +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.l2cache.prefetcher] +type=StridePrefetcher +clk_domain=system.cpu_clk_domain +cross_pages=false +data_accesses_only=false +degree=8 +eventq_index=0 +inst_tagged=true +latency=1 +on_miss_only=false +on_prefetch=true +on_read_only=false +serial_squash=false +size=100 +sys=system +use_master_id=true + +[system.cpu0.l2cache.tags] +type=RandomRepl +assoc=16 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=12 +sequential_access=false +size=1048576 + +[system.cpu0.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu0.l2cache.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu0.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu1] +type=TimingSimpleCPU +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu +dtb=system.cpu1.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu1.interrupts +isa=system.cpu1.isa +istage2_mmu=system.cpu1.istage2_mmu +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu1.tracer +workload= +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=6 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu1.dcache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=16 +cpu_side=system.cpu1.dcache_port +mem_side=system.cpu1.toL2Bus.slave[1] + +[system.cpu1.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu1.toL2Bus.slave[5] + +[system.cpu1.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu1.dtb.walker + +[system.cpu1.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu1.toL2Bus.slave[3] + +[system.cpu1.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=1 +is_top_level=true +max_miss_count=0 +mshrs=2 +prefetch_on_access=false +prefetcher=Null +response_latency=1 +sequential_access=false +size=32768 +system=system +tags=system.cpu1.icache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.cpu1.toL2Bus.slave[0] + +[system.cpu1.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=1 +sequential_access=false +size=32768 + +[system.cpu1.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu1.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu1.toL2Bus.slave[4] + +[system.cpu1.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu1.itb.walker + +[system.cpu1.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu1.toL2Bus.slave[2] + +[system.cpu1.l2cache] +type=BaseCache +children=prefetcher tags +addr_ranges=0:18446744073709551615 +assoc=16 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=12 +is_top_level=false +max_miss_count=0 +mshrs=16 +prefetch_on_access=true +prefetcher=system.cpu1.l2cache.prefetcher +response_latency=12 +sequential_access=false +size=1048576 +system=system +tags=system.cpu1.l2cache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.toL2Bus.master[0] +mem_side=system.toL2Bus.slave[1] + +[system.cpu1.l2cache.prefetcher] +type=StridePrefetcher +clk_domain=system.cpu_clk_domain +cross_pages=false +data_accesses_only=false +degree=8 +eventq_index=0 +inst_tagged=true +latency=1 +on_miss_only=false +on_prefetch=true +on_read_only=false +serial_squash=false +size=100 +sys=system +use_master_id=true + +[system.cpu1.l2cache.tags] +type=RandomRepl +assoc=16 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=12 +sequential_access=false +size=1048576 + +[system.cpu1.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu1.l2cache.cpu_side +slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu1.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.intrctrl] +type=IntrControl +eventq_index=0 +sys=system + +[system.iobus] +type=NoncoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=true +width=8 +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma + +[system.iocache] +type=BaseCache +children=tags +addr_ranges=2147483648:2415919103 +assoc=8 +clk_domain=system.clk_domain +eventq_index=0 +forward_snoops=false +hit_latency=50 +is_top_level=true +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=50 +sequential_access=false +size=1024 +system=system +tags=system.iocache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] + +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=50 +sequential_access=false +size=1024 + +[system.l2c] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=4194304 +system=system +tags=system.l2c.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=4194304 + +[system.membus] +type=CoherentXBar +children=badaddr_responder +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +default=system.membus.badaddr_responder.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=0 +pio_latency=100000 +pio_size=8 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaChCo +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=2147483648:2415919103 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[5] + +[system.realview] +type=RealView +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +eventq_index=0 +intrctrl=system.intrctrl +pci_cfg_base=805306368 +pci_cfg_gen_offsets=true +pci_io_base=788529152 +system=system + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470024192 +pio_latency=100000 +system=system +pio=system.iobus.master[18] + +[system.realview.cf_ctrl] +type=IdeController +BAR0=471465984 +BAR0LegacyIO=true +BAR0Size=256 +BAR1=471466240 +BAR1LegacyIO=true +BAR1Size=4096 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=2 +disks= +eventq_index=0 +io_shift=2 +pci_bus=2 +pci_dev=0 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[9] +dma=system.iobus.slave[2] +pio=system.iobus.master[8] + +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=46 +pio_addr=471793664 +pio_latency=10000 +pixel_clock=41667 +system=system +vnc=system.vncserver +dma=system.iobus.slave[1] +pio=system.iobus.master[4] + +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=470286336 +pio_latency=100000 +system=system +pio=system.iobus.master[22] + +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +eventq_index=0 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 +system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] +pio=system.iobus.master[25] + +[system.realview.generic_timer] +type=GenericTimer +eventq_index=0 +gic=system.realview.gic +int_num=29 +system=system + +[system.realview.gic] +type=Pl390 +clk_domain=system.clk_domain +cpu_addr=738205696 +cpu_pio_delay=10000 +dist_addr=738201600 +dist_pio_delay=10000 +eventq_index=0 +int_latency=10000 +it_lines=128 +msix_addr=0 +platform=system.realview +system=system +pio=system.membus.master[2] + +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 +system=system +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] + +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 +eventq_index=0 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] + +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=44 +is_mouse=false +pio_addr=470155264 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[6] + +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=45 +is_mouse=true +pio_addr=470220800 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[7] + +[system.realview.l2x0_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=739246080 +pio_latency=100000 +pio_size=4095 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] + +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=738721792 +pio_latency=100000 +system=system +pio=system.membus.master[3] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470089728 +pio_latency=100000 +system=system +pio=system.iobus.master[21] + +[system.realview.nvmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:67108863 +port=system.membus.master[1] + +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + +[system.realview.realview_io] +type=RealViewCtrl +clk_domain=system.clk_domain +eventq_index=0 +idreg=35979264 +pio_addr=469827584 +pio_latency=100000 +proc_id0=335544320 +proc_id1=335544320 +system=system +pio=system.iobus.master[1] + +[system.realview.rtc] +type=PL031 +amba_id=3412017 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=36 +pio_addr=471269376 +pio_latency=100000 +system=system +time=Thu Jan 1 00:00:00 2009 +pio=system.iobus.master[10] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=true +pio_addr=469893120 +pio_latency=100000 +system=system +pio=system.iobus.master[16] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=34 +int_num1=34 +pio_addr=470876160 +pio_latency=100000 +system=system +pio=system.iobus.master[2] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=35 +int_num1=35 +pio_addr=470941696 +pio_latency=100000 +system=system +pio=system.iobus.master[3] + +[system.realview.uart] +type=Pl011 +clk_domain=system.clk_domain +end_on_eot=false +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=37 +pio_addr=470351872 +pio_latency=100000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.master[0] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470417408 +pio_latency=100000 +system=system +pio=system.iobus.master[13] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470482944 +pio_latency=100000 +system=system +pio=system.iobus.master[14] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470548480 +pio_latency=100000 +system=system +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470745088 +pio_latency=100000 +system=system +pio=system.iobus.master[17] + +[system.terminal] +type=Terminal +eventq_index=0 +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=8 +master=system.l2c.cpu_side +slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side + +[system.vncserver] +type=VncServer +eventq_index=0 +frame_capture=false +number=0 +port=5900 + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simerr new file mode 100644 index 000000000..744db2c76 --- /dev/null +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simerr @@ -0,0 +1,11 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match. +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0 +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: Tried to read RealView I/O at offset 0x8 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout new file mode 100644 index 000000000..1e0022357 --- /dev/null +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout @@ -0,0 +1,17 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Oct 29 2014 15:46:15 +gem5 started Oct 29 2014 16:01:57 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual +Selected 64-bit ARM architecture, updating default disk image... +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 + 0: system.cpu0.isa: ISA system set to: 0x5b5eb00 0x5b5eb00 + 0: system.cpu1.isa: ISA system set to: 0x5b5eb00 0x5b5eb00 +info: Using bootloader at address 0x10 +info: Using kernel entry physical address at 0x80080000 +info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 47438274662000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt new file mode 100644 index 000000000..092eed50c --- /dev/null +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -0,0 +1,2933 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 47.438275 # Number of seconds simulated +sim_ticks 47438274662000 # Number of ticks simulated +final_tick 47438274662000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 649244 # Simulator instruction rate (inst/s) +host_op_rate 763603 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34889420828 # Simulator tick rate (ticks/s) +host_mem_usage 811016 # Number of bytes of host memory used +host_seconds 1359.68 # Real time elapsed on the host +sim_insts 882760938 # Number of instructions simulated +sim_ops 1038251286 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::realview.ide 477376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 221952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 405952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 701748 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 13046680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 27196672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 278976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 430208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 568824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 13928160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 27822464 # Number of bytes read from this memory +system.physmem.bytes_read::total 85079012 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 701748 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 568824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1270572 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 44376640 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 6830592 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 54965772 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 45117316 # Number of bytes written to this memory +system.physmem.bytes_written::total 151290320 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 7459 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 3468 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 6343 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 51372 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 203876 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 424948 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 4359 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 6722 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 8976 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 217642 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 434726 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1369891 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 693385 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 106728 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 861117 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 704959 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2366189 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 10063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 4679 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 8557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 14793 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 275024 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 573307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 5881 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 9069 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 11991 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 293606 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 586498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1793468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 14793 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 11991 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 26784 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 935461 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 143989 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 1158680 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 951074 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3189204 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 935461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 154052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 4679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 8557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 14793 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1433704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 573307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 5881 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 9069 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 11991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1244680 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 586498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4982671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1369891 # Number of read requests accepted +system.physmem.writeReqs 2366189 # Number of write requests accepted +system.physmem.readBursts 1369891 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2366189 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 87382976 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 290048 # Total number of bytes read from write queue +system.physmem.bytesWritten 145690880 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 85079012 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 151290320 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 4532 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 89741 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 95337 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 80179 # Per bank write bursts +system.physmem.perBankRdBursts::1 81898 # Per bank write bursts +system.physmem.perBankRdBursts::2 76695 # Per bank write bursts +system.physmem.perBankRdBursts::3 88857 # Per bank write bursts +system.physmem.perBankRdBursts::4 82614 # Per bank write bursts +system.physmem.perBankRdBursts::5 89869 # Per bank write bursts +system.physmem.perBankRdBursts::6 79228 # Per bank write bursts +system.physmem.perBankRdBursts::7 87605 # Per bank write bursts +system.physmem.perBankRdBursts::8 77754 # Per bank write bursts +system.physmem.perBankRdBursts::9 127975 # Per bank write bursts +system.physmem.perBankRdBursts::10 81231 # Per bank write bursts +system.physmem.perBankRdBursts::11 85621 # Per bank write bursts +system.physmem.perBankRdBursts::12 74411 # Per bank write bursts +system.physmem.perBankRdBursts::13 85967 # Per bank write bursts +system.physmem.perBankRdBursts::14 83368 # Per bank write bursts +system.physmem.perBankRdBursts::15 82087 # Per bank write bursts +system.physmem.perBankWrBursts::0 134695 # Per bank write bursts +system.physmem.perBankWrBursts::1 125793 # Per bank write bursts +system.physmem.perBankWrBursts::2 142260 # Per bank write bursts +system.physmem.perBankWrBursts::3 126417 # Per bank write bursts +system.physmem.perBankWrBursts::4 155026 # Per bank write bursts +system.physmem.perBankWrBursts::5 152020 # Per bank write bursts +system.physmem.perBankWrBursts::6 183109 # Per bank write bursts +system.physmem.perBankWrBursts::7 140837 # Per bank write bursts +system.physmem.perBankWrBursts::8 128222 # Per bank write bursts +system.physmem.perBankWrBursts::9 141420 # Per bank write bursts +system.physmem.perBankWrBursts::10 135722 # Per bank write bursts +system.physmem.perBankWrBursts::11 146309 # Per bank write bursts +system.physmem.perBankWrBursts::12 139215 # Per bank write bursts +system.physmem.perBankWrBursts::13 127398 # Per bank write bursts +system.physmem.perBankWrBursts::14 153454 # Per bank write bursts +system.physmem.perBankWrBursts::15 144523 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 10 # Number of times write queue was full causing retry +system.physmem.totGap 47438271681000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 312 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 831449 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 280.321107 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 152.348246 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 337.173071 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 412387 49.60% 49.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 160013 19.25% 68.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 57469 6.91% 75.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 29190 3.51% 79.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24961 3.00% 82.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 16130 1.94% 84.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 12424 1.49% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 12438 1.50% 87.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 106437 12.80% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 831449 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 117879 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 11.582360 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 193.016425 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 117876 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::20480-22527 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-26623 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-59391 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 117879 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 117879 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.311497 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.988433 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 4.874271 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 75351 63.92% 63.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 36700 31.13% 95.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 3007 2.55% 97.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 902 0.77% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 786 0.67% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 199 0.17% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 149 0.13% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 77 0.07% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 81 0.07% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 16 0.01% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 14 0.01% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 14 0.01% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 396 0.34% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 29 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 39 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 22 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 47 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 4 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 10 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 4 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 6 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 15 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 117879 # Writes before turning the bus around for reads +system.physmem.totQLat 39355914512 # Total ticks spent queuing +system.physmem.totMemAccLat 64956395762 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6826795000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28824.59 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 47574.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.84 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.07 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.79 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.19 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.35 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.79 # Average write queue length when enqueuing +system.physmem.readRowHits 1064531 # Number of row buffer hits during reads +system.physmem.writeRowHits 1745793 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.97 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 76.69 # Row buffer hit rate for writes +system.physmem.avgGap 12697338.30 # Average gap between requests +system.physmem.pageHitRate 77.17 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 45390521349500 # Time in different power states +system.physmem.memoryStateTime::REF 1584068200000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 463683887500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 3148966800 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3136780080 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1718186250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1711536750 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 5202085200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 5447566800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 7517817360 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 7233384240 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3098437399200 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3098437399200 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1260445205745 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1262996298315 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 27357310364250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 27355072563750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 31733780024805 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 31734035529135 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.948883 # Core power per rank (mW) +system.physmem.averagePower::1 668.954269 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 1262651 # Transaction distribution +system.membus.trans_dist::ReadResp 1262651 # Transaction distribution +system.membus.trans_dist::WriteReq 38160 # Transaction distribution +system.membus.trans_dist::WriteResp 38160 # Transaction distribution +system.membus.trans_dist::Writeback 693385 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 1670201 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 1670201 # Transaction distribution +system.membus.trans_dist::UpgradeReq 307572 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 298715 # Transaction distribution +system.membus.trans_dist::UpgradeResp 95343 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 162530 # Transaction distribution +system.membus.trans_dist::ReadExResp 146943 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123084 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24300 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 7267614 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 7415090 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229896 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 229896 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7644986 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156191 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 229061364 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 229266359 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7307968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7307968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 236574327 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 528061 # Total snoops (count) +system.membus.snoop_fanout::samples 4313648 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 4313648 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 4313648 # Request fanout histogram +system.membus.reqLayer0.occupancy 100869991 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 21144997 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 23127462719 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 14206266380 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 187834022 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.l2c.tags.replacements 1088949 # number of replacements +system.l2c.tags.tagsinuse 64239.358232 # Cycle average of tags in use +system.l2c.tags.total_refs 6591556 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1149786 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 5.732855 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 9309.879147 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 38.225449 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 41.200627 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 627.976202 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3676.898634 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16318.952466 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 311.035795 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 436.956601 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 693.970644 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 9626.822610 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 23157.440058 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.142057 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000583 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000629 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.009582 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.056105 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.249007 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004746 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.006667 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.010589 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.146894 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.353354 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.980215 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 32295 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 314 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 28228 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 21 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 137 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 836 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 1678 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 29623 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 31 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 268 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1122 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4068 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 22816 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.492783 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.004791 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.430725 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 79894517 # Number of tag accesses +system.l2c.tags.data_accesses 79894517 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 5969 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3906 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 130836 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 569496 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1489116 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 6350 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 4630 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 144360 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 647503 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1630669 # number of ReadReq hits +system.l2c.ReadReq_hits::total 4632835 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1982686 # number of Writeback hits +system.l2c.Writeback_hits::total 1982686 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 22177 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 28734 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 50911 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 6966 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 8106 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 15072 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48437 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 51237 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 99674 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 5969 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3906 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 130836 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 617933 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 1489116 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6350 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4630 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 144360 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 698740 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 1630669 # number of demand (read+write) hits +system.l2c.demand_hits::total 4732509 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 5969 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3906 # number of overall hits +system.l2c.overall_hits::cpu0.inst 130836 # number of overall hits +system.l2c.overall_hits::cpu0.data 617933 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 1489116 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6350 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4630 # number of overall hits +system.l2c.overall_hits::cpu1.inst 144360 # number of overall hits +system.l2c.overall_hits::cpu1.data 698740 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 1630669 # number of overall hits +system.l2c.overall_hits::total 4732509 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 3468 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 6343 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 8294 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 128231 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 425212 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 4359 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 6722 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 8893 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 146336 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 434855 # number of ReadReq misses +system.l2c.ReadReq_misses::total 1172713 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 33912 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 36287 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 70199 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 10020 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 11790 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 21810 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 77130 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 73144 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 150274 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 3468 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 6343 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 8294 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 205361 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 425212 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 4359 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 6722 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 8893 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 219480 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 434855 # 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average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 13 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1670 # Number of DMA write transactions. +system.toL2Bus.trans_dist::ReadReq 6645186 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 6637629 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38160 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38160 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1982686 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1670210 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1563473 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 355152 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 313787 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 668939 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 102 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297718 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297718 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9432330 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9652916 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 19085246 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 302653655 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 312342176 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 614995831 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1425200 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 11183456 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.010347 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.101194 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 11067738 98.97% 98.97% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115718 1.03% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 11183456 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 19814172733 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 6396000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 15605521398 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 16621378743 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 40465 # Transaction distribution +system.iobus.trans_dist::ReadResp 40465 # Transaction distribution +system.iobus.trans_dist::WriteReq 136732 # Transaction distribution +system.iobus.trans_dist::WriteResp 136786 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 54 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48150 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123084 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231338 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231338 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354502 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48170 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156191 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7497645 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36603000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 981958721 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 93029000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 179341978 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.inst_hits 0 # ITB inst hits +system.cpu0.dtb.inst_misses 0 # ITB inst misses +system.cpu0.dtb.read_hits 81279666 # DTB read hits +system.cpu0.dtb.read_misses 78948 # DTB read misses +system.cpu0.dtb.write_hits 73742535 # DTB write hits +system.cpu0.dtb.write_misses 27290 # DTB write misses +system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 41415 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1036 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 31886 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 3595 # Number of TLB faults due to prefetch +system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dtb.perms_faults 8523 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 81358614 # DTB read accesses +system.cpu0.dtb.write_accesses 73769825 # DTB write accesses +system.cpu0.dtb.inst_accesses 0 # ITB inst accesses +system.cpu0.dtb.hits 155022201 # DTB hits +system.cpu0.dtb.misses 106238 # DTB misses +system.cpu0.dtb.accesses 155128439 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 432012599 # ITB inst hits +system.cpu0.itb.inst_misses 54786 # ITB inst misses +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses +system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 41415 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1036 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 22623 # Number of entries that have been flushed from TLB +system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.inst_accesses 432067385 # ITB inst accesses +system.cpu0.itb.hits 432012599 # DTB hits +system.cpu0.itb.misses 54786 # DTB misses +system.cpu0.itb.accesses 432067385 # DTB accesses +system.cpu0.numCycles 94876549324 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 431769250 # Number of instructions committed +system.cpu0.committedOps 507110651 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 465722099 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 423380 # Number of float alu accesses +system.cpu0.num_func_calls 25579239 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 65525116 # number of instructions that are conditional controls +system.cpu0.num_int_insts 465722099 # number of integer instructions +system.cpu0.num_fp_insts 423380 # number of float instructions +system.cpu0.num_int_register_reads 674979358 # number of times the integer registers were read +system.cpu0.num_int_register_writes 369311745 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 705560 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 308536 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 112703400 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 112387692 # number of times the CC registers were written +system.cpu0.num_mem_refs 155012297 # number of memory refs +system.cpu0.num_load_insts 81273219 # Number of load instructions +system.cpu0.num_store_insts 73739078 # Number of store instructions +system.cpu0.num_idle_cycles 93821929037.552032 # Number of idle cycles +system.cpu0.num_busy_cycles 1054620286.447978 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011116 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988884 # Percentage of idle cycles +system.cpu0.Branches 96363585 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 351187949 69.21% 69.21% # Class of executed instruction +system.cpu0.op_class::IntMult 1094457 0.22% 69.43% # Class of executed instruction +system.cpu0.op_class::IntDiv 58568 0.01% 69.44% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 43852 0.01% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::MemRead 81273219 16.02% 85.47% # Class of executed instruction +system.cpu0.op_class::MemWrite 73739078 14.53% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 507397124 # Class of executed instruction +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 5117 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 4835795 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.921057 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 427176292 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 4836307 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 88.326959 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 24248022750 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.921057 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999846 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999846 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 868861505 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 868861505 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 427176292 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 427176292 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 427176292 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 427176292 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 427176292 # number of overall hits +system.cpu0.icache.overall_hits::total 427176292 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 4836307 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 4836307 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 4836307 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 4836307 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 4836307 # number of overall misses +system.cpu0.icache.overall_misses::total 4836307 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 42021880066 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 42021880066 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 42021880066 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 42021880066 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 42021880066 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 42021880066 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 432012599 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 432012599 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 432012599 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 432012599 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 432012599 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 432012599 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011195 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011195 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011195 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011195 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011195 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011195 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8688.836351 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8688.836351 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8688.836351 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8688.836351 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8688.836351 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8688.836351 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4836307 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 4836307 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 4836307 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 4836307 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 4836307 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 4836307 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 34764760966 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 34764760966 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 34764760966 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 34764760966 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 34764760966 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 34764760966 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3405609750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 3405609750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011195 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011195 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011195 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011195 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011195 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011195 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7188.286634 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7188.286634 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7188.286634 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 7188.286634 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7188.286634 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 7188.286634 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 44883381 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 769766 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 41733922 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 7731 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 460 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 2371502 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 3699891 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.l2cache.tags.replacements 2933552 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16178.968525 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 10401290 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2949711 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 3.526206 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 20647851500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 3715.452521 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 41.338628 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 40.195819 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 822.456727 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3056.932991 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8502.591837 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.226773 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002523 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002453 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.050199 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.186580 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.518957 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.987486 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8877 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 49 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7233 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 49 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 502 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2719 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 3687 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1920 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 22 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 393 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2913 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2975 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 925 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.541809 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.002991 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.441467 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 228304892 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 228304892 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 221810 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 122090 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4672690 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 2607787 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 7624377 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 2894821 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 2894821 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 81724 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 81724 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 31053 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 31053 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 866415 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 866415 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 221810 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 122090 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 4672690 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3474202 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 8490792 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 221810 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 122090 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 4672690 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3474202 # number of overall hits +system.cpu0.l2cache.overall_hits::total 8490792 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12355 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10686 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 163617 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 944935 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 1131593 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 105877 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 105877 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154791 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 154791 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 220288 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 220288 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12355 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10686 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 163617 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1165223 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 1351881 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12355 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10686 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 163617 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1165223 # 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average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 252166.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 252166.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38075.734399 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38075.734399 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34902.553865 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 57572.061950 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 21046.237669 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27474.499568 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27109.838885 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34902.553865 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 57572.061950 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 21046.237669 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27474.499568 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 29835.210040 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 28862.065867 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.tags.replacements 5282593 # number of replacements +system.cpu0.dcache.tags.tagsinuse 478.557100 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 149517101 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5283105 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.300990 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 3644536500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 478.557100 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.934682 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.934682 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 411 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 315346998 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 315346998 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75666916 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75666916 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 69634196 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 69634196 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 181888 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 181888 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 858515 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 858515 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1792597 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1792597 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1751129 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1751129 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 145301112 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 145301112 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 145483000 # number of overall hits +system.cpu0.dcache.overall_hits::total 145483000 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2868190 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 2868190 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1290634 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1290634 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 609921 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 609921 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 145533 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 145533 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 185941 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 185941 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4158824 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4158824 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 4768745 # number of overall misses +system.cpu0.dcache.overall_misses::total 4768745 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41686378389 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 41686378389 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 22767469365 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 22767469365 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2114986821 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2114986821 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3970270831 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3970270831 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1983000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1983000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 64453847754 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 64453847754 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 64453847754 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 64453847754 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 78535106 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 78535106 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 70924830 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 70924830 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 791809 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 791809 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 858515 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 858515 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1938130 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1938130 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1937070 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1937070 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 149459936 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 149459936 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 150251745 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 150251745 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036521 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036521 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018197 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018197 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770288 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.770288 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075089 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.075089 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095991 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095991 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027826 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027826 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031738 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.031738 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14534.036584 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14534.036584 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17640.531216 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17640.531216 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14532.695822 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14532.695822 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21352.315148 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21352.315148 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15498.094595 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15498.094595 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13515.893124 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13515.893124 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 858515 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 2894821 # number of writebacks +system.cpu0.dcache.writebacks::total 2894821 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28163 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 28163 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21327 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21327 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41518 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41518 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 49490 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 49490 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 49490 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 49490 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2840027 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2840027 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1269307 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1269307 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 608681 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 608681 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 104015 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 104015 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 185850 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 185850 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4109334 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4109334 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4718015 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4718015 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 34673571058 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 34673571058 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 19854321886 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 19854321886 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13611528726 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13611528726 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 38259906745 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 38259906745 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1241876461 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1241876461 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3588911169 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3588911169 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1889000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1889000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 54527892944 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 54527892944 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 68139421670 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 68139421670 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2380477468 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2380477468 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2403593708 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2403593708 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4784071176 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4784071176 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036163 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036163 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017897 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017897 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.768722 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.768722 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053668 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.053668 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095944 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095944 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027495 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027495 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031401 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031401 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12208.887823 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12208.887823 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15641.859602 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15641.859602 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22362.335486 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22362.335486 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11939.397789 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11939.397789 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19310.794560 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19310.794560 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13269.277441 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13269.277441 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14442.391911 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14442.391911 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.toL2Bus.trans_dist::ReadReq 12330313 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9009509 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 16126 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 16126 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 2894821 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 3465295 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1670210 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 858515 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 371533 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 344881 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 439023 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1234519 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1094177 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 9758864 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 14862906 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 296442 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 542592 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 25460804 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 309696148 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 543504195 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1062208 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1873320 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 856135871 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 8448176 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 22253887 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.367543 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.482136 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 14074632 63.25% 63.25% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 8179255 36.75% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 22253887 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 10836211781 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 180026995 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer0.occupancy 7309068550 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 7654516797 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer2.occupancy 164187799 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer3.occupancy 308745047 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.inst_hits 0 # ITB inst hits +system.cpu1.dtb.inst_misses 0 # ITB inst misses +system.cpu1.dtb.read_hits 85169560 # DTB read hits +system.cpu1.dtb.read_misses 81568 # DTB read misses +system.cpu1.dtb.write_hits 77252621 # DTB write hits +system.cpu1.dtb.write_misses 28177 # DTB write misses +system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 41415 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1036 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 42405 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 4822 # Number of TLB faults due to prefetch +system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dtb.perms_faults 11145 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 85251128 # DTB read accesses +system.cpu1.dtb.write_accesses 77280798 # DTB write accesses +system.cpu1.dtb.inst_accesses 0 # ITB inst accesses +system.cpu1.dtb.hits 162422181 # DTB hits +system.cpu1.dtb.misses 109745 # DTB misses +system.cpu1.dtb.accesses 162531926 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 451299133 # ITB inst hits +system.cpu1.itb.inst_misses 60868 # ITB inst misses +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses +system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 41415 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1036 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 29689 # Number of entries that have been flushed from TLB +system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.inst_accesses 451360001 # ITB inst accesses +system.cpu1.itb.hits 451299133 # DTB hits +system.cpu1.itb.misses 60868 # DTB misses +system.cpu1.itb.accesses 451360001 # DTB accesses +system.cpu1.numCycles 94876549324 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 450991688 # Number of instructions committed +system.cpu1.committedOps 531140635 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 488008709 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 470535 # Number of float alu accesses +system.cpu1.num_func_calls 27052635 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 68722135 # number of instructions that are conditional controls +system.cpu1.num_int_insts 488008709 # number of integer instructions +system.cpu1.num_fp_insts 470535 # number of float instructions +system.cpu1.num_int_register_reads 711965253 # number of times the integer registers were read +system.cpu1.num_int_register_writes 387496587 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 748074 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 424948 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 118082190 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 117761356 # number of times the CC registers were written +system.cpu1.num_mem_refs 162414438 # number of memory refs +system.cpu1.num_load_insts 85168501 # Number of load instructions +system.cpu1.num_store_insts 77245937 # Number of store instructions +system.cpu1.num_idle_cycles 93789094629.720032 # Number of idle cycles +system.cpu1.num_busy_cycles 1087454694.279977 # Number of busy cycles +system.cpu1.not_idle_fraction 0.011462 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.988538 # Percentage of idle cycles +system.cpu1.Branches 100614893 # Number of branches fetched +system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 367777606 69.20% 69.20% # Class of executed instruction +system.cpu1.op_class::IntMult 1128259 0.21% 69.42% # Class of executed instruction +system.cpu1.op_class::IntDiv 59926 0.01% 69.43% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 67918 0.01% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::MemRead 85168501 16.03% 85.47% # Class of executed instruction +system.cpu1.op_class::MemWrite 77245937 14.53% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 531448189 # Class of executed instruction +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 13727 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 5018265 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.292950 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 446280351 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5018777 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 88.922132 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8374030789000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.292950 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969322 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969322 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 272 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 907617048 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 907617048 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 446280351 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 446280351 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 446280351 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 446280351 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 446280351 # number of overall hits +system.cpu1.icache.overall_hits::total 446280351 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5018782 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5018782 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5018782 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5018782 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5018782 # number of overall misses +system.cpu1.icache.overall_misses::total 5018782 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 43828213410 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 43828213410 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 43828213410 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 43828213410 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 43828213410 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 43828213410 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 451299133 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 451299133 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 451299133 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 451299133 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 451299133 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 451299133 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011121 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.011121 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011121 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.011121 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011121 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.011121 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8732.838647 # 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number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7884500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3785923263 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3793807763 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3621697529 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3621697529 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7884500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7407620792 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7415505292 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.053021 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.077445 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.030514 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.265289 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.129145 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.565556 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.565556 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.811678 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.811678 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.189407 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.189407 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.053021 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.077445 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.030514 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.247519 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.135922 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.053021 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.077445 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.030514 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.247519 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.377310 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 38969.985947 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 55683.057689 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21007.174994 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 25744.677294 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25571.323344 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29486.100365 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 29486.100365 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17259.392339 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17259.392339 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13963.073546 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13963.073546 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 229562.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 229562.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36178.155824 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36178.155824 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 38969.985947 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 55683.057689 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21007.174994 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27614.347108 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27233.457341 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 38969.985947 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 55683.057689 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21007.174994 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27614.347108 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29486.100365 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28674.608848 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.tags.replacements 5412769 # number of replacements +system.cpu1.dcache.tags.tagsinuse 455.628997 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 156797756 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5413278 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.965399 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8374220312000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.628997 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.889900 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.889900 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 330228848 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 330228848 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 79329783 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 79329783 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 73242746 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 73242746 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 190572 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 190572 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 704958 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 704958 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1728485 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1728485 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1710118 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1710118 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 152572529 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 152572529 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 152763101 # number of overall hits +system.cpu1.dcache.overall_hits::total 152763101 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3054941 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3054941 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1365411 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1365411 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 663261 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 663261 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 178994 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 178994 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 196091 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 196091 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4420352 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4420352 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5083613 # number of overall misses +system.cpu1.dcache.overall_misses::total 5083613 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 45633904603 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 45633904603 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 23251947701 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 23251947701 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2574333319 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2574333319 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4154245626 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4154245626 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2386500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2386500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 68885852304 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 68885852304 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 68885852304 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 68885852304 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 82384724 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 82384724 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 74608157 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 74608157 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 853833 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 853833 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 704958 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 704958 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1907479 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1907479 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1906209 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1906209 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 156992881 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 156992881 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 157846714 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 157846714 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037081 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.037081 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018301 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018301 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.776804 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.776804 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.093838 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.093838 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102870 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.102870 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028156 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.028156 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032206 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.032206 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14937.736802 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14937.736802 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17029.266427 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17029.266427 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14382.232471 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14382.232471 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21185.294715 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21185.294715 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15583.793396 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15583.793396 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13550.569704 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 13550.569704 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 704958 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.writebacks::writebacks 3078594 # number of writebacks +system.cpu1.dcache.writebacks::total 3078594 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 23839 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 23839 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 436 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 436 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 45139 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45139 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 24275 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 24275 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 24275 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 24275 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3031102 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3031102 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1364975 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1364975 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 663261 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 663261 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 133855 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 133855 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 196002 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 196002 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4396077 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4396077 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5059338 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5059338 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38375786357 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38375786357 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20437608309 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20437608309 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14184435008 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14184435008 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 31455228300 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 31455228300 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1522508206 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1522508206 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3750879374 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3750879374 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2276500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2276500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 58813394666 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 58813394666 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 72997829674 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 72997829674 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3974280487 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3974280487 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3786981721 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3786981721 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7761262208 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7761262208 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036792 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036792 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018295 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018295 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.776804 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.776804 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.070174 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.070174 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.102823 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.102823 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028002 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028002 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032052 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032052 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12660.671385 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12660.671385 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14972.881048 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14972.881048 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21385.902394 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21385.902394 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11374.309559 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11374.309559 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19136.944388 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19136.944388 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13378.608852 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13378.608852 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14428.336212 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14428.336212 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.toL2Bus.trans_dist::ReadReq 12531191 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9460246 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 22034 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 22034 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3078590 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 3649719 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1670210 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 704958 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 365743 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 350744 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 452026 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1320531 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1177447 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 10037784 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15516501 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332477 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 559655 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 26446417 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 321202488 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 568398888 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1205080 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1932672 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 892739128 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 8517318 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 22943145 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.359651 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.479898 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 14691626 64.03% 64.03% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 8251519 35.97% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 22943145 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 11163844442 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 175587993 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer0.occupancy 7529809391 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 8141370258 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer2.occupancy 182479297 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer3.occupancy 318532791 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 115665 # number of replacements +system.iocache.tags.tagsinuse 11.304646 # Cycle average of tags in use +system.iocache.tags.total_refs 3 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 115681 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 9130394779000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.406620 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.898026 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.462914 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.243627 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706540 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 1041810 # Number of tag accesses +system.iocache.tags.data_accesses 1041810 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 106728 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 106728 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8941 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8978 # number of ReadReq misses +system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses +system.iocache.WriteReq_misses::total 3 # number of WriteReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 54 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 54 # number of WriteInvalidateReq misses +system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8941 # number of demand (read+write) misses +system.iocache.demand_misses::total 8981 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ethernet 40 # number of overall misses +system.iocache.overall_misses::realview.ide 8941 # number of overall misses +system.iocache.overall_misses::total 8981 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1994628595 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 2000335595 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1994628595 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 2000692595 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1994628595 # number of overall miss cycles +system.iocache.overall_miss_latency::total 2000692595 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8941 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8978 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106782 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106782 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8941 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8981 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8941 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8981 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000506 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000506 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 223087.864333 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 222804.142905 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 223087.864333 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 222769.468322 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 223087.864333 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 222769.468322 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 55195 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.053734 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 106728 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8941 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8978 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8941 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8981 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8941 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8981 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1529539613 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1533322613 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6584739086 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6584739086 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1529539613 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1533523613 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1529539613 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1533523613 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 171070.306789 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 170786.657719 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 171070.306789 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 170751.988977 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 171070.306789 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 170751.988977 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- |