diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/quick/fs/10.linux-boot/ref/arm/linux | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux')
7 files changed, 6115 insertions, 6097 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt index beee6689a..7fca9a0be 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -1,58 +1,58 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.783855 # Number of seconds simulated -sim_ticks 2783855034000 # Number of ticks simulated -final_tick 2783855034000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2783854715000 # Number of ticks simulated +final_tick 2783854715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 850769 # Simulator instruction rate (inst/s) -host_op_rate 1035674 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16588804734 # Simulator tick rate (ticks/s) -host_mem_usage 576284 # Number of bytes of host memory used -host_seconds 167.82 # Real time elapsed on the host -sim_insts 142771937 # Number of instructions simulated -sim_ops 173801895 # Number of ops (including micro ops) simulated +host_inst_rate 492350 # Simulator instruction rate (inst/s) +host_op_rate 599357 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9600186649 # Simulator tick rate (ticks/s) +host_mem_usage 585092 # Number of bytes of host memory used +host_seconds 289.98 # Real time elapsed on the host +sim_insts 142771202 # Number of instructions simulated +sim_ops 173801044 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10324900 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10324772 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11533448 # Number of bytes read from this memory +system.physmem.bytes_read::total 11533320 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8840960 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8858484 # Number of bytes written to this memory +system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 161846 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 161844 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189183 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138140 # Number of write requests responded to by this memory +system.physmem.num_reads::total 189181 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142521 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3708850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3708804 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4142977 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4142932 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3175798 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3175775 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3182092 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3175798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3182070 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3175775 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3715145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3715099 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7325070 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.physmem.bw_total::total 7325002 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -65,9 +65,9 @@ system.realview.nvmem.bw_inst_read::cpu.inst 7 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -75,7 +75,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -105,7 +105,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 10028 # Table walker walks requested system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency @@ -126,9 +126,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31526014 # DTB read hits +system.cpu.dtb.read_hits 31525882 # DTB read hits system.cpu.dtb.read_misses 8580 # DTB read misses -system.cpu.dtb.write_hits 23124171 # DTB write hits +system.cpu.dtb.write_hits 23124079 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -139,13 +139,13 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534594 # DTB read accesses -system.cpu.dtb.write_accesses 23125619 # DTB write accesses +system.cpu.dtb.read_accesses 31534462 # DTB read accesses +system.cpu.dtb.write_accesses 23125527 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54650185 # DTB hits +system.cpu.dtb.hits 54649961 # DTB hits system.cpu.dtb.misses 10028 # DTB misses -system.cpu.dtb.accesses 54660213 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.accesses 54659989 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -175,7 +175,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 4762 # Table walker walks requested system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency @@ -194,7 +194,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 147038452 # ITB inst hits +system.cpu.itb.inst_hits 147037694 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -211,14 +211,14 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 147043214 # ITB inst accesses -system.cpu.itb.hits 147038452 # DTB hits +system.cpu.itb.inst_accesses 147042456 # ITB inst accesses +system.cpu.itb.hits 147037694 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 147043214 # DTB accesses +system.cpu.itb.accesses 147042456 # DTB accesses system.cpu.numPwrStateTransitions 6160 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 3080 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 874939595.358117 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17329944407.298908 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 874939633.669805 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17329944405.377167 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 3002 97.47% 97.47% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 72 2.34% 99.81% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state @@ -228,38 +228,38 @@ system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 3080 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 89041080297 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2694813953703 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5567713149 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 89040643297 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2694814071703 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 5567712511 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed -system.cpu.committedInsts 142771937 # Number of instructions committed -system.cpu.committedOps 173801895 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 153161571 # Number of integer alu accesses +system.cpu.committedInsts 142771202 # Number of instructions committed +system.cpu.committedOps 173801044 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 153160791 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses -system.cpu.num_func_calls 16873976 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18730294 # number of instructions that are conditional controls -system.cpu.num_int_insts 153161571 # number of integer instructions +system.cpu.num_func_calls 16873864 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18730220 # number of instructions that are conditional controls +system.cpu.num_int_insts 153160791 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions -system.cpu.num_int_register_reads 285044694 # number of times the integer registers were read -system.cpu.num_int_register_writes 107178579 # number of times the integer registers were written +system.cpu.num_int_register_reads 285043206 # number of times the integer registers were read +system.cpu.num_int_register_writes 107178068 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 530850452 # number of times the CC registers were read -system.cpu.num_cc_register_writes 62364047 # number of times the CC registers were written -system.cpu.num_mem_refs 55938751 # number of memory refs -system.cpu.num_load_insts 31855653 # Number of load instructions -system.cpu.num_store_insts 24083098 # Number of store instructions -system.cpu.num_idle_cycles 5389630889.858858 # Number of idle cycles -system.cpu.num_busy_cycles 178082259.141142 # Number of busy cycles +system.cpu.num_cc_register_reads 530847827 # number of times the CC registers were read +system.cpu.num_cc_register_writes 62363707 # number of times the CC registers were written +system.cpu.num_mem_refs 55938510 # number of memory refs +system.cpu.num_load_insts 31855508 # Number of load instructions +system.cpu.num_store_insts 24083002 # Number of store instructions +system.cpu.num_idle_cycles 5389631125.859330 # Number of idle cycles +system.cpu.num_busy_cycles 178081385.140670 # Number of busy cycles system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles system.cpu.idle_fraction 0.968015 # Percentage of idle cycles -system.cpu.Branches 36397005 # Number of branches fetched +system.cpu.Branches 36396820 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 121152199 68.36% 68.36% # Class of executed instruction -system.cpu.op_class::IntMult 116879 0.07% 68.43% # Class of executed instruction +system.cpu.op_class::IntAlu 121151571 68.36% 68.36% # Class of executed instruction +system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction @@ -287,17 +287,17 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::MemRead 31855653 17.98% 86.41% # Class of executed instruction -system.cpu.op_class::MemWrite 24083098 13.59% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 31855508 17.98% 86.41% # Class of executed instruction +system.cpu.op_class::MemWrite 24083002 13.59% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 177218735 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 819389 # number of replacements +system.cpu.op_class::total 177217860 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 819387 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53784005 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819901 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.598170 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 53783783 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819899 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.598059 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -307,51 +307,51 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219235605 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219235605 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 30128867 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30128867 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22339858 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22339858 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 219234707 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219234707 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 30128737 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30128737 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22339767 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22339767 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 395067 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 395067 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 457333 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 457333 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52468725 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52468725 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52863792 # number of overall hits -system.cpu.dcache.overall_hits::total 52863792 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 396279 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 396279 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 52468504 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52468504 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52863571 # number of overall hits +system.cpu.dcache.overall_hits::total 52863571 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 301662 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 301662 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 116119 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 116119 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 697942 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 697942 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 814061 # number of overall misses -system.cpu.dcache.overall_misses::total 814061 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30525146 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30525146 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641521 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641521 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 697939 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 697939 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 814058 # number of overall misses +system.cpu.dcache.overall_misses::total 814058 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 30525014 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30525014 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641429 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641429 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53166667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53166667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53677853 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53677853 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 53166443 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53166443 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53677629 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53677629 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses @@ -372,14 +372,14 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks -system.cpu.dcache.writebacks::total 682017 # number of writebacks -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1698989 # number of replacements +system.cpu.dcache.writebacks::writebacks 682138 # number of writebacks +system.cpu.dcache.writebacks::total 682138 # number of writebacks +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1698988 # number of replacements system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145342052 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1699501 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 85.520427 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 145341295 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1699500 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 85.520032 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 7831497000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy @@ -390,27 +390,27 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77 system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 148741066 # Number of tag accesses -system.cpu.icache.tags.data_accesses 148741066 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 145342052 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145342052 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145342052 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145342052 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145342052 # number of overall hits -system.cpu.icache.overall_hits::total 145342052 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1699507 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1699507 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1699507 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1699507 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1699507 # number of overall misses -system.cpu.icache.overall_misses::total 1699507 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 147041559 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 147041559 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 147041559 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 147041559 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 147041559 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 147041559 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 148740307 # Number of tag accesses +system.cpu.icache.tags.data_accesses 148740307 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 145341295 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145341295 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 145341295 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 145341295 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 145341295 # number of overall hits +system.cpu.icache.overall_hits::total 145341295 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1699506 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699506 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1699506 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699506 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1699506 # number of overall misses +system.cpu.icache.overall_misses::total 1699506 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 147040801 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 147040801 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 147040801 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 147040801 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 147040801 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 147040801 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses @@ -423,73 +423,70 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1698989 # number of writebacks -system.cpu.icache.writebacks::total 1698989 # number of writebacks -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 109914 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65155.312641 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4524828 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 175195 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 25.827381 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 48764.064013 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931994 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.693007 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.619283 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.744081 # Average percentage of cache occupancy +system.cpu.icache.writebacks::writebacks 1698988 # number of writebacks +system.cpu.icache.writebacks::total 1698988 # number of writebacks +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 109912 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65246.862245 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4827688 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 175338 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 27.533609 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 71491095000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.971735 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.023390 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9170.132693 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56073.734427 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139903 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.110163 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139925 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.855617 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995588 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65421 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9745 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55480 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40578737 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40578737 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 11218 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 682017 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 682017 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1666988 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1666988 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 151130 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 151130 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681192 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1681192 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505442 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 505442 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1681192 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 656572 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2348982 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1681192 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 656572 # number of overall hits -system.cpu.l2cache.overall_hits::total 2348982 # number of overall hits +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998245 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 40257223 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40257223 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5671 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2714 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 8385 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 682138 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 682138 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1666989 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1666989 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 2746 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 2746 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 152790 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 152790 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681191 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1681191 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505440 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 505440 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 5671 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 2714 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1681191 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 658230 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2347806 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 5671 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 2714 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681191 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 658230 # number of overall hits +system.cpu.l2cache.overall_hits::total 2347806 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 147777 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 147777 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 146117 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 146117 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18298 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15568 # number of ReadSharedReq misses @@ -497,116 +494,116 @@ system.cpu.l2cache.ReadSharedReq_misses::total 15568 system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 18298 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 163345 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 181652 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 161685 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 179992 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 163345 # number of overall misses -system.cpu.l2cache.overall_misses::total 181652 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 11227 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 682017 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 682017 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1666988 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1666988 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 161685 # number of overall misses +system.cpu.l2cache.overall_misses::total 179992 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5678 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2716 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 8394 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 682138 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 682138 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1666989 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1666989 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2755 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2755 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699490 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1699490 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521010 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 521010 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1699490 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819917 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2530634 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1699490 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819917 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2530634 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000802 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699489 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1699489 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521008 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5678 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 2716 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699489 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819915 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2527798 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5678 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 2716 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699489 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819915 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2527798 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001233 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000736 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001072 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003267 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.003267 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494391 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.494391 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.488838 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.488838 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010767 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029880 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029880 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001233 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000736 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010767 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.199221 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.071781 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.197197 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.071205 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001233 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000736 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010767 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.199221 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.071781 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.197197 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.071205 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks -system.cpu.l2cache.writebacks::total 101950 # number of writebacks -system.cpu.toL2Bus.snoop_filter.tot_requests 5059879 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540474 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39263 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks +system.cpu.l2cache.writebacks::total 101949 # number of writebacks +system.cpu.toL2Bus.snoop_filter.tot_requests 5059872 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540470 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2288317 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2288314 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 682017 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1698989 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 137372 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 682138 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1698988 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 137249 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2757 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699507 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 521010 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116047 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581961 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116044 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581953 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7753434 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96306529 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7753423 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96314145 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 313957213 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 182976 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 8840960 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5318714 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018479 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.134677 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 313964701 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 115326 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6541312 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5251057 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018717 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.135522 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5220428 98.15% 98.15% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 98286 1.85% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5152775 98.13% 98.13% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98282 1.87% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5318714 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.snoop_fanout::total 5251057 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -657,14 +654,14 @@ system.iobus.pkt_size_system.bridge.master::total 159061 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909892 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909890 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 227410175509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909892 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 227410176509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.909890 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -672,7 +669,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328176 # Number of tag accesses system.iocache.tags.data_accesses 328176 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses system.iocache.ReadReq_misses::total 240 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -705,65 +702,71 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.membus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 362809 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 151023 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 488 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 40087 # Transaction distribution system.membus.trans_dist::ReadResp 74202 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::WritebackDirty 138140 # Transaction distribution -system.membus.trans_dist::CleanEvict 8204 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution +system.membus.trans_dist::CleanEvict 8203 # Transaction distribution +system.membus.trans_dist::UpgradeReq 130 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution -system.membus.trans_dist::ReadExReq 145998 # Transaction distribution -system.membus.trans_dist::ReadExResp 145998 # Transaction distribution +system.membus.trans_dist::UpgradeResp 132 # Transaction distribution +system.membus.trans_dist::ReadExReq 145996 # Transaction distribution +system.membus.trans_dist::ReadExResp 145996 # Transaction distribution system.membus.trans_dist::ReadSharedReq 34115 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506584 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613944 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 497824 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 605184 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723302 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 714542 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092540 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255513 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092348 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255321 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20587033 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20586841 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 434823 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 430442 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012836 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.112565 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 434823 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 424917 98.72% 98.72% # Request fanout histogram +system.membus.snoop_fanout::1 5525 1.28% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 434823 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 430442 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -795,28 +798,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index fdfa30aa0..9c9dc0805 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,71 +4,67 @@ sim_seconds 2.802883 # Nu sim_ticks 2802883274000 # Number of ticks simulated final_tick 2802883274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 992891 # Simulator instruction rate (inst/s) -host_op_rate 1209822 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18955432442 # Simulator tick rate (ticks/s) -host_mem_usage 590980 # Number of bytes of host memory used -host_seconds 147.87 # Real time elapsed on the host +host_inst_rate 787866 # Simulator instruction rate (inst/s) +host_op_rate 960003 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15041277607 # Simulator tick rate (ticks/s) +host_mem_usage 600036 # Number of bytes of host memory used +host_seconds 186.35 # Real time elapsed on the host sim_insts 146815798 # Number of instructions simulated sim_ops 178892721 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1106276 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9415076 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 154452 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1081616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1163300 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9541412 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 165332 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1112336 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11759020 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1106276 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 154452 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1260728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8476800 # Number of bytes written to this memory +system.physmem.bytes_read::total 11983980 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1163300 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 165332 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1328632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8870080 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8494364 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8887644 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25739 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 147630 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2568 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16920 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26630 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 149604 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2738 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 17400 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 192882 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 132450 # Number of write requests responded to by this memory +system.physmem.num_reads::total 196397 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138595 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136841 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 142986 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 394692 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3359068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 55105 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 385894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 415037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3404142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 58986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 396854 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4195330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 394692 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 55105 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 449797 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3024314 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4275590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 415037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 58986 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 474023 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3164627 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3030581 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3024314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3170893 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3164627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 394692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3365320 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 55105 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 385908 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 415037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3410394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 58986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 396868 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7225911 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7446483 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -334,32 +330,32 @@ system.cpu0.dcache.tags.data_accesses 74108220 # Nu system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 19107088 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 19107088 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15689092 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15689092 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15689072 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15689072 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346042 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 346042 # number of SoftPFReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379604 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 379604 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363038 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 363038 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34796180 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34796180 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35142222 # number of overall hits -system.cpu0.dcache.overall_hits::total 35142222 # number of overall hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363048 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 363048 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 34796160 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34796160 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35142202 # number of overall hits +system.cpu0.dcache.overall_hits::total 35142202 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 373135 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 373135 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 295767 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 295767 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 295787 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 295787 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6741 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 6741 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18421 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18421 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 668902 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 668902 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 769224 # number of overall misses -system.cpu0.dcache.overall_misses::total 769224 # number of overall misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18411 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18411 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 668922 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 668922 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 769244 # number of overall misses +system.cpu0.dcache.overall_misses::total 769244 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 19480223 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 19480223 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 15984859 # number of WriteReq accesses(hits+misses) @@ -376,18 +372,18 @@ system.cpu0.dcache.overall_accesses::cpu0.data 35911446 system.cpu0.dcache.overall_accesses::total 35911446 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019155 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.019155 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018503 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018504 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018504 # miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224754 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224754 # miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017448 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017448 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048291 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048291 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048265 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048265 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018861 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.018861 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021420 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.021420 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021421 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.021421 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -454,181 +450,181 @@ system.cpu0.l2cache.prefetcher.pfInCache 0 # nu system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 249561 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16130.656320 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2729360 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 265678 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 10.273188 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 244755 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15690.306286 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1516961 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 260398 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.825548 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 16129.249413 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.326952 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.079954 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.984451 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000081 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.984537 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16104 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 349 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5522 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7440 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2639 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.982910 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 59687833 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 59687833 # Number of data accesses +system.cpu0.l2cache.tags.occ_blocks::writebacks 15688.001822 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.238695 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.065768 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.957520 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000137 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.957660 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15637 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 527 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 887 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7822 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5177 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1224 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.954407 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 60864487 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 60864487 # Number of data accesses system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10176 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4489 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 14665 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 510613 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 510613 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1264371 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1264371 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94352 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 94352 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1067857 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1067857 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352287 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 352287 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10176 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4489 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1067857 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 446639 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1529161 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10176 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4489 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1067857 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 446639 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1529161 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 214 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 138 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 352 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26245 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26245 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18421 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18421 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175170 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 175170 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 42026 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 42026 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127911 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 127911 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 214 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 138 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 42026 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 303081 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 345459 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 214 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 138 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 42026 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 303081 # number of overall misses -system.cpu0.l2cache.overall_misses::total 345459 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10390 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4627 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 15017 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 510613 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 510613 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 1264371 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 1264371 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26245 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 26245 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18421 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 18421 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10088 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4467 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 14555 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 510065 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 510065 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 1264919 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 1264919 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94269 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 94269 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1050188 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1050188 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 344415 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 344415 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10088 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4467 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1050188 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 438684 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1503427 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10088 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4467 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1050188 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 438684 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1503427 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 274 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 140 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 414 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26265 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26265 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18411 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18411 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175253 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 175253 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 59695 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 59695 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 135783 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 135783 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 274 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 140 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 59695 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 311036 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 371145 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 274 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 140 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 59695 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 311036 # number of overall misses +system.cpu0.l2cache.overall_misses::total 371145 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10362 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4607 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 14969 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 510065 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 510065 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 1264919 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 1264919 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26265 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26265 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18411 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 18411 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269522 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 269522 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1109883 # number of ReadCleanReq accesses(hits+misses) system.cpu0.l2cache.ReadCleanReq_accesses::total 1109883 # number of ReadCleanReq accesses(hits+misses) system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480198 # number of ReadSharedReq accesses(hits+misses) system.cpu0.l2cache.ReadSharedReq_accesses::total 480198 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10390 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4627 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10362 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4607 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.inst 1109883 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.data 749720 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1874620 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10390 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4627 # number of overall (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1874572 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10362 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4607 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.inst 1109883 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.data 749720 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1874620 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020597 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.029825 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.023440 # miss rate for ReadReq accesses +system.cpu0.l2cache.overall_accesses::total 1874572 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026443 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.030389 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.027657 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649928 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.649928 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037865 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037865 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266371 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266371 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020597 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.029825 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037865 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404259 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.184282 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020597 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.029825 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037865 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404259 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.184282 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650236 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650236 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.053785 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.053785 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.282765 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.282765 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026443 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.030389 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.053785 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.414870 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.197989 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026443 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.030389 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.053785 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.414870 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.197989 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.writebacks::writebacks 192746 # number of writebacks -system.cpu0.l2cache.writebacks::total 192746 # number of writebacks -system.cpu0.toL2Bus.snoop_filter.tot_requests 3719480 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1859901 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.l2cache.writebacks::writebacks 192868 # number of writebacks +system.cpu0.l2cache.writebacks::total 192868 # number of writebacks +system.cpu0.toL2Bus.snoop_filter.tot_requests 3719490 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1859911 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27861 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 218561 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215432 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3129 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 111560 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 109856 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1704 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 1651491 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 28340 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 28340 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 510613 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1292232 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 26245 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18421 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 44666 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 510065 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1292780 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 26265 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18411 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 44676 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExReq 269522 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExResp 269522 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1109883 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480198 # Transaction distribution system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3347172 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402087 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402107 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5790883 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5790903 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142067768 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92555520 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size::total 234706536 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 623474 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 12368448 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 4317750 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.067119 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.253107 # Request fanout histogram +system.cpu0.toL2Bus.snoops 530280 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 12377344 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 4224545 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.042934 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.204688 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 4031077 93.36% 93.36% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 283544 6.57% 99.93% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 3129 0.07% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 4044873 95.75% 95.75% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 177968 4.21% 99.96% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1704 0.04% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4317750 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 4224545 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -865,32 +861,32 @@ system.cpu1.dcache.tags.data_accesses 39746590 # Nu system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.ReadReq_hits::cpu1.data 11857228 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 11857228 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7396366 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7396366 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7396381 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7396381 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50103 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 50103 # number of SoftPFReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91426 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 91426 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72412 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72412 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19253594 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19253594 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19303697 # number of overall hits -system.cpu1.dcache.overall_hits::total 19303697 # number of overall hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72441 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 72441 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 19253609 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19253609 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19303712 # number of overall hits +system.cpu1.dcache.overall_hits::total 19303712 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 136574 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 136574 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 92490 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 92490 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 92475 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92475 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30717 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 30717 # number of SoftPFReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22549 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 22549 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 229064 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 229064 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259781 # number of overall misses -system.cpu1.dcache.overall_misses::total 259781 # number of overall misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22520 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 22520 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 229049 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 229049 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 259766 # number of overall misses +system.cpu1.dcache.overall_misses::total 259766 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 11993802 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 11993802 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 7488856 # number of WriteReq accesses(hits+misses) @@ -907,18 +903,18 @@ system.cpu1.dcache.overall_accesses::cpu1.data 19563478 system.cpu1.dcache.overall_accesses::total 19563478 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011387 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.011387 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012350 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.012350 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012348 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.012348 # miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380067 # miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380067 # miss rate for SoftPFReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054970 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054970 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237455 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237455 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237150 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237150 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013278 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.013278 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -984,179 +980,179 @@ system.cpu1.l2cache.prefetcher.pfInCache 0 # nu system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 47270 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15227.212087 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1184400 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 62319 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 19.005440 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 45747 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14812.613567 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 613917 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 60319 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 10.177838 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 15223.147061 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.040750 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.024276 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.929147 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000125 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_blocks::writebacks 14808.372104 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.216207 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.025256 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.903831 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000135 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.929395 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15029 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_percent::total 0.904090 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14549 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 528 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9407 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5094 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001221 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.917297 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 24496500 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 24496500 # Number of data accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1590 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8844 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4115 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001404 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.888000 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 25046952 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 25046952 # Number of data accesses system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3624 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1921 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 5545 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 120975 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 120975 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 583053 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 583053 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19849 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 19849 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510459 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 510459 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99238 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 99238 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3624 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1921 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 510459 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 119087 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 635091 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3624 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1921 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 510459 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 119087 # number of overall hits -system.cpu1.l2cache.overall_hits::total 635091 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 336 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 270 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 606 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28875 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28875 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22549 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22549 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43766 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 43766 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13339 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 13339 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73371 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 73371 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 336 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 270 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 13339 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 117137 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 131082 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 336 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 270 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 13339 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 117137 # number of overall misses -system.cpu1.l2cache.overall_misses::total 131082 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3960 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3528 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1892 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 5420 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 120650 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 120650 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 583378 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 583378 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19790 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 19790 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 502408 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 502408 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 97451 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 97451 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3528 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1892 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 502408 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 117241 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 625069 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3528 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1892 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 502408 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 117241 # number of overall hits +system.cpu1.l2cache.overall_hits::total 625069 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 436 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 299 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 735 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28860 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28860 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22520 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22520 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43825 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 43825 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21390 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 21390 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 75158 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 75158 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 436 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 299 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 21390 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 118983 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 141108 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 436 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 299 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 21390 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 118983 # number of overall misses +system.cpu1.l2cache.overall_misses::total 141108 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3964 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2191 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 6151 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 120975 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 120975 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 583053 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 583053 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28875 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 28875 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22549 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 22549 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 6155 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 120650 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 120650 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 583378 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 583378 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28860 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 28860 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22520 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 22520 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523798 # number of ReadCleanReq accesses(hits+misses) system.cpu1.l2cache.ReadCleanReq_accesses::total 523798 # number of ReadCleanReq accesses(hits+misses) system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172609 # number of ReadSharedReq accesses(hits+misses) system.cpu1.l2cache.ReadSharedReq_accesses::total 172609 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3960 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3964 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2191 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.inst 523798 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.data 236224 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 766173 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3960 # number of overall (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 766177 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3964 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2191 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.inst 523798 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 236224 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 766173 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.084848 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.123231 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.098521 # miss rate for ReadReq accesses +system.cpu1.l2cache.overall_accesses::total 766177 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.109990 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.136467 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.119415 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.687982 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.687982 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025466 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025466 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.425071 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.425071 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.084848 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.123231 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025466 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495873 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.171087 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.084848 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.123231 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025466 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495873 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.171087 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688910 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688910 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.040836 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.040836 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.435423 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.435423 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.109990 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.136467 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.040836 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.503687 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.184172 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.109990 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.136467 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.040836 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.503687 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.184172 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.writebacks::writebacks 32649 # number of writebacks -system.cpu1.l2cache.writebacks::total 32649 # number of writebacks -system.cpu1.toL2Bus.snoop_filter.tot_requests 1533187 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773168 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.l2cache.writebacks::writebacks 32289 # number of writebacks +system.cpu1.l2cache.writebacks::total 32289 # number of writebacks +system.cpu1.toL2Bus.snoop_filter.tot_requests 1533143 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773124 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11161 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 166233 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164289 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1944 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 97275 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 90578 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 6697 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 709156 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2504 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 2504 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 120975 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 594214 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 28875 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22549 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 51424 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 120650 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 594539 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 28860 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22520 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 51380 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523798 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172609 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571236 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778655 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778567 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2368587 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2368499 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67014084 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27419302 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size::total 94470778 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 347619 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 2342400 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1819791 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.108284 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.314158 # Request fanout histogram +system.cpu1.toL2Bus.snoops 295837 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 2333632 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1767980 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.075142 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.277617 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1624681 89.28% 89.28% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 193166 10.61% 99.89% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1944 0.11% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1641828 92.86% 92.86% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 119455 6.76% 99.62% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 6697 0.38% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1819791 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1767980 # Request fanout histogram system.iobus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30995 # Transaction distribution system.iobus.trans_dist::ReadResp 30995 # Transaction distribution @@ -1257,242 +1253,233 @@ system.iocache.avg_blocked_cycles::no_targets nan system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 107708 # number of replacements -system.l2c.tags.tagsinuse 62491.556145 # Cycle average of tags in use -system.l2c.tags.total_refs 243932 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168376 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.448734 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48154.057665 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.929229 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.998273 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7781.790625 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4106.660422 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.967503 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1678.829831 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 764.322598 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.734773 # Average percentage of cache occupancy +system.l2c.tags.replacements 135163 # number of replacements +system.l2c.tags.tagsinuse 65177.726515 # Cycle average of tags in use +system.l2c.tags.total_refs 431584 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 200605 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.151412 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 86559025000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 6643.934415 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.937413 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.032741 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7087.737158 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 43017.411906 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1645.646531 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6779.026349 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.101378 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.118741 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.062663 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.025617 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011663 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.953545 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.108150 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.656394 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.025111 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.103440 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994533 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60662 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65436 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1796 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13211 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 45580 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 15758 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 49214 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.925629 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5178046 # Number of tag accesses -system.l2c.tags.data_accesses 5178046 # Number of data accesses +system.l2c.tags.occ_task_id_percent::1024 0.998474 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5327823 # Number of tag accesses +system.l2c.tags.data_accesses 5327823 # Number of data accesses system.l2c.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 225395 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 225395 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 578 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 107 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 685 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 78 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 52 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 130 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 13904 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 3026 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 16930 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 73 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 78 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 25302 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 75954 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 40 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 44 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 10936 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11571 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 123998 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 73 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 78 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 25302 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 89858 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 40 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 44 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 10936 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14597 # number of demand (read+write) hits -system.l2c.demand_hits::total 140928 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 73 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 78 # number of overall hits -system.l2c.overall_hits::cpu0.inst 25302 # number of overall hits -system.l2c.overall_hits::cpu0.data 89858 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 40 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 44 # number of overall hits -system.l2c.overall_hits::cpu1.inst 10936 # number of overall hits -system.l2c.overall_hits::cpu1.data 14597 # number of overall hits -system.l2c.overall_hits::total 140928 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9941 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3286 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13227 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 736 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1140 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1876 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 136523 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15823 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 152346 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses +system.l2c.WritebackDirty_hits::writebacks 225157 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 225157 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 10195 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 3254 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 13449 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 779 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 1161 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 1940 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 13430 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 3004 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 16434 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 116 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 70 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 42080 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 82797 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 36 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 24 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 18817 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 12978 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 156918 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 116 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 70 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 42080 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 96227 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 36 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 24 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 18817 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 15982 # number of demand (read+write) hits +system.l2c.demand_hits::total 173352 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 116 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 70 # number of overall hits +system.l2c.overall_hits::cpu0.inst 42080 # number of overall hits +system.l2c.overall_hits::cpu0.data 96227 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 36 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 24 # number of overall hits +system.l2c.overall_hits::cpu1.inst 18817 # number of overall hits +system.l2c.overall_hits::cpu1.data 15982 # number of overall hits +system.l2c.overall_hits::total 173352 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 275 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 112 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 387 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 30 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 26 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 56 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 137059 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 15933 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 152992 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 8 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 16724 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 11220 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 2403 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1107 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 31464 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses +system.l2c.ReadSharedReq_misses::cpu0.inst 17615 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 12278 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 2573 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1450 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 33926 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 16724 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 147743 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2403 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16930 # number of demand (read+write) misses -system.l2c.demand_misses::total 183810 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses +system.l2c.demand_misses::cpu0.inst 17615 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 149337 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2573 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 17383 # number of demand (read+write) misses +system.l2c.demand_misses::total 186918 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 16724 # number of overall misses -system.l2c.overall_misses::cpu0.data 147743 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2403 # number of overall misses -system.l2c.overall_misses::cpu1.data 16930 # number of overall misses -system.l2c.overall_misses::total 183810 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 225395 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 225395 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 10519 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3393 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13912 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 814 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1192 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2006 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 150427 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 18849 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 169276 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 80 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 80 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 42026 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 87174 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 41 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 44 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 13339 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 12678 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 155462 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 80 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 80 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 42026 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 237601 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 41 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 44 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 13339 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 31527 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 324738 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 80 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 80 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 42026 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 237601 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 41 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 44 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 13339 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 31527 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 324738 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.945052 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.968464 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.950762 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.904177 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.956376 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.935194 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.907570 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.839461 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.899986 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.087500 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.025000 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.397944 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128708 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.024390 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.180148 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.087317 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.202390 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.087500 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.025000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.397944 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.621811 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.024390 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.180148 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.537000 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.566026 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.087500 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.025000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.397944 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.621811 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.024390 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.180148 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.537000 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.566026 # miss rate for overall accesses +system.l2c.overall_misses::cpu0.inst 17615 # number of overall misses +system.l2c.overall_misses::cpu0.data 149337 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2573 # number of overall misses +system.l2c.overall_misses::cpu1.data 17383 # number of overall misses +system.l2c.overall_misses::total 186918 # number of overall misses +system.l2c.WritebackDirty_accesses::writebacks 225157 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 225157 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 10470 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3366 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 13836 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 809 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1187 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1996 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 150489 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 18937 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 169426 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 124 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 72 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 59695 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 95075 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 36 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 24 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 21390 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 14428 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 190844 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 124 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 72 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 59695 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 245564 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 36 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 24 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 21390 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 33365 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 360270 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 124 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 72 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 59695 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 245564 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 36 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 24 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 21390 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 33365 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 360270 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.026266 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.033274 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.027971 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.037083 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.021904 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.028056 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.910758 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.841369 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.903002 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.064516 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.027778 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.295083 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.129140 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.120290 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.100499 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.177768 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.064516 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.027778 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.295083 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.608139 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.120290 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.520995 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.518828 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.064516 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.027778 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.295083 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.608139 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.120290 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.520995 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.518828 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 96260 # number of writebacks -system.l2c.writebacks::total 96260 # number of writebacks -system.membus.snoop_filter.tot_requests 462665 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 248104 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.writebacks::writebacks 102405 # number of writebacks +system.l2c.writebacks::total 102405 # number of writebacks +system.membus.snoop_filter.tot_requests 459549 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 242014 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 43995 # Transaction distribution -system.membus.trans_dist::ReadResp 75711 # Transaction distribution +system.membus.trans_dist::ReadResp 78173 # Transaction distribution system.membus.trans_dist::WriteReq 30844 # Transaction distribution system.membus.trans_dist::WriteResp 30844 # Transaction distribution -system.membus.trans_dist::WritebackDirty 132450 # Transaction distribution -system.membus.trans_dist::CleanEvict 8737 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60370 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40840 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15528 # Transaction distribution -system.membus.trans_dist::ReadExReq 152316 # Transaction distribution -system.membus.trans_dist::ReadExResp 151921 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 31716 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138595 # Transaction distribution +system.membus.trans_dist::CleanEvict 11037 # Transaction distribution +system.membus.trans_dist::UpgradeReq 47132 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38991 # Transaction distribution +system.membus.trans_dist::UpgradeResp 461 # Transaction distribution +system.membus.trans_dist::ReadExReq 153373 # Transaction distribution +system.membus.trans_dist::ReadExResp 152974 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34178 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13468 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 616948 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 738326 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 602273 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 723651 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 847720 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 833045 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26936 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17953992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18143762 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18572232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18762002 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20476050 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21094290 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 537492 # Request fanout histogram -system.membus.snoop_fanout::mean 0.010359 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.101252 # Request fanout histogram +system.membus.snoop_fanout::samples 534369 # Request fanout histogram +system.membus.snoop_fanout::mean 0.010375 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.101327 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 531924 98.96% 98.96% # Request fanout histogram -system.membus.snoop_fanout::1 5568 1.04% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 528825 98.96% 98.96% # Request fanout histogram +system.membus.snoop_fanout::1 5544 1.04% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 537492 # Request fanout histogram +system.membus.snoop_fanout::total 534369 # Request fanout histogram system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states @@ -1562,43 +1549,43 @@ system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 862712 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 444233 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 128693 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 9862 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 9359 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 503 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 898844 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 454083 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 154581 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 30372 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 29420 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 952 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 43999 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 301604 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 337174 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 30844 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 30844 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 225395 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 64670 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60630 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40970 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 101600 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 213426 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 213426 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 257605 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1162374 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 422639 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1585013 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34441336 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10376426 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 44817762 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 113249 # Total snoops (count) -system.toL2Bus.snoopTraffic 6177216 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 1050551 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.300796 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.459647 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 225157 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 65355 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60563 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40931 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 101494 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 213640 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 213640 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 293175 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1214281 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 442535 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1656816 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36095992 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10996714 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 47092706 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 140680 # Total snoops (count) +system.toL2Bus.snoopTraffic 6570496 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 1114107 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.326086 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.470599 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 735052 69.97% 69.97% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 314996 29.98% 99.95% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 503 0.05% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 751764 67.48% 67.48% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 361391 32.44% 99.91% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 952 0.09% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1050551 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 1114107 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index aefcf2796..cc1e1b968 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,58 +1,58 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.783855 # Number of seconds simulated -sim_ticks 2783855034000 # Number of ticks simulated -final_tick 2783855034000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2783854715000 # Number of ticks simulated +final_tick 2783854715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 704767 # Simulator instruction rate (inst/s) -host_op_rate 857940 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13741971204 # Simulator tick rate (ticks/s) -host_mem_usage 573692 # Number of bytes of host memory used -host_seconds 202.58 # Real time elapsed on the host -sim_insts 142771937 # Number of instructions simulated -sim_ops 173801895 # Number of ops (including micro ops) simulated +host_inst_rate 812904 # Simulator instruction rate (inst/s) +host_op_rate 989581 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15850589349 # Simulator tick rate (ticks/s) +host_mem_usage 583016 # Number of bytes of host memory used +host_seconds 175.63 # Real time elapsed on the host +sim_insts 142771202 # Number of instructions simulated +sim_ops 173801044 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10324900 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10324772 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11533448 # Number of bytes read from this memory +system.physmem.bytes_read::total 11533320 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8840960 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8858484 # Number of bytes written to this memory +system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 161846 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 161844 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189183 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138140 # Number of write requests responded to by this memory +system.physmem.num_reads::total 189181 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142521 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3708850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3708804 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4142977 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4142932 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3175798 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3175775 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3182092 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3175798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3182070 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3175775 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3715145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3715099 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7325070 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.physmem.bw_total::total 7325002 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -65,9 +65,9 @@ system.realview.nvmem.bw_inst_read::cpu.inst 7 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -75,7 +75,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -105,7 +105,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 10028 # Table walker walks requested system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency @@ -126,9 +126,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31526014 # DTB read hits +system.cpu.dtb.read_hits 31525882 # DTB read hits system.cpu.dtb.read_misses 8580 # DTB read misses -system.cpu.dtb.write_hits 23124171 # DTB write hits +system.cpu.dtb.write_hits 23124079 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -139,13 +139,13 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534594 # DTB read accesses -system.cpu.dtb.write_accesses 23125619 # DTB write accesses +system.cpu.dtb.read_accesses 31534462 # DTB read accesses +system.cpu.dtb.write_accesses 23125527 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54650185 # DTB hits +system.cpu.dtb.hits 54649961 # DTB hits system.cpu.dtb.misses 10028 # DTB misses -system.cpu.dtb.accesses 54660213 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.accesses 54659989 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -175,7 +175,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 4762 # Table walker walks requested system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency @@ -194,7 +194,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 147038452 # ITB inst hits +system.cpu.itb.inst_hits 147037694 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -211,14 +211,14 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 147043214 # ITB inst accesses -system.cpu.itb.hits 147038452 # DTB hits +system.cpu.itb.inst_accesses 147042456 # ITB inst accesses +system.cpu.itb.hits 147037694 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 147043214 # DTB accesses +system.cpu.itb.accesses 147042456 # DTB accesses system.cpu.numPwrStateTransitions 6160 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 3080 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 874939595.358117 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17329944407.298908 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 874939633.669805 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17329944405.377167 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 3002 97.47% 97.47% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 72 2.34% 99.81% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state @@ -228,38 +228,38 @@ system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 3080 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 89041080297 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2694813953703 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5567713149 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 89040643297 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2694814071703 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 5567712511 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed -system.cpu.committedInsts 142771937 # Number of instructions committed -system.cpu.committedOps 173801895 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 153161571 # Number of integer alu accesses +system.cpu.committedInsts 142771202 # Number of instructions committed +system.cpu.committedOps 173801044 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 153160791 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses -system.cpu.num_func_calls 16873976 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18730294 # number of instructions that are conditional controls -system.cpu.num_int_insts 153161571 # number of integer instructions +system.cpu.num_func_calls 16873864 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18730220 # number of instructions that are conditional controls +system.cpu.num_int_insts 153160791 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions -system.cpu.num_int_register_reads 285044694 # number of times the integer registers were read -system.cpu.num_int_register_writes 107178579 # number of times the integer registers were written +system.cpu.num_int_register_reads 285043206 # number of times the integer registers were read +system.cpu.num_int_register_writes 107178068 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 530850452 # number of times the CC registers were read -system.cpu.num_cc_register_writes 62364047 # number of times the CC registers were written -system.cpu.num_mem_refs 55938751 # number of memory refs -system.cpu.num_load_insts 31855653 # Number of load instructions -system.cpu.num_store_insts 24083098 # Number of store instructions -system.cpu.num_idle_cycles 5389630889.858858 # Number of idle cycles -system.cpu.num_busy_cycles 178082259.141142 # Number of busy cycles +system.cpu.num_cc_register_reads 530847827 # number of times the CC registers were read +system.cpu.num_cc_register_writes 62363707 # number of times the CC registers were written +system.cpu.num_mem_refs 55938510 # number of memory refs +system.cpu.num_load_insts 31855508 # Number of load instructions +system.cpu.num_store_insts 24083002 # Number of store instructions +system.cpu.num_idle_cycles 5389631125.859330 # Number of idle cycles +system.cpu.num_busy_cycles 178081385.140670 # Number of busy cycles system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles system.cpu.idle_fraction 0.968015 # Percentage of idle cycles -system.cpu.Branches 36397005 # Number of branches fetched +system.cpu.Branches 36396820 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 121152199 68.36% 68.36% # Class of executed instruction -system.cpu.op_class::IntMult 116879 0.07% 68.43% # Class of executed instruction +system.cpu.op_class::IntAlu 121151571 68.36% 68.36% # Class of executed instruction +system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction @@ -287,17 +287,17 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::MemRead 31855653 17.98% 86.41% # Class of executed instruction -system.cpu.op_class::MemWrite 24083098 13.59% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 31855508 17.98% 86.41% # Class of executed instruction +system.cpu.op_class::MemWrite 24083002 13.59% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 177218735 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 819389 # number of replacements +system.cpu.op_class::total 177217860 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 819387 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53784005 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819901 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.598170 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 53783783 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819899 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.598059 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -307,51 +307,51 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219235605 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219235605 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 30128867 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30128867 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22339858 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22339858 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 219234707 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219234707 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 30128737 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30128737 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22339767 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22339767 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 395067 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 395067 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 457333 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 457333 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52468725 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52468725 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52863792 # number of overall hits -system.cpu.dcache.overall_hits::total 52863792 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 396279 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 396279 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 52468504 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52468504 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52863571 # number of overall hits +system.cpu.dcache.overall_hits::total 52863571 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 301662 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 301662 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 116119 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 116119 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 697942 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 697942 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 814061 # number of overall misses -system.cpu.dcache.overall_misses::total 814061 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30525146 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30525146 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641521 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641521 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 697939 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 697939 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 814058 # number of overall misses +system.cpu.dcache.overall_misses::total 814058 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 30525014 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30525014 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641429 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641429 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53166667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53166667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53677853 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53677853 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 53166443 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53166443 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53677629 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53677629 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses @@ -372,14 +372,14 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks -system.cpu.dcache.writebacks::total 682017 # number of writebacks -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1698989 # number of replacements +system.cpu.dcache.writebacks::writebacks 682138 # number of writebacks +system.cpu.dcache.writebacks::total 682138 # number of writebacks +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1698988 # number of replacements system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145342052 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1699501 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 85.520427 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 145341295 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1699500 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 85.520032 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 7831497000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy @@ -390,27 +390,27 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77 system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 148741066 # Number of tag accesses -system.cpu.icache.tags.data_accesses 148741066 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 145342052 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145342052 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145342052 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145342052 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145342052 # number of overall hits -system.cpu.icache.overall_hits::total 145342052 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1699507 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1699507 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1699507 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1699507 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1699507 # number of overall misses -system.cpu.icache.overall_misses::total 1699507 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 147041559 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 147041559 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 147041559 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 147041559 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 147041559 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 147041559 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 148740307 # Number of tag accesses +system.cpu.icache.tags.data_accesses 148740307 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 145341295 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145341295 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 145341295 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 145341295 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 145341295 # number of overall hits +system.cpu.icache.overall_hits::total 145341295 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1699506 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699506 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1699506 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699506 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1699506 # number of overall misses +system.cpu.icache.overall_misses::total 1699506 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 147040801 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 147040801 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 147040801 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 147040801 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 147040801 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 147040801 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses @@ -423,73 +423,70 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1698989 # number of writebacks -system.cpu.icache.writebacks::total 1698989 # number of writebacks -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 109914 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65155.312641 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4524828 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 175195 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 25.827381 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 48764.064013 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931994 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.693007 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.619283 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.744081 # Average percentage of cache occupancy +system.cpu.icache.writebacks::writebacks 1698988 # number of writebacks +system.cpu.icache.writebacks::total 1698988 # number of writebacks +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 109912 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65246.862245 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4827688 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 175338 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 27.533609 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 71491095000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.971735 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.023390 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9170.132693 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56073.734427 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139903 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.110163 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139925 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.855617 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995588 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65421 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9745 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55480 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40578737 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40578737 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 11218 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 682017 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 682017 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1666988 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1666988 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 151130 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 151130 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681192 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1681192 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505442 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 505442 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1681192 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 656572 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2348982 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1681192 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 656572 # number of overall hits -system.cpu.l2cache.overall_hits::total 2348982 # number of overall hits +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998245 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 40257223 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40257223 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5671 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2714 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 8385 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 682138 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 682138 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1666989 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1666989 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 2746 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 2746 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 152790 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 152790 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681191 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1681191 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505440 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 505440 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 5671 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 2714 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1681191 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 658230 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2347806 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 5671 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 2714 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681191 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 658230 # number of overall hits +system.cpu.l2cache.overall_hits::total 2347806 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 147777 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 147777 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 146117 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 146117 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18298 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15568 # number of ReadSharedReq misses @@ -497,116 +494,116 @@ system.cpu.l2cache.ReadSharedReq_misses::total 15568 system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 18298 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 163345 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 181652 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 161685 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 179992 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 163345 # number of overall misses -system.cpu.l2cache.overall_misses::total 181652 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 11227 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 682017 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 682017 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1666988 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1666988 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 161685 # number of overall misses +system.cpu.l2cache.overall_misses::total 179992 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5678 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2716 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 8394 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 682138 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 682138 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1666989 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1666989 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2755 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2755 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699490 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1699490 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521010 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 521010 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1699490 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819917 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2530634 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1699490 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819917 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2530634 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000802 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699489 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1699489 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521008 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5678 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 2716 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699489 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819915 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2527798 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5678 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 2716 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699489 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819915 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2527798 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001233 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000736 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001072 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003267 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.003267 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494391 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.494391 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.488838 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.488838 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010767 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029880 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029880 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001233 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000736 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010767 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.199221 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.071781 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.197197 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.071205 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001233 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000736 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010767 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.199221 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.071781 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.197197 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.071205 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks -system.cpu.l2cache.writebacks::total 101950 # number of writebacks -system.cpu.toL2Bus.snoop_filter.tot_requests 5059879 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540474 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39263 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks +system.cpu.l2cache.writebacks::total 101949 # number of writebacks +system.cpu.toL2Bus.snoop_filter.tot_requests 5059872 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540470 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2288317 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2288314 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 682017 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1698989 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 137372 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 682138 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1698988 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 137249 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2757 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699507 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 521010 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116047 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581961 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116044 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581953 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7753434 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96306529 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7753423 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96314145 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 313957213 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 182976 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 8840960 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5318714 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018479 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.134677 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 313964701 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 115326 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6541312 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5251057 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018717 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.135522 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5220428 98.15% 98.15% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 98286 1.85% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5152775 98.13% 98.13% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98282 1.87% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5318714 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.snoop_fanout::total 5251057 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -657,14 +654,14 @@ system.iobus.pkt_size_system.bridge.master::total 159061 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909892 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909890 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 227410175509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909892 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 227410176509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.909890 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -672,7 +669,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328176 # Number of tag accesses system.iocache.tags.data_accesses 328176 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses system.iocache.ReadReq_misses::total 240 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -705,65 +702,71 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.membus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 362809 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 151023 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 488 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 40087 # Transaction distribution system.membus.trans_dist::ReadResp 74202 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::WritebackDirty 138140 # Transaction distribution -system.membus.trans_dist::CleanEvict 8204 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution +system.membus.trans_dist::CleanEvict 8203 # Transaction distribution +system.membus.trans_dist::UpgradeReq 130 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution -system.membus.trans_dist::ReadExReq 145998 # Transaction distribution -system.membus.trans_dist::ReadExResp 145998 # Transaction distribution +system.membus.trans_dist::UpgradeResp 132 # Transaction distribution +system.membus.trans_dist::ReadExReq 145996 # Transaction distribution +system.membus.trans_dist::ReadExResp 145996 # Transaction distribution system.membus.trans_dist::ReadSharedReq 34115 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506584 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613944 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 497824 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 605184 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723302 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 714542 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092540 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255513 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092348 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255321 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20587033 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20586841 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 434823 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 430442 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012836 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.112565 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 434823 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 424917 98.72% 98.72% # Request fanout histogram +system.membus.snoop_fanout::1 5525 1.28% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 434823 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 430442 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -795,28 +798,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index b27032bf8..dc9310742 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,158 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.869797 # Number of seconds simulated -sim_ticks 2869796829000 # Number of ticks simulated -final_tick 2869796829000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.870001 # Number of seconds simulated +sim_ticks 2870000710000 # Number of ticks simulated +final_tick 2870000710000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 478807 # Simulator instruction rate (inst/s) -host_op_rate 579136 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10450673539 # Simulator tick rate (ticks/s) -host_mem_usage 612484 # Number of bytes of host memory used -host_seconds 274.60 # Real time elapsed on the host -sim_insts 131482259 # Number of instructions simulated -sim_ops 159033076 # Number of ops (including micro ops) simulated +host_inst_rate 371570 # Simulator instruction rate (inst/s) +host_op_rate 449436 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8101953096 # Simulator tick rate (ticks/s) +host_mem_usage 621024 # Number of bytes of host memory used +host_seconds 354.24 # Real time elapsed on the host +sim_insts 131623434 # Number of instructions simulated +sim_ops 159206188 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1151908 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1242084 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8334784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147092 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 510612 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 354880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1182180 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1312420 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8596224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 150484 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 578772 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 396096 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11742896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1151908 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147092 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1299000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8345408 # Number of bytes written to this memory +system.physmem.bytes_read::total 12217776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1182180 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 150484 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1332664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8789056 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8362972 # Number of bytes written to this memory +system.physmem.bytes_written::total 8806620 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26452 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 19927 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 130231 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2453 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 7999 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 5545 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26925 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21026 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134316 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2506 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6189 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 192631 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 130397 # Number of write requests responded to by this memory +system.physmem.num_reads::total 200051 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 137329 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 134788 # Number of write requests responded to by this memory +system.physmem.num_writes::total 141720 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 401390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 432813 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2904312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 51255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 177926 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 123660 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4091891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 401390 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 51255 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 452645 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2908014 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 411909 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 457289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2995199 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52433 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 201663 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 138013 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4257064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 411909 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52433 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 464343 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3062388 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6106 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2914134 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2908014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3068508 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3062388 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 401390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 438919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2904312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 51255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 177940 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 123660 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7006025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 192631 # Number of read requests accepted -system.physmem.writeReqs 134788 # Number of write requests accepted -system.physmem.readBursts 192631 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 134788 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12319616 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue -system.physmem.bytesWritten 8376000 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11742896 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8362972 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 411909 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 463395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2995199 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 52433 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 201677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 138013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7325572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 200051 # Number of read requests accepted +system.physmem.writeReqs 141720 # Number of write requests accepted +system.physmem.readBursts 200051 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 141720 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12793920 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue +system.physmem.bytesWritten 8819520 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12217776 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8806620 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11574 # Per bank write bursts -system.physmem.perBankRdBursts::1 11705 # Per bank write bursts -system.physmem.perBankRdBursts::2 12139 # Per bank write bursts -system.physmem.perBankRdBursts::3 12297 # Per bank write bursts -system.physmem.perBankRdBursts::4 20811 # Per bank write bursts -system.physmem.perBankRdBursts::5 12493 # Per bank write bursts -system.physmem.perBankRdBursts::6 11636 # Per bank write bursts -system.physmem.perBankRdBursts::7 11627 # Per bank write bursts -system.physmem.perBankRdBursts::8 11518 # Per bank write bursts -system.physmem.perBankRdBursts::9 11803 # Per bank write bursts -system.physmem.perBankRdBursts::10 10854 # Per bank write bursts -system.physmem.perBankRdBursts::11 10225 # Per bank write bursts -system.physmem.perBankRdBursts::12 10900 # Per bank write bursts -system.physmem.perBankRdBursts::13 11460 # Per bank write bursts -system.physmem.perBankRdBursts::14 10649 # Per bank write bursts -system.physmem.perBankRdBursts::15 10803 # Per bank write bursts -system.physmem.perBankWrBursts::0 8359 # Per bank write bursts -system.physmem.perBankWrBursts::1 8644 # Per bank write bursts -system.physmem.perBankWrBursts::2 9057 # Per bank write bursts -system.physmem.perBankWrBursts::3 8858 # Per bank write bursts -system.physmem.perBankWrBursts::4 8408 # Per bank write bursts -system.physmem.perBankWrBursts::5 8900 # Per bank write bursts -system.physmem.perBankWrBursts::6 8435 # Per bank write bursts -system.physmem.perBankWrBursts::7 8166 # Per bank write bursts -system.physmem.perBankWrBursts::8 8021 # Per bank write bursts -system.physmem.perBankWrBursts::9 8475 # Per bank write bursts -system.physmem.perBankWrBursts::10 7798 # Per bank write bursts -system.physmem.perBankWrBursts::11 7415 # Per bank write bursts -system.physmem.perBankWrBursts::12 7820 # Per bank write bursts -system.physmem.perBankWrBursts::13 7815 # Per bank write bursts -system.physmem.perBankWrBursts::14 7421 # Per bank write bursts -system.physmem.perBankWrBursts::15 7283 # Per bank write bursts +system.physmem.perBankRdBursts::0 11709 # Per bank write bursts +system.physmem.perBankRdBursts::1 12160 # Per bank write bursts +system.physmem.perBankRdBursts::2 12038 # Per bank write bursts +system.physmem.perBankRdBursts::3 12178 # Per bank write bursts +system.physmem.perBankRdBursts::4 20671 # Per bank write bursts +system.physmem.perBankRdBursts::5 12806 # Per bank write bursts +system.physmem.perBankRdBursts::6 12086 # Per bank write bursts +system.physmem.perBankRdBursts::7 12477 # Per bank write bursts +system.physmem.perBankRdBursts::8 12638 # Per bank write bursts +system.physmem.perBankRdBursts::9 12504 # Per bank write bursts +system.physmem.perBankRdBursts::10 11795 # Per bank write bursts +system.physmem.perBankRdBursts::11 11324 # Per bank write bursts +system.physmem.perBankRdBursts::12 11594 # Per bank write bursts +system.physmem.perBankRdBursts::13 11843 # Per bank write bursts +system.physmem.perBankRdBursts::14 11003 # Per bank write bursts +system.physmem.perBankRdBursts::15 11079 # Per bank write bursts +system.physmem.perBankWrBursts::0 8559 # Per bank write bursts +system.physmem.perBankWrBursts::1 9022 # Per bank write bursts +system.physmem.perBankWrBursts::2 9017 # Per bank write bursts +system.physmem.perBankWrBursts::3 8844 # Per bank write bursts +system.physmem.perBankWrBursts::4 8437 # Per bank write bursts +system.physmem.perBankWrBursts::5 9230 # Per bank write bursts +system.physmem.perBankWrBursts::6 8825 # Per bank write bursts +system.physmem.perBankWrBursts::7 8866 # Per bank write bursts +system.physmem.perBankWrBursts::8 9056 # Per bank write bursts +system.physmem.perBankWrBursts::9 8974 # Per bank write bursts +system.physmem.perBankWrBursts::10 8482 # Per bank write bursts +system.physmem.perBankWrBursts::11 8329 # Per bank write bursts +system.physmem.perBankWrBursts::12 8472 # Per bank write bursts +system.physmem.perBankWrBursts::13 8225 # Per bank write bursts +system.physmem.perBankWrBursts::14 7833 # Per bank write bursts +system.physmem.perBankWrBursts::15 7634 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 25 # Number of times write queue was full causing retry -system.physmem.totGap 2869796310500 # Total gap between requests +system.physmem.numWrRetry 37 # Number of times write queue was full causing retry +system.physmem.totGap 2870000192000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9732 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 182871 # Read request sizes (log2) +system.physmem.readPktSize::6 190291 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 130397 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 135454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 15340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 9792 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6685 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5269 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4441 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3740 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 102 # What read queue length does an incoming req see +system.physmem.writePktSize::6 137329 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 139673 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 16007 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7050 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4708 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 97 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 43 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -181,165 +185,164 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 146 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 97 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 85101 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 243.188118 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 136.988063 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 305.573889 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45210 53.13% 53.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16886 19.84% 72.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5688 6.68% 79.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3460 4.07% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2293 2.69% 86.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1445 1.70% 88.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 997 1.17% 89.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 929 1.09% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8193 9.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 85101 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6403 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.062939 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 590.633185 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6402 99.98% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6403 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6403 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.439638 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.792302 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.006159 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5407 84.44% 84.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 293 4.58% 89.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 63 0.98% 90.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 46 0.72% 90.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 252 3.94% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 29 0.45% 95.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 22 0.34% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 17 0.27% 95.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 14 0.22% 95.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.12% 96.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.08% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 12 0.19% 96.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 163 2.55% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.06% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 10 0.16% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 4 0.06% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 10 0.16% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 4 0.06% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.06% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.05% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 5 0.08% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 9 0.14% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6403 # Writes before turning the bus around for reads -system.physmem.totQLat 4388531068 # Total ticks spent queuing -system.physmem.totMemAccLat 7997793568 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 962470000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22798.27 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::44 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 128 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 85925 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 251.537690 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 143.363316 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 306.826134 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 42893 49.92% 49.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18336 21.34% 71.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6281 7.31% 78.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3896 4.53% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2533 2.95% 86.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1590 1.85% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1050 1.22% 89.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 985 1.15% 90.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8361 9.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 85925 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6834 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.251244 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 562.918265 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6833 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6834 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6834 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.164618 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.651361 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.320527 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5790 84.72% 84.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 323 4.73% 89.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 59 0.86% 90.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 46 0.67% 90.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 267 3.91% 94.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 35 0.51% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 21 0.31% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 28 0.41% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 23 0.34% 96.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 7 0.10% 96.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 12 0.18% 96.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 155 2.27% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.04% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.07% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 6 0.09% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 12 0.18% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.01% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 6 0.09% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.01% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.16% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6834 # Writes before turning the bus around for reads +system.physmem.totQLat 4674239132 # Total ticks spent queuing +system.physmem.totMemAccLat 8422457882 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 999525000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23382.30 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41548.27 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.29 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.09 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.91 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 42132.30 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.46 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.07 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.07 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.14 # Average write queue length when enqueuing -system.physmem.readRowHits 160943 # Number of row buffer hits during reads -system.physmem.writeRowHits 77324 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.07 # Row buffer hit rate for writes -system.physmem.avgGap 8764904.63 # Average gap between requests -system.physmem.pageHitRate 73.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 343133280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 187225500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 813391800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 445998960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187440976320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 84650934555 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1647621183000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1921502843415 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.561249 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2740835391788 # Time in different power states -system.physmem_0.memoryStateTime::REF 95828720000 # Time in different power states +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.74 # Average write queue length when enqueuing +system.physmem.readRowHits 166683 # Number of row buffer hits during reads +system.physmem.writeRowHits 85101 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 61.75 # Row buffer hit rate for writes +system.physmem.avgGap 8397436.27 # Average gap between requests +system.physmem.pageHitRate 74.55 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 335240640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 182919000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 827767200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 458784000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187454198880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 84698340030 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647701064750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1921658314500 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.568191 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2740964082488 # Time in different power states +system.physmem_0.memoryStateTime::REF 95835480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33132603712 # Time in different power states +system.physmem_0.memoryStateTime::ACT 33201034512 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 300230280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 163816125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 688053600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 402071040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187440976320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 83039782815 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1649034474000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1921069404180 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.410214 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2743194226190 # Time in different power states -system.physmem_1.memoryStateTime::REF 95828720000 # Time in different power states +system.physmem_1.actEnergy 314352360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 171521625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 731484000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 434192400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187454198880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 83981561895 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1648329817500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1921417128660 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.484154 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2742009812705 # Time in different power states +system.physmem_1.memoryStateTime::REF 95835480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30771048810 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32151144795 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -358,9 +361,9 @@ system.realview.nvmem.bw_inst_read::total 24 # I system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -368,7 +371,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -398,61 +401,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 7605 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 7605 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1343 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6262 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 7605 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 7605 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 7605 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6211 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12321.365320 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11473.330493 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5604.476225 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 5759 92.72% 92.72% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 412 6.63% 99.36% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 31 0.50% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.06% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 7878 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7878 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1506 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6372 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7878 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7878 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7878 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6484 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12295.265268 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11397.219739 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5676.180841 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 5980 92.23% 92.23% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 464 7.16% 99.38% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 34 0.52% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 1 0.02% 99.92% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.95% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6211 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6484 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 1125817500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 1125817500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 1125817500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 4907 79.00% 79.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1304 21.00% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6211 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7605 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5017 77.38% 77.38% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1467 22.62% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6484 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7878 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7605 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6211 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7878 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6484 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6211 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 13816 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6484 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 14362 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 22785353 # DTB read hits -system.cpu0.dtb.read_misses 6506 # DTB read misses -system.cpu0.dtb.write_hits 17536845 # DTB write hits -system.cpu0.dtb.write_misses 1099 # DTB write misses +system.cpu0.dtb.read_hits 25174501 # DTB read hits +system.cpu0.dtb.read_misses 6776 # DTB read misses +system.cpu0.dtb.write_hits 18763964 # DTB write hits +system.cpu0.dtb.write_misses 1102 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3343 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3391 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1756 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1765 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 22791859 # DTB read accesses -system.cpu0.dtb.write_accesses 17537944 # DTB write accesses +system.cpu0.dtb.read_accesses 25181277 # DTB read accesses +system.cpu0.dtb.write_accesses 18765066 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 40322198 # DTB hits -system.cpu0.dtb.misses 7605 # DTB misses -system.cpu0.dtb.accesses 40329803 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 43938465 # DTB hits +system.cpu0.dtb.misses 7878 # DTB misses +system.cpu0.dtb.accesses 43946343 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -482,7 +485,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.cpu0.itb.walker.walks 3349 # Table walker walks requested system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate @@ -491,16 +494,16 @@ system.cpu0.itb.walker.walkWaitTime::samples 3349 system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12840.762966 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 12002.591700 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5837.643760 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 347 14.87% 14.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1703 73.00% 87.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 210 9.00% 96.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 26 1.11% 97.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 42 1.80% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.09% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12613.587655 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11778.875659 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5637.639193 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 386 16.55% 16.55% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1666 71.41% 87.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 225 9.64% 97.60% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 26 1.11% 98.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 26 1.11% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.91% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::total 2333 # Table walker service (enqueue to completion) latency @@ -517,7 +520,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 5682 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 108479195 # ITB inst hits +system.cpu0.itb.inst_hits 119077538 # ITB inst hits system.cpu0.itb.inst_misses 3349 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -534,771 +537,780 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 108482544 # ITB inst accesses -system.cpu0.itb.hits 108479195 # DTB hits +system.cpu0.itb.inst_accesses 119080887 # ITB inst accesses +system.cpu0.itb.hits 119077538 # DTB hits system.cpu0.itb.misses 3349 # DTB misses -system.cpu0.itb.accesses 108482544 # DTB accesses -system.cpu0.numPwrStateTransitions 3748 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1874 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1464520585.209178 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23650117166.731750 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1082 57.74% 57.74% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 787 42.00% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.itb.accesses 119080887 # DTB accesses +system.cpu0.numPwrStateTransitions 3762 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1881 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1452265205.015417 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23608911235.366570 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1082 57.52% 57.52% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 794 42.21% 99.73% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499966342824 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1874 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 125285252318 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2744511576682 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 5739593658 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 499963656512 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1881 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 138289859366 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731710850634 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 5740001420 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1874 # number of quiesce instructions executed -system.cpu0.committedInsts 105397426 # Number of instructions committed -system.cpu0.committedOps 127063433 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 112192231 # Number of integer alu accesses +system.cpu0.kern.inst.quiesce 1881 # number of quiesce instructions executed +system.cpu0.committedInsts 115412619 # Number of instructions committed +system.cpu0.committedOps 139453859 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 123427491 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses -system.cpu0.num_func_calls 10407708 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14566669 # number of instructions that are conditional controls -system.cpu0.num_int_insts 112192231 # number of integer instructions +system.cpu0.num_func_calls 12678366 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 15706258 # number of instructions that are conditional controls +system.cpu0.num_int_insts 123427491 # number of integer instructions system.cpu0.num_fp_insts 9820 # number of float instructions -system.cpu0.num_int_register_reads 204833184 # number of times the integer registers were read -system.cpu0.num_int_register_writes 77435370 # number of times the integer registers were written +system.cpu0.num_int_register_reads 227200136 # number of times the integer registers were read +system.cpu0.num_int_register_writes 85767213 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 459130085 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 48875384 # number of times the CC registers were written -system.cpu0.num_mem_refs 41457196 # number of memory refs -system.cpu0.num_load_insts 23036367 # Number of load instructions -system.cpu0.num_store_insts 18420829 # Number of store instructions -system.cpu0.num_idle_cycles 5489023153.362087 # Number of idle cycles -system.cpu0.num_busy_cycles 250570504.637913 # Number of busy cycles -system.cpu0.not_idle_fraction 0.043656 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.956344 # Percentage of idle cycles -system.cpu0.Branches 25689353 # Number of branches fetched +system.cpu0.num_cc_register_reads 505219370 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 52317118 # number of times the CC registers were written +system.cpu0.num_mem_refs 45075192 # number of memory refs +system.cpu0.num_load_insts 25426401 # Number of load instructions +system.cpu0.num_store_insts 19648791 # Number of store instructions +system.cpu0.num_idle_cycles 5463421701.266096 # Number of idle cycles +system.cpu0.num_busy_cycles 276579718.733904 # Number of busy cycles +system.cpu0.not_idle_fraction 0.048185 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.951815 # Percentage of idle cycles +system.cpu0.Branches 29123439 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 88685820 68.09% 68.09% # Class of executed instruction -system.cpu0.op_class::IntMult 91693 0.07% 68.16% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8209 0.01% 68.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.17% # Class of executed instruction -system.cpu0.op_class::MemRead 23036367 17.69% 85.86% # Class of executed instruction -system.cpu0.op_class::MemWrite 18420829 14.14% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 98023875 68.44% 68.44% # Class of executed instruction +system.cpu0.op_class::IntMult 109907 0.08% 68.52% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8209 0.01% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::MemRead 25426401 17.75% 86.28% # Class of executed instruction +system.cpu0.op_class::MemWrite 19648791 13.72% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 130245191 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 690306 # number of replacements -system.cpu0.dcache.tags.tagsinuse 490.313655 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 39473136 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 690818 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 57.139704 # Average number of references to valid blocks. +system.cpu0.op_class::total 143219456 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 693439 # number of replacements +system.cpu0.dcache.tags.tagsinuse 491.449824 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43066582 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 693951 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 62.059975 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1151827000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 490.313655 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.957644 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.957644 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 491.449824 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.959863 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.959863 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 81317769 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 81317769 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 21536394 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 21536394 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 16814376 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 16814376 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319053 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 319053 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365550 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365550 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362389 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 362389 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 38350770 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 38350770 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 38669823 # number of overall hits -system.cpu0.dcache.overall_hits::total 38669823 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 394644 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 394644 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 324668 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 324668 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127577 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 127577 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21580 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21580 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19821 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19821 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 719312 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 719312 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 846889 # number of overall misses -system.cpu0.dcache.overall_misses::total 846889 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5059230000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5059230000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5720917500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5720917500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 328019500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 328019500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 473718500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 473718500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1421500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1421500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 10780147500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 10780147500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 10780147500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 10780147500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 21931038 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 21931038 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 17139044 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 17139044 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446630 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446630 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387130 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 387130 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382210 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 382210 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 39070082 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 39070082 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 39516712 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 39516712 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.017995 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.017995 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018943 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018943 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285644 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285644 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055744 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055744 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051859 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051859 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018411 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.018411 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021431 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.021431 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12819.731201 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12819.731201 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17620.823426 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17620.823426 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15200.162187 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15200.162187 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23899.828465 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23899.828465 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 88514427 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88514427 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 23911425 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23911425 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 18032865 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18032865 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319065 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 319065 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365782 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 365782 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362736 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 362736 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 41944290 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41944290 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 42263355 # number of overall hits +system.cpu0.dcache.overall_hits::total 42263355 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 397667 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 397667 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 324388 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 324388 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127754 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 127754 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21573 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21573 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19602 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 19602 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 722055 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 722055 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 849809 # number of overall misses +system.cpu0.dcache.overall_misses::total 849809 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5269907000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5269907000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5597938000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5597938000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 327322000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 327322000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 460475500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 460475500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1158000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1158000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 10867845000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 10867845000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 10867845000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 10867845000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 24309092 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 24309092 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 18357253 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 18357253 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446819 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446819 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387355 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 387355 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382338 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 382338 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 42666345 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42666345 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 43113164 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43113164 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016359 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.016359 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017671 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017671 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285919 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285919 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055693 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055693 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051269 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051269 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016923 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016923 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019711 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.019711 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13252.060141 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13252.060141 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17256.920725 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17256.920725 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15172.762249 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15172.762249 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23491.250893 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23491.250893 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14986.747753 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14986.747753 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12729.115032 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12729.115032 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15051.270333 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15051.270333 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12788.573668 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12788.573668 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 690306 # number of writebacks -system.cpu0.dcache.writebacks::total 690306 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25258 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25258 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14953 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14953 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 25258 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 25258 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25258 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 25258 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 369386 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 369386 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324668 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 324668 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100493 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 100493 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6627 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6627 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19821 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 19821 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 694054 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 694054 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 794547 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 794547 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 21106 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 21106 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19680 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19680 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 40786 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 40786 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4295278500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4295278500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5396249500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5396249500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1609240500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1609240500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 98443000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98443000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 453938500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 453938500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1380500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1380500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9691528000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9691528000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11300768500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11300768500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4679128000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4679128000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4679128000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4679128000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016843 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016843 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018943 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018943 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225003 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225003 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017118 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017118 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051859 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051859 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017764 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.017764 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020107 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.020107 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11628.157266 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11628.157266 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16620.823426 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16620.823426 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16013.458649 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16013.458649 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14854.836276 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14854.836276 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22901.896978 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22901.896978 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 693439 # number of writebacks +system.cpu0.dcache.writebacks::total 693439 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25271 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25271 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15260 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15260 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25271 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25271 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25271 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25271 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 372396 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 372396 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324388 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 324388 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100689 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 100689 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6313 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6313 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19602 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19602 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 696784 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 696784 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 797473 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 797473 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31786 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31786 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60249 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60249 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4503432000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4503432000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5273550000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5273550000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1615902000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1615902000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94571500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94571500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 440907500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 440907500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1124000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1124000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9776982000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9776982000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11392884000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11392884000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628627500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628627500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628627500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628627500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015319 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015319 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017671 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017671 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225346 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225346 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016298 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016298 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051269 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051269 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016331 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016331 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018497 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018497 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12093.126672 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12093.126672 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16256.920725 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16256.920725 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16048.446206 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16048.446206 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14980.437193 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14980.437193 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22492.985410 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22492.985410 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13963.651243 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13963.651243 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14222.907518 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14222.907518 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221696.579172 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221696.579172 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 114723.875840 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 114723.875840 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1101713 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.449165 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 107376961 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1102225 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 97.418368 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 14058108000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.449165 # Average occupied blocks per requestor +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14031.582241 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14031.582241 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14286.231634 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14286.231634 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208539.215378 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208539.215378 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110020.539760 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110020.539760 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1105141 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.449200 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 117971876 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1105653 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 106.698825 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 14058125000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.449200 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998924 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998924 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 218060624 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 218060624 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 107376961 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 107376961 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 107376961 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 107376961 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 107376961 # number of overall hits -system.cpu0.icache.overall_hits::total 107376961 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1102234 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1102234 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1102234 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1102234 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1102234 # number of overall misses -system.cpu0.icache.overall_misses::total 1102234 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10984481500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10984481500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10984481500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10984481500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10984481500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10984481500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 108479195 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 108479195 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 108479195 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 108479195 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 108479195 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 108479195 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010161 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.010161 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010161 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.010161 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010161 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.010161 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9965.652938 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9965.652938 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9965.652938 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9965.652938 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9965.652938 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9965.652938 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 239260738 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 239260738 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 117971876 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 117971876 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 117971876 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 117971876 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 117971876 # number of overall hits +system.cpu0.icache.overall_hits::total 117971876 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1105662 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1105662 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1105662 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1105662 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1105662 # number of overall misses +system.cpu0.icache.overall_misses::total 1105662 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11445416000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11445416000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11445416000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11445416000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11445416000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11445416000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 119077538 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 119077538 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 119077538 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 119077538 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 119077538 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 119077538 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009285 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.009285 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009285 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.009285 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009285 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.009285 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10351.640917 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10351.640917 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10351.640917 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10351.640917 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10351.640917 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10351.640917 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1101713 # number of writebacks -system.cpu0.icache.writebacks::total 1101713 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1102234 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1102234 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1102234 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1102234 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1102234 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1102234 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1105141 # number of writebacks +system.cpu0.icache.writebacks::total 1105141 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1105662 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1105662 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1105662 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1105662 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1105662 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1105662 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10433364500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10433364500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10433364500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10433364500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10433364500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10433364500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10892585000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10892585000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10892585000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10892585000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10892585000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10892585000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 811416500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 811416500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 811416500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 811416500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010161 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010161 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010161 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010161 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010161 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010161 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9465.652938 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9465.652938 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9465.652938 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9465.652938 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9465.652938 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9465.652938 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009285 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009285 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009285 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009285 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009285 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009285 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9851.640917 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9851.640917 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9851.640917 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9851.640917 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9851.640917 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9851.640917 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89937.541565 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89937.541565 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1850136 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1850170 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 29 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1836809 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1836835 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 22 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 236334 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 266149 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16069.328191 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2918942 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 282232 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 10.342350 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 235109 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 260353 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15640.705301 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1686155 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 275976 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.109789 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14514.612326 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.486543 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.157051 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1554.072270 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.885902 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000010 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.094853 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.980794 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1018 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15059 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 235 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 358 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 412 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 14471.492082 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.272651 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.132938 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1167.807630 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.883270 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000078 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.071277 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.954633 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 311 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15308 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 29 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 131 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 144 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 218 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3210 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7726 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3842 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062134 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.919128 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 59974635 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 59974635 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 9773 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4523 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 14296 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 475089 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 475089 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1289020 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1289020 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 224372 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 224372 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1057524 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1057524 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 382410 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 382410 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 9773 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4523 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1057524 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 606782 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1678602 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 9773 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4523 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1057524 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 606782 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1678602 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 217 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 146 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 363 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55553 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 55553 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19821 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 19821 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44743 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 44743 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 44710 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 44710 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94096 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 94096 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 217 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 146 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 44710 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 138839 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 183912 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 217 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 146 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 44710 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 138839 # number of overall misses -system.cpu0.l2cache.overall_misses::total 183912 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 5274500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3487000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 8761500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 99258500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 99258500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 22708000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 22708000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1319000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1319000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2047288500 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2047288500 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2385299500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2385299500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2791991500 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2791991500 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5274500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3487000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2385299500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 4839280000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 7233341000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5274500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3487000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2385299500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 4839280000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 7233341000 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 9990 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4669 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 14659 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 475089 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 475089 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 1289020 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 1289020 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55553 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 55553 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19821 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 19821 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269115 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 269115 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1102234 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 1102234 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 476506 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 476506 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 9990 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4669 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1102234 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 745621 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1862514 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 9990 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4669 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1102234 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 745621 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1862514 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021722 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.031270 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.024763 # miss rate for ReadReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 815 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6065 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6346 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1905 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018982 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.934326 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 61385527 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 61385527 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 9987 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4390 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 14377 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 478787 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 478787 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 1291925 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 1291925 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 226376 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 226376 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1043295 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1043295 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 377938 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 377938 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 9987 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4390 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1043295 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 604314 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1661986 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 9987 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4390 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1043295 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 604314 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1661986 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 261 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 141 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 402 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55107 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 55107 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19598 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 19598 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 42905 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 42905 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 62367 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 62367 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101460 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 101460 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 261 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 141 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 62367 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 144365 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 207134 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 261 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 141 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 62367 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 144365 # number of overall misses +system.cpu0.l2cache.overall_misses::total 207134 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 6301500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3315500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 9617000 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 31218000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 31218000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9500500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9500500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1071498 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1071498 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2039769000 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 2039769000 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2950382000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2950382000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3031048000 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3031048000 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 6301500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3315500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2950382000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 5070817000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 8030816000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 6301500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3315500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2950382000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 5070817000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 8030816000 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10248 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4531 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 14779 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 478787 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 478787 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 1291925 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 1291925 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55107 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 55107 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19598 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 19598 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269281 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 269281 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1105662 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 1105662 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 479398 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 479398 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10248 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4531 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1105662 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 748679 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1869120 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10248 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4531 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1105662 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 748679 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1869120 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.025468 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.031119 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.027201 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.166260 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.166260 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040563 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040563 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.197471 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.197471 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021722 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.031270 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040563 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.186206 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.098744 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021722 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.031270 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040563 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.186206 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.098744 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 24306.451613 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23883.561644 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 24136.363636 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 1786.735190 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 1786.735190 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1145.653600 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1145.653600 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 45756.621147 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45756.621147 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53350.469694 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53350.469694 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29671.734186 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29671.734186 # average ReadSharedReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 24306.451613 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23883.561644 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53350.469694 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34855.336037 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 39330.446083 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 24306.451613 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23883.561644 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53350.469694 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34855.336037 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 39330.446083 # average overall miss latency +system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.159332 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.159332 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056407 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056407 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.211640 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.211640 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.025468 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.031119 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056407 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.192826 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.110819 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.025468 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.031119 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056407 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.192826 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.110819 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 24143.678161 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23514.184397 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 23922.885572 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 566.497904 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 566.497904 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 484.768854 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 484.768854 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 267874.500000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 267874.500000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 47541.521967 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47541.521967 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 47306.780830 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 47306.780830 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29874.315001 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29874.315001 # average ReadSharedReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 24143.678161 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23514.184397 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 47306.780830 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35124.974890 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 38771.114351 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 24143.678161 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23514.184397 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 47306.780830 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35124.974890 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 38771.114351 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.unused_prefetches 11148 # number of HardPF blocks evicted w/o reference -system.cpu0.l2cache.writebacks::writebacks 227538 # number of writebacks -system.cpu0.l2cache.writebacks::total 227538 # number of writebacks -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1132 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 1132 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 31 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 31 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1163 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 1163 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1163 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 1163 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 217 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 146 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 363 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 258758 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 258758 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55553 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55553 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19821 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19821 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43611 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 43611 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 44710 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 44710 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94065 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94065 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 217 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 146 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 44710 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 137676 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 182749 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 217 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 146 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 44710 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 137676 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 258758 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 441507 # number of overall MSHR misses +system.cpu0.l2cache.unused_prefetches 10615 # number of HardPF blocks evicted w/o reference +system.cpu0.l2cache.writebacks::writebacks 227687 # number of writebacks +system.cpu0.l2cache.writebacks::total 227687 # number of writebacks +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1191 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 1191 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 30 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 30 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1221 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 1221 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1221 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 1221 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 261 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 141 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 402 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 259983 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 259983 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55107 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55107 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19598 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19598 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41714 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 41714 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 62367 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 62367 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 101430 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 101430 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 261 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 141 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 62367 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 143144 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 205913 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 261 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 141 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 62367 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 143144 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 259983 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 465896 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 21106 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 30128 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19680 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19680 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31786 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40808 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 40786 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 49808 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3972500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2611000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 6583500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13423934365 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13423934365 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1067977500 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1067977500 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 305529500 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 305529500 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1073000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1073000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1676618000 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1676618000 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2117039500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2117039500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2223147000 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2223147000 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3972500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2611000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2117039500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3899765000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 6023388000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3972500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2611000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2117039500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3899765000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13423934365 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 19447322365 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60249 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69271 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4735500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2469500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 7205000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13869294782 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13869294782 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 942789000 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 942789000 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 294087500 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 294087500 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 867498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 867498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1672104500 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1672104500 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2576180000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2576180000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2417355500 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2417355500 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4735500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2469500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2576180000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4089460000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 6672845000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4735500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2469500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2576180000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4089460000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13869294782 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 20542139782 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 743751500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4509867000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5253618500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6373927500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7117679000 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 743751500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4509867000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 5253618500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021722 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031270 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.024763 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6373927500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7117679000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.025468 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031119 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027201 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.162053 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.162053 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040563 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040563 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.197406 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.197406 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021722 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031270 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040563 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.184646 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.098120 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021722 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031270 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040563 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.184646 # mshr miss rate for overall accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.154909 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154909 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056407 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056407 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.211578 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.211578 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.025468 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031119 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056407 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191195 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110166 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.025468 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031119 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056407 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191195 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.237049 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18306.451613 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17883.561644 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 18136.363636 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51878.335607 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 51878.335607 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19224.479326 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19224.479326 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15414.434186 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15414.434186 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38444.841898 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38444.841898 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47350.469694 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47350.469694 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23634.157232 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23634.157232 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18306.451613 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17883.561644 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47350.469694 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28325.670415 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32959.895813 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18306.451613 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17883.561644 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47350.469694 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28325.670415 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51878.335607 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44047.596901 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.249260 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18143.678161 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17514.184397 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 17922.885572 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53346.929538 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53346.929538 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17108.334694 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17108.334694 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15005.995510 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15005.995510 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 216874.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 216874.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40084.971472 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40084.971472 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 41306.780830 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 41306.780830 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23832.746722 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23832.746722 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18143.678161 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17514.184397 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 41306.780830 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28568.853742 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32406.137544 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18143.678161 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17514.184397 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 41306.780830 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28568.853742 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53346.929538 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44091.685230 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 213677.011276 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174376.609798 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200526.253697 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174418.716918 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 110573.897906 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 105477.403228 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 3727432 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1879617 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 314429 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 310730 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3699 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 50409 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1677085 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19680 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19680 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 702838 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1316929 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 184068 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 307004 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 88013 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42167 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112831 # Transaction distribution +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105793.083703 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 102751.209020 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 3740310 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1886004 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27868 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 209163 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 207471 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1692 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 61471 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1694410 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28463 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28463 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 706729 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1319793 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 79890 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 307615 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 87684 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41751 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 111919 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 90 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 288284 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284624 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1102234 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 554693 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3303 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3324225 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2514874 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11068 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 23857 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5874024 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141088696 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96080240 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18676 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 39960 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 237227572 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 980964 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 18662568 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 2867653 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.124927 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.334515 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 288494 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284839 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1105662 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 565382 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3277 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3334509 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2561453 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10930 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24498 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5931390 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141527480 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96553100 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18124 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 40992 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 238139696 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 885320 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 18675332 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 2797680 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.089870 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.288103 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2513105 87.64% 87.64% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 350849 12.23% 99.87% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 3699 0.13% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2547944 91.07% 91.07% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 248044 8.87% 99.94% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1692 0.06% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2867653 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 3694518500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2797680 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 3721587498 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 114067456 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 113922479 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1662373000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1667515000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1187117482 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1206437474 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 13871990 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 14255489 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1328,68 +1340,62 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 3295 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 3295 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 621 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2674 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 3295 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 3295 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 3295 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2525 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11832.673267 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11118.852324 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 4722.323425 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-4095 1 0.04% 0.04% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-8191 600 23.76% 23.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1197 47.41% 71.21% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-16383 525 20.79% 92.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-20479 78 3.09% 95.09% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::20480-24575 55 2.18% 97.27% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-28671 34 1.35% 98.61% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::28672-32767 21 0.83% 99.45% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-36863 5 0.20% 99.64% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::36864-40959 3 0.12% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-45055 3 0.12% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::45056-49151 1 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-53247 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-61439 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2525 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -2078115828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -2078115828 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -2078115828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1912 75.72% 75.72% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 613 24.28% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2525 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3295 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 3379 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3379 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 683 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2696 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 3379 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3379 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3379 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2609 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12498.275201 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11540.409783 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5547.212388 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 616 23.61% 23.61% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1660 63.63% 87.24% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 255 9.77% 97.01% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 67 2.57% 99.58% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 5 0.19% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.11% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.08% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2609 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -2073200828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -2073200828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -2073200828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1934 74.13% 74.13% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 675 25.87% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2609 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3379 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3295 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2525 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3379 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2609 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2525 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 5820 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2609 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5988 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6294037 # DTB read hits -system.cpu1.dtb.read_misses 2780 # DTB read misses -system.cpu1.dtb.write_hits 4620410 # DTB write hits -system.cpu1.dtb.write_misses 515 # DTB write misses +system.cpu1.dtb.read_hits 3943912 # DTB read hits +system.cpu1.dtb.read_misses 2863 # DTB read misses +system.cpu1.dtb.write_hits 3421052 # DTB write hits +system.cpu1.dtb.write_misses 516 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1950 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1981 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 345 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 312 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6296817 # DTB read accesses -system.cpu1.dtb.write_accesses 4620925 # DTB write accesses +system.cpu1.dtb.read_accesses 3946775 # DTB read accesses +system.cpu1.dtb.write_accesses 3421568 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 10914447 # DTB hits -system.cpu1.dtb.misses 3295 # DTB misses -system.cpu1.dtb.accesses 10917742 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 7364964 # DTB hits +system.cpu1.dtb.misses 3379 # DTB misses +system.cpu1.dtb.accesses 7368343 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1419,7 +1425,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 1746 # Table walker walks requested system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate @@ -1428,25 +1434,24 @@ system.cpu1.itb.walker.walkWaitTime::samples 1746 system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12387.082204 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11535.325922 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5801.640137 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 173 15.63% 15.63% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 662 59.80% 75.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 167 15.09% 90.51% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 48 4.34% 94.85% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.18% 95.03% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 22 1.99% 97.02% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 9 0.81% 97.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.18% 98.01% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 17 1.54% 99.55% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 13079.042457 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 12148.751119 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5740.258970 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 165 14.91% 14.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 593 53.57% 68.47% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 181 16.35% 84.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 52 4.70% 89.52% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 63 5.69% 95.21% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 26 2.35% 97.56% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 1.54% 99.10% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 99.37% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 4 0.36% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.18% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -2078939828 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -2078939828 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -2078939828 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::samples -2073744828 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -2073744828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -2073744828 # Table walker pending requests distribution system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated @@ -1457,7 +1462,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 27022574 # ITB inst hits +system.cpu1.itb.inst_hits 16566340 # ITB inst hits system.cpu1.itb.inst_misses 1746 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1474,658 +1479,656 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 27024320 # ITB inst accesses -system.cpu1.itb.hits 27022574 # DTB hits +system.cpu1.itb.inst_accesses 16568086 # ITB inst accesses +system.cpu1.itb.hits 16566340 # DTB hits system.cpu1.itb.misses 1746 # DTB misses -system.cpu1.itb.accesses 27024320 # DTB accesses -system.cpu1.numPwrStateTransitions 5545 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2773 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1021169708.427335 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25639051633.019150 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1969 71.01% 71.01% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 798 28.78% 99.78% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.itb.accesses 16568086 # DTB accesses +system.cpu1.numPwrStateTransitions 5497 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2749 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1034540641.602037 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25769735768.471432 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1960 71.30% 71.30% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 783 28.48% 99.78% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 929980591792 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2773 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 38093227531 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2831703601469 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 5738665817 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 929980464320 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2749 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 26048486236 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2843952223764 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 5739069639 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2773 # number of quiesce instructions executed -system.cpu1.committedInsts 26084833 # Number of instructions committed -system.cpu1.committedOps 31969643 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 28891717 # Number of integer alu accesses +system.cpu1.kern.inst.quiesce 2749 # number of quiesce instructions executed +system.cpu1.committedInsts 16210815 # Number of instructions committed +system.cpu1.committedOps 19752329 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 17813732 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses -system.cpu1.num_func_calls 3291352 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2940246 # number of instructions that are conditional controls -system.cpu1.num_int_insts 28891717 # number of integer instructions +system.cpu1.num_func_calls 1029438 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1815045 # number of instructions that are conditional controls +system.cpu1.num_int_insts 17813732 # number of integer instructions system.cpu1.num_fp_insts 1857 # number of float instructions -system.cpu1.num_int_register_reads 54405566 # number of times the integer registers were read -system.cpu1.num_int_register_writes 20702345 # number of times the integer registers were written +system.cpu1.num_int_register_reads 32326512 # number of times the integer registers were read +system.cpu1.num_int_register_writes 12493939 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 117659728 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 9804030 # number of times the CC registers were written -system.cpu1.num_mem_refs 11150743 # number of memory refs -system.cpu1.num_load_insts 6405542 # Number of load instructions -system.cpu1.num_store_insts 4745201 # Number of store instructions -system.cpu1.num_idle_cycles 5662491677.952167 # Number of idle cycles -system.cpu1.num_busy_cycles 76174139.047833 # Number of busy cycles -system.cpu1.not_idle_fraction 0.013274 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.986726 # Percentage of idle cycles -system.cpu1.Branches 6334050 # Number of branches fetched +system.cpu1.num_cc_register_reads 72207765 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 6423893 # number of times the CC registers were written +system.cpu1.num_mem_refs 7598514 # number of memory refs +system.cpu1.num_load_insts 4055507 # Number of load instructions +system.cpu1.num_store_insts 3543007 # Number of store instructions +system.cpu1.num_idle_cycles 5686981123.489185 # Number of idle cycles +system.cpu1.num_busy_cycles 52088515.510815 # Number of busy cycles +system.cpu1.not_idle_fraction 0.009076 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.990924 # Percentage of idle cycles +system.cpu1.Branches 2922923 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 21707276 65.97% 65.97% # Class of executed instruction -system.cpu1.op_class::IntMult 42869 0.13% 66.10% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3317 0.01% 66.11% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 66.11% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 66.11% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 66.11% # Class of executed instruction -system.cpu1.op_class::MemRead 6405542 19.47% 85.58% # Class of executed instruction -system.cpu1.op_class::MemWrite 4745201 14.42% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 12474914 62.05% 62.05% # Class of executed instruction +system.cpu1.op_class::IntMult 26468 0.13% 62.19% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3329 0.02% 62.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.20% # Class of executed instruction +system.cpu1.op_class::MemRead 4055507 20.17% 82.38% # Class of executed instruction +system.cpu1.op_class::MemWrite 3543007 17.62% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 32904271 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 184968 # number of replacements -system.cpu1.dcache.tags.tagsinuse 463.748200 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 10628914 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 185317 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 57.355310 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 117456056000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 463.748200 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.905758 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.905758 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 279 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 70 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.681641 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 22007267 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 22007267 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 5972632 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 5972632 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4424329 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4424329 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48799 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 48799 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78725 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78725 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70549 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70549 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 10396961 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 10396961 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 10445760 # number of overall hits -system.cpu1.dcache.overall_hits::total 10445760 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 132851 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 132851 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 90720 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 90720 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30243 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30243 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17042 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17042 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23391 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23391 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 223571 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 223571 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 253814 # number of overall misses -system.cpu1.dcache.overall_misses::total 253814 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1953731000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1953731000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2328640500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2328640500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317134000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 317134000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 572176500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 572176500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2893000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2893000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4282371500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4282371500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4282371500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4282371500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 6105483 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 6105483 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4515049 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4515049 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79042 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79042 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95767 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 95767 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93940 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 93940 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 10620532 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 10620532 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 10699574 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 10699574 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.021759 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.021759 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.020093 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.020093 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382619 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382619 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177953 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177953 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248999 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248999 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.021051 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.021051 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.023722 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.023722 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14706.182114 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14706.182114 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25668.435847 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25668.435847 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18608.966084 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18608.966084 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24461.395408 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24461.395408 # average StoreCondReq miss latency +system.cpu1.op_class::total 20103291 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 186972 # number of replacements +system.cpu1.dcache.tags.tagsinuse 469.131643 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 7097155 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 187306 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 37.890698 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 127531940000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.131643 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916273 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.916273 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 334 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 255 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 79 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.652344 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 14948788 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14948788 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 3631994 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3631994 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3232351 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3232351 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48894 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 48894 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78959 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 78959 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70892 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 70892 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 6864345 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6864345 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 6913239 # number of overall hits +system.cpu1.dcache.overall_hits::total 6913239 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 133677 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 133677 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 91948 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 91948 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30343 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30343 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16973 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16973 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23209 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23209 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 225625 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 225625 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 255968 # number of overall misses +system.cpu1.dcache.overall_misses::total 255968 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2021367000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2021367000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2373794500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2373794500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317489000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 317489000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544203500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 544203500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1998500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1998500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4395161500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4395161500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4395161500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4395161500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3765671 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3765671 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3324299 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3324299 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79237 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79237 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95932 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 95932 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94101 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94101 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 7089970 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 7089970 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 7169207 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7169207 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035499 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035499 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027659 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027659 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382940 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382940 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.176927 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.176927 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246639 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246639 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031823 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031823 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035704 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035704 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15121.277407 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15121.277407 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25816.706182 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 25816.706182 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18705.532316 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18705.532316 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23447.951226 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23447.951226 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19154.414034 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19154.414034 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16872.085464 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16872.085464 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19479.940166 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19479.940166 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17170.745953 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17170.745953 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 184968 # number of writebacks -system.cpu1.dcache.writebacks::total 184968 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 261 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 261 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11955 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11955 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 261 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 261 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 261 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 261 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 132590 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 132590 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90720 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 90720 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29532 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29532 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5087 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5087 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23391 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23391 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 223310 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 223310 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 252842 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 252842 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 13772 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 13772 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11224 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11224 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 24996 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 24996 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1815324500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1815324500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2237920500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2237920500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 484982000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 484982000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 85050000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 85050000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 548834500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 548834500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2844000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2844000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4053245000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4053245000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4538227000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4538227000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2392670000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2392670000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2392670000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2392670000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.021717 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.021717 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.020093 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.020093 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.373624 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.373624 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053119 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053119 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248999 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248999 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.021026 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.021026 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.023631 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.023631 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13691.262539 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13691.262539 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24668.435847 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24668.435847 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16422.253826 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16422.253826 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16719.087871 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16719.087871 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23463.490231 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23463.490231 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 186972 # number of writebacks +system.cpu1.dcache.writebacks::total 186972 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 283 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 283 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12048 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12048 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 283 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 283 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 283 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 283 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133394 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 133394 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91948 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 91948 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29641 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29641 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4925 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4925 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23209 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23209 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 225342 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 225342 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 254983 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 254983 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3099 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3099 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2450 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5549 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5549 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1881488500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1881488500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2281846500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2281846500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 500338500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 500338500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 85063000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 85063000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521039500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521039500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1953500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1953500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4163335000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4163335000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4663673500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4663673500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443787500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443787500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443787500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443787500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035424 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035424 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027659 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027659 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.374080 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.374080 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051338 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051338 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246639 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246639 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031783 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031783 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035566 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035566 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14104.746091 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14104.746091 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24816.706182 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24816.706182 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16879.946695 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16879.946695 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17271.675127 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17271.675127 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22449.890129 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22449.890129 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18150.754556 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18150.754556 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17948.865299 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17948.865299 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173734.388615 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173734.388615 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95722.115538 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95722.115538 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 504074 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.478768 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 26517983 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 504586 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 52.553941 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 85269939000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.478768 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973591 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973591 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18475.628156 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18475.628156 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18290.135029 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18290.135029 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143203.452727 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143203.452727 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79976.121824 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79976.121824 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 505656 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.477037 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 16060167 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 506168 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 31.728926 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 85274966000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.477037 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973588 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973588 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 54549724 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 54549724 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 26517983 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 26517983 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 26517983 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 26517983 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 26517983 # number of overall hits -system.cpu1.icache.overall_hits::total 26517983 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 504586 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 504586 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 504586 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 504586 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 504586 # number of overall misses -system.cpu1.icache.overall_misses::total 504586 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4509196500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4509196500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4509196500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4509196500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4509196500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4509196500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 27022569 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 27022569 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 27022569 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 27022569 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 27022569 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 27022569 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018673 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.018673 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018673 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.018673 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018673 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.018673 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8936.428082 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8936.428082 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8936.428082 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8936.428082 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8936.428082 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8936.428082 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 33638838 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 33638838 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 16060167 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 16060167 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 16060167 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 16060167 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 16060167 # number of overall hits +system.cpu1.icache.overall_hits::total 16060167 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 506168 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 506168 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 506168 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 506168 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 506168 # number of overall misses +system.cpu1.icache.overall_misses::total 506168 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4710776500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4710776500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4710776500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4710776500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4710776500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4710776500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 16566335 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 16566335 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 16566335 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 16566335 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 16566335 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 16566335 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030554 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.030554 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030554 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.030554 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030554 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.030554 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9306.744994 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9306.744994 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9306.744994 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9306.744994 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9306.744994 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9306.744994 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 504074 # number of writebacks -system.cpu1.icache.writebacks::total 504074 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 504586 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 504586 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 504586 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 504586 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 504586 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 504586 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 505656 # number of writebacks +system.cpu1.icache.writebacks::total 505656 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 506168 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 506168 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 506168 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 506168 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 506168 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 506168 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4256903500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4256903500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4256903500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4256903500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4256903500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4256903500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15776500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15776500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15776500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 15776500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018673 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018673 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018673 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.018673 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018673 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.018673 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8436.428082 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8436.428082 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8436.428082 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8436.428082 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8436.428082 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8436.428082 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89132.768362 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89132.768362 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 194200 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 194208 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4457692500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4457692500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4457692500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4457692500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4457692500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4457692500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15627500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15627500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15627500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 15627500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030554 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030554 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030554 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.030554 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030554 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.030554 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8806.744994 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8806.744994 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8806.744994 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8806.744994 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8806.744994 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8806.744994 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88290.960452 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 88290.960452 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88290.960452 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 88290.960452 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 198543 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 198543 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 58064 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 39025 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14524.719643 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1158959 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 53669 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 21.594570 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 58537 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 43670 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14604.323800 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 603874 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 58010 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 10.409826 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14059.725770 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 5.138677 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.073426 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 457.781770 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.858138 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000314 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.027941 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.886519 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1036 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13588 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 48 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 987 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14211.070638 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.100990 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.057181 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 388.094990 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.867375 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000189 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000126 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.023687 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.891377 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 327 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14000 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 23 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 304 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1629 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11648 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.063232 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001221 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.829346 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 23678541 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 23678541 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3677 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1997 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 5674 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 113054 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 113054 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 564912 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 564912 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27115 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 27115 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 491676 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 491676 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 100094 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 100094 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3677 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1997 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 491676 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 127209 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 624559 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3677 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1997 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 491676 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 127209 # number of overall hits -system.cpu1.l2cache.overall_hits::total 624559 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 321 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 267 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 588 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29273 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29273 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23388 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23388 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34332 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 34332 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 12910 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 12910 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 67115 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 67115 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 321 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 267 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 12910 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 101447 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 114945 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 321 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 267 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 12910 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 101447 # number of overall misses -system.cpu1.l2cache.overall_misses::total 114945 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6521000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5470500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 11991500 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 64762500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 64762500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 33901000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 33901000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2768998 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2768998 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1261050000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1261050000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 523740500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 523740500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1479063500 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1479063500 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6521000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5470500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 523740500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2740113500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3275845500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6521000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5470500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 523740500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 2740113500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3275845500 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3998 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2264 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 6262 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 113054 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 113054 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 564912 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 564912 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29273 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29273 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23388 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23388 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61447 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 61447 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 504586 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 504586 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 167209 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 167209 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3998 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2264 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 504586 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 228656 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 739504 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3998 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2264 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 504586 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 228656 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 739504 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.080290 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.117933 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.093900 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 895 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2815 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10290 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.019958 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.854492 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 24332814 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 24332814 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3764 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1983 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 5747 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 114262 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 114262 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 567214 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 567214 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27479 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 27479 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 484841 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 484841 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 98007 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 98007 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3764 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1983 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 484841 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 125486 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 616074 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3764 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1983 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 484841 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 125486 # number of overall hits +system.cpu1.l2cache.overall_hits::total 616074 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 441 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 340 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 781 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29645 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 29645 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23207 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 23207 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34824 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 34824 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21327 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 21327 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69953 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 69953 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 441 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 340 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 21327 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 104777 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 126885 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 441 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 340 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 21327 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 104777 # number of overall misses +system.cpu1.l2cache.overall_misses::total 126885 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9030000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6837500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 15867500 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 14606500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 14606500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 16450500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 16450500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1885500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1885500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1331294000 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1331294000 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 775115000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 775115000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1573819000 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1573819000 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9030000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6837500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 775115000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 2905113000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 3696095500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9030000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6837500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 775115000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 2905113000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 3696095500 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 4205 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2323 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 6528 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114262 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 114262 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 567214 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 567214 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29645 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 29645 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23207 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23207 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62303 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 62303 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 506168 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 506168 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 167960 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 167960 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 4205 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2323 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 506168 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 230263 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 742959 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 4205 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2323 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 506168 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 230263 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 742959 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.104875 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.146362 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.119638 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.558725 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.558725 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025585 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025585 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.401384 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.401384 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.080290 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.117933 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025585 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.443666 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.155435 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.080290 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.117933 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025585 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.443666 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.155435 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20314.641745 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20488.764045 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20393.707483 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2212.362928 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2212.362928 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1449.504019 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1449.504019 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 922999.333333 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 922999.333333 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 36731.038099 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 36731.038099 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40568.590240 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40568.590240 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22037.748640 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22037.748640 # average ReadSharedReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20314.641745 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20488.764045 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40568.590240 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27010.296017 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 28499.243116 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20314.641745 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20488.764045 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40568.590240 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27010.296017 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 28499.243116 # average overall miss latency +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.558946 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.558946 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.042134 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.042134 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.416486 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.416486 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.104875 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.146362 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.042134 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.455032 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.170783 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.104875 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.146362 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.042134 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.455032 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.170783 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20476.190476 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20110.294118 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20316.901408 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 492.713780 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 492.713780 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 708.859396 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 708.859396 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 942750 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 942750 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38229.209740 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38229.209740 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36344.305341 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36344.305341 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22498.234529 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22498.234529 # average ReadSharedReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20476.190476 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20110.294118 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36344.305341 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27726.628936 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 29129.491272 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20476.190476 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20110.294118 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36344.305341 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27726.628936 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 29129.491272 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.unused_prefetches 741 # number of HardPF blocks evicted w/o reference -system.cpu1.l2cache.writebacks::writebacks 28109 # number of writebacks -system.cpu1.l2cache.writebacks::total 28109 # number of writebacks -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 75 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 75 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 75 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 75 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 321 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 267 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 23341 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 23341 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29273 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29273 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23388 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23388 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34257 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 34257 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 12910 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 12910 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 67115 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 67115 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 321 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 267 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 12910 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 101372 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 114870 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 321 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 267 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 12910 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 101372 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 23341 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 138211 # number of overall MSHR misses +system.cpu1.l2cache.unused_prefetches 787 # number of HardPF blocks evicted w/o reference +system.cpu1.l2cache.writebacks::writebacks 33133 # number of writebacks +system.cpu1.l2cache.writebacks::total 33133 # number of writebacks +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 84 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 84 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 84 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 84 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 84 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 441 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 340 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 781 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25691 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 25691 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29645 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29645 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23207 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23207 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34740 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 34740 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 21327 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 21327 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69953 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69953 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 441 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 340 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 21327 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104693 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 126801 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 441 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 340 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 21327 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104693 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25691 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 152492 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 13772 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 13949 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11224 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11224 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3099 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3276 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2450 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 24996 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 25173 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4595000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3868500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 8463500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 732704788 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 732704788 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 486199500 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 486199500 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 373432500 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 373432500 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2474998 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2474998 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1046225500 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1046225500 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 446280500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 446280500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1076373500 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1076373500 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4595000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3868500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 446280500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2122599000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2577343000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4595000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3868500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 446280500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2122599000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 732704788 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 3310047788 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14449000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2282145500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2296594500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14449000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2282145500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2296594500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.080290 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.117933 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.093900 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5549 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5726 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6384000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4797500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 11181500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 812147618 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 812147618 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 453420500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 453420500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 346968500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 346968500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1615500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1615500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1114497500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1114497500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 647153000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 647153000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1154101000 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1154101000 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6384000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4797500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 647153000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2268598500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2926933000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6384000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4797500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 647153000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2268598500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 812147618 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 3739080618 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14300000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418649000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 432949000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14300000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418649000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 432949000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.104875 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.146362 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.119638 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses @@ -2134,123 +2137,123 @@ system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.557505 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.557505 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.025585 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.025585 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.401384 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.401384 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.080290 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.117933 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.025585 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443338 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.155334 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.080290 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.117933 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.025585 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443338 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.557598 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.557598 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.042134 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042134 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.416486 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.416486 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.104875 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.146362 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.042134 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454667 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.170670 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.104875 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.146362 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.042134 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454667 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186897 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14314.641745 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14488.764045 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14393.707483 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31391.319481 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31391.319481 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16609.144946 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16609.144946 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15966.841970 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15966.841970 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 824999.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 824999.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30540.488075 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30540.488075 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34568.590240 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34568.590240 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16037.748640 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16037.748640 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14314.641745 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14488.764045 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34568.590240 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 20938.710887 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22437.041873 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14314.641745 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14488.764045 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34568.590240 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 20938.710887 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31391.319481 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23949.235502 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81632.768362 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165709.083648 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164642.232418 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81632.768362 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91300.428068 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91232.451436 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 1481374 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 748184 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11076 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 177406 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 174791 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2615 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 23242 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 733434 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11224 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11224 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 142093 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 575988 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 98729 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 27772 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 72921 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41250 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85602 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 90 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 69150 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 66171 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 504586 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 246891 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 241 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1513600 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 873749 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5588 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9967 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2402904 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64554948 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29333690 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9056 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 15992 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 93913686 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 383897 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 4632988 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1125089 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.175565 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.386511 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.205250 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14476.190476 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14110.294118 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14316.901408 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31612.145031 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31612.145031 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15295.007590 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15295.007590 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14951.027707 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14951.027707 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 807750 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 807750 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32081.102476 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32081.102476 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30344.305341 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30344.305341 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16498.234529 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16498.234529 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14476.190476 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14110.294118 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30344.305341 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21669.056193 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23082.885782 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14476.190476 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14110.294118 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30344.305341 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21669.056193 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31612.145031 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24519.847717 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 80790.960452 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135091.642465 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132157.814408 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 80790.960452 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75445.846098 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75611.072302 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 1488311 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 751924 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11152 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 112911 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104591 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8320 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 12675 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 724258 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2450 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2450 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 148574 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 578366 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 28228 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 30717 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 71065 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40939 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85439 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 36 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 69452 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66978 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 506168 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 262948 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1518346 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 839098 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5647 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10280 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2373371 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64757444 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29422876 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9292 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16820 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 94206432 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 332481 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 4905948 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1059226 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.131024 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.359953 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 930178 82.68% 82.68% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 192296 17.09% 99.77% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 2615 0.23% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 928762 87.68% 87.68% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 122144 11.53% 99.21% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 8320 0.79% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1125089 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1449361998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1059226 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1442372000 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 81273182 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79594348 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 757056000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 759429000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 388749000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 376190500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 5969499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 6075998 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 31015 # Transaction distribution system.iobus.trans_dist::ReadResp 31015 # Transaction distribution -system.iobus.trans_dist::WriteReq 59421 # Transaction distribution -system.iobus.trans_dist::WriteResp 59421 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 59422 # Transaction distribution +system.iobus.trans_dist::WriteResp 59422 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -2269,11 +2272,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180872 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -2292,33 +2295,33 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484066 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48725500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48721500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 106000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 323500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 321000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 94500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 94000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 599000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 622500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 23000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 48000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) @@ -2330,32 +2333,32 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6153000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6160000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 32045500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 32045000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187736829 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187728827 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36445 # number of replacements -system.iocache.tags.tagsinuse 14.386581 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.386151 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 289188615000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.386581 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.899161 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.899161 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 289285136000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.386151 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.899134 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.899134 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328311 # Number of tag accesses system.iocache.tags.data_accesses 328311 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -2364,14 +2367,14 @@ system.iocache.demand_misses::realview.ide 36479 # system.iocache.demand_misses::total 36479 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36479 # number of overall misses system.iocache.overall_misses::total 36479 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 35445377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 35445377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4303608452 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4303608452 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4339053829 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4339053829 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4339053829 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4339053829 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 34821377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 34821377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4306604450 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4306604450 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4341425827 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4341425827 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4341425827 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4341425827 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2388,19 +2391,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 139001.478431 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 139001.478431 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118805.445340 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118805.445340 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118946.622139 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118946.622139 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118946.622139 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118946.622139 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 136554.419608 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 136554.419608 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118888.152882 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118888.152882 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 119011.645796 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119011.645796 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 119011.645796 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119011.645796 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 3.750000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks @@ -2412,14 +2415,14 @@ system.iocache.demand_mshr_misses::realview.ide 36479 system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 22695377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 22695377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2490051224 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2490051224 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2512746601 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2512746601 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2512746601 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2512746601 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 22071377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 22071377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2493082245 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2493082245 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2515153622 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2515153622 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2515153622 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2515153622 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2428,566 +2431,591 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 89001.478431 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 89001.478431 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68740.371687 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68740.371687 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68882.003372 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68882.003372 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68882.003372 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68882.003372 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 119266 # number of replacements -system.l2c.tags.tagsinuse 63150.928665 # Cycle average of tags in use -system.l2c.tags.total_refs 419498 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 183131 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.290699 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13441.811145 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.006326 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.055729 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7581.242495 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2905.326286 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35913.296254 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1514.615308 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 303.672578 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1486.902543 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.205106 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 86554.419608 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 86554.419608 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68824.046074 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68824.046074 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68947.987116 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68947.987116 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68947.987116 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68947.987116 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 137913 # number of replacements +system.l2c.tags.tagsinuse 65077.078827 # Cycle average of tags in use +system.l2c.tags.total_refs 526584 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 203352 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.589520 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 102405123000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 6467.156176 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.052663 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.040623 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7119.410088 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6998.473757 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37485.432069 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.004586 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1431.375532 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3211.021288 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2361.112045 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.098681 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000047 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.115681 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.044332 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.547993 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.023111 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.004634 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022688 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.963607 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 30886 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 32974 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 76 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4718 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 26088 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2232 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 30425 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.471283 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.503143 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5778594 # Number of tag accesses -system.l2c.tags.data_accesses 5778594 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 255647 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 255647 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 32152 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2169 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 34321 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2017 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 1011 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3028 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4187 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1790 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5977 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 77 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 85 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 27265 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 45372 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46765 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 37 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 32 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 10614 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 8420 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 4646 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 143313 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 77 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 85 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 27265 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 49559 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 46765 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 37 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 32 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 10614 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 10210 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 4646 # number of demand (read+write) hits -system.l2c.demand_hits::total 149290 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 77 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 85 # number of overall hits -system.l2c.overall_hits::cpu0.inst 27265 # number of overall hits -system.l2c.overall_hits::cpu0.data 49559 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 46765 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 37 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 32 # number of overall hits -system.l2c.overall_hits::cpu1.inst 10614 # number of overall hits -system.l2c.overall_hits::cpu1.data 10210 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 4646 # number of overall hits -system.l2c.overall_hits::total 149290 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 8829 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2766 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11595 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 562 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1350 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1912 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 10910 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7277 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 18187 # number of ReadExReq misses +system.l2c.tags.occ_percent::cpu0.inst 0.108634 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.106788 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.571982 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.021841 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.048996 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.036028 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.992997 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 34227 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 31208 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 194 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4904 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 29129 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1170 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 29939 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.522263 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.476196 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6120881 # Number of tag accesses +system.l2c.tags.data_accesses 6120881 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 260820 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 260820 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 40104 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 5060 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 45164 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2347 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 2252 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 4599 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4026 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1389 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5415 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 108 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 71 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 44456 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 52767 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45168 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 38 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 27 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 18981 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 11141 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5391 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 178148 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 108 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 71 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 44456 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 56793 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 45168 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 38 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 27 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 18981 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 12530 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 5391 # number of demand (read+write) hits +system.l2c.demand_hits::total 183563 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 108 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 71 # number of overall hits +system.l2c.overall_hits::cpu0.inst 44456 # number of overall hits +system.l2c.overall_hits::cpu0.data 56793 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 45168 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 38 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 27 # number of overall hits +system.l2c.overall_hits::cpu1.inst 18981 # number of overall hits +system.l2c.overall_hits::cpu1.data 12530 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 5391 # number of overall hits +system.l2c.overall_hits::total 183563 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 439 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 262 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 701 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 134 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 80 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 214 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11600 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8098 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 19698 # number of ReadExReq misses system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 17445 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 8731 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 130401 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 2296 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 718 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5545 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 165145 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 17911 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 9058 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134486 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 2346 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 949 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6189 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 170949 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 17445 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 19641 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 130401 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2296 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 7995 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 5545 # number of demand (read+write) misses -system.l2c.demand_misses::total 183332 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 17911 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 20658 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 134486 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2346 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 9047 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 6189 # number of demand (read+write) misses +system.l2c.demand_misses::total 190647 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 17445 # number of overall misses -system.l2c.overall_misses::cpu0.data 19641 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 130401 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2296 # number of overall misses -system.l2c.overall_misses::cpu1.data 7995 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 5545 # number of overall misses -system.l2c.overall_misses::total 183332 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 14927000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 2436000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 17363000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1977500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1602000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3579500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 1046073500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 591480500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1637554000 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 605500 # number of ReadSharedReq miss cycles +system.l2c.overall_misses::cpu0.inst 17911 # number of overall misses +system.l2c.overall_misses::cpu0.data 20658 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 134486 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2346 # number of overall misses +system.l2c.overall_misses::cpu1.data 9047 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 6189 # number of overall misses +system.l2c.overall_misses::total 190647 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 8533000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 947500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 9480500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 549000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 243000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 792000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 1114115000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 666355000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1780470000 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 613500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 174000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1424566500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 766776000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 12582000643 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 188965500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 64274000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 624236555 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 15651598698 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 605500 # number of demand (read+write) miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1475165500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 798074000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 13067739073 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 89500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 196303000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 84484000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 694399123 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 16317041696 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 613500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 174000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1424566500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1812849500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12582000643 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 188965500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 655754500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 624236555 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 17289152698 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 605500 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1475165500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1912189000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13067739073 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 89500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 196303000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 750839000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 694399123 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 18097511696 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 613500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 174000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1424566500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1812849500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12582000643 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 188965500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 655754500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 624236555 # number of overall miss cycles -system.l2c.overall_miss_latency::total 17289152698 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 255647 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 255647 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 40981 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4935 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 45916 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2579 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 2361 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 4940 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 15097 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 9067 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 24164 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 84 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 87 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 44710 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 54103 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 177166 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 37 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 32 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 12910 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 9138 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 10191 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 308458 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 84 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 87 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 44710 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 69200 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 177166 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 37 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 32 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 12910 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 18205 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 10191 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 332622 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 84 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 87 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 44710 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 69200 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 177166 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 37 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 32 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 12910 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 18205 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 10191 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 332622 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.215441 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.560486 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.252526 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.217914 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.571792 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.387045 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.722660 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.802581 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.752649 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.083333 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.022989 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.390181 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.161377 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.736039 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.177847 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.078573 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.544108 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.535389 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.083333 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.022989 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.390181 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.283829 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.736039 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.177847 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.439165 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.544108 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.551172 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.083333 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.022989 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.390181 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.283829 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.736039 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.177847 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.439165 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.544108 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.551172 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1690.678446 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 880.694143 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1497.455800 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3518.683274 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1186.666667 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1872.123431 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 95882.080660 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81280.816270 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 90039.808655 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 86500 # average ReadSharedReq miss latency +system.l2c.overall_miss_latency::cpu0.inst 1475165500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1912189000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13067739073 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 89500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 196303000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 750839000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 694399123 # number of overall miss cycles +system.l2c.overall_miss_latency::total 18097511696 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 260820 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 260820 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 40543 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5322 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 45865 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 2481 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 2332 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 4813 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 15626 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 9487 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 25113 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 115 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 73 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 62367 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 61825 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179654 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 39 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 27 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 21327 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 12090 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11580 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 349097 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 115 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 73 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 62367 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 77451 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179654 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 39 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 27 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 21327 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 21577 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11580 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 374210 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 115 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 73 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 62367 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 77451 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179654 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 39 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 27 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 21327 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 21577 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11580 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 374210 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.010828 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.049230 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.015284 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.054010 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.034305 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.044463 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.742352 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.853589 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.784375 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.060870 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.027397 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.287187 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.146510 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.748583 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.025641 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.110001 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.078495 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.534456 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.489689 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.060870 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.027397 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.287187 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.266723 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.748583 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.025641 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.110001 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.419289 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.534456 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.509465 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.060870 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.027397 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.287187 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.266723 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.748583 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.025641 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.110001 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.419289 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.534456 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.509465 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 19437.357631 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3616.412214 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 13524.251070 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4097.014925 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 3037.500000 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3700.934579 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 96044.396552 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82286.367004 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 90388.364301 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 87642.857143 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 87000 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 81660.447120 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87822.242584 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96486.995061 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82302.047038 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89518.105850 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 112576.475203 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 94774.886905 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86500 # average overall miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 82360.867623 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88107.087657 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 97168.025467 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 83675.618073 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89024.236038 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 112198.921150 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 95449.763941 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87642.857143 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 81660.447120 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 92299.246474 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96486.995061 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 82302.047038 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 82020.575360 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 112576.475203 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 94305.155117 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 82360.867623 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 92564.091393 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 97168.025467 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 83675.618073 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 82993.146900 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 112198.921150 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 94926.810786 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87642.857143 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 81660.447120 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 92299.246474 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96486.995061 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 82302.047038 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 82020.575360 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 112576.475203 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 94305.155117 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.overall_avg_miss_latency::cpu0.inst 82360.867623 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 92564.091393 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 97168.025467 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 83675.618073 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 82993.146900 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 112198.921150 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 94926.810786 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 12 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 94207 # number of writebacks -system.l2c.writebacks::total 94207 # number of writebacks -system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 8 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 8 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 16 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 16 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 2843 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 2843 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 8829 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 2766 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11595 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 562 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1350 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1912 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 10910 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 7277 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 18187 # number of ReadExReq MSHR misses +system.l2c.writebacks::writebacks 101139 # number of writebacks +system.l2c.writebacks::total 101139 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 1 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 5 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 6 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 3904 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 3904 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 439 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 262 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 701 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 134 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 80 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 214 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 11600 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 8098 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 19698 # number of ReadExReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17437 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8731 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 130401 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2288 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 718 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5545 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 165129 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17910 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9058 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134486 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2341 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 949 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6189 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 170943 # number of ReadSharedReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 17437 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 19641 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 130401 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2288 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 7995 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5545 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 183316 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 17910 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 20658 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134486 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2341 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 9047 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6189 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 190641 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 17437 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 19641 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 130401 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2288 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 7995 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5545 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 183316 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 17910 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 20658 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134486 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2341 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 9047 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6189 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 190641 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 21106 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31786 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 13769 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 44074 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19680 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11224 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 30904 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3096 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 44081 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 30913 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 40786 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60249 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 24993 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 74978 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 211257500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 63038000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 274295500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 14501000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 33544500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 48045500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 936973500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 518710500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1455684000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 535500 # number of ReadSharedReq MSHR miss cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5546 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 74994 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 10668500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5960000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 16628500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3486500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1878000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 5364500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 998115000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 585374501 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1583489501 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 543500 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 154000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1249680003 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 679466000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11277986652 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 165660000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 57094000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 568784560 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 13999360715 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 535500 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1296016500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 707494000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11722877577 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 79500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 172535500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 74994000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 632508125 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 14607202702 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 543500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 154000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1249680003 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 1616439500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11277986652 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 165660000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 575804500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 568784560 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 15455044715 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 535500 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1296016500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1705609000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11722877577 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 79500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 172535500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 660368501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 632508125 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16190692203 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 543500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 154000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1249680003 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 1616439500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11277986652 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 165660000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 575804500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 568784560 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 15455044715 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1296016500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1705609000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11722877577 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 79500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 172535500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 660368501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 632508125 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16190692203 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 581355000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4129945000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11263000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2034246500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6756809500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801764501 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11113500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362869500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6757102501 # number of ReadReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 581355000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4129945000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11263000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2034246500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 6756809500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5801764501 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11113500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362869500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6757102501 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.215441 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.560486 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.252526 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.217914 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.571792 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.387045 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.722660 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.802581 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.752649 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.083333 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.022989 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.390002 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.161377 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736039 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.177227 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078573 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.544108 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.535337 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.083333 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.022989 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.390002 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.283829 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736039 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.177227 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.439165 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.544108 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.551124 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.083333 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.022989 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.390002 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.283829 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736039 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.177227 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.439165 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.544108 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.551124 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23927.681504 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22790.310918 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23656.360500 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25802.491103 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24847.777778 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25128.399582 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85882.080660 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71280.816270 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 80039.808655 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 76500 # average ReadSharedReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.010828 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.049230 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.015284 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.054010 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.034305 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.044463 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.742352 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.853589 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.784375 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.060870 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.287171 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.146510 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748583 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.025641 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.109767 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078495 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.534456 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.489672 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.060870 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.287171 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.266723 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748583 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.025641 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.109767 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.419289 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.534456 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.509449 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.060870 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.287171 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.266723 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748583 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.025641 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.109767 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.419289 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.534456 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.509449 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 24301.822323 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22748.091603 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23721.112696 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26018.656716 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23475 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25067.757009 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 86044.396552 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72286.305384 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 80388.338968 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 77642.857143 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71668.291736 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77822.242584 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86486.964456 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72403.846154 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79518.105850 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102576.115419 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 84778.329155 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76500 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72362.730318 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78107.087657 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87168.014344 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73701.623238 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79024.236038 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102198.759897 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85450.721597 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77642.857143 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71668.291736 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82299.246474 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86486.964456 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72403.846154 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72020.575360 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102576.115419 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 84308.214858 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72362.730318 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82564.091393 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87168.014344 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73701.623238 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72993.091743 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102198.759897 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 84927.650416 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77642.857143 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71668.291736 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82299.246474 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86486.964456 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72403.846154 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72020.575360 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102576.115419 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 84308.214858 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72362.730318 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82564.091393 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87168.014344 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73701.623238 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72993.091743 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102198.759897 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 84927.650416 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 195676.347958 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 147741.048733 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 153306.019422 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182525.781822 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62788.135593 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117205.910853 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 153288.321522 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101258.887854 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81392.649942 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 90117.227720 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 502889 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 289010 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96296.444771 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62788.135593 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65429.047962 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 90101.908166 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 504508 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 283356 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 44074 # Transaction distribution -system.membus.trans_dist::ReadResp 209458 # Transaction distribution -system.membus.trans_dist::WriteReq 30904 # Transaction distribution -system.membus.trans_dist::WriteResp 30904 # Transaction distribution -system.membus.trans_dist::WritebackDirty 130397 # Transaction distribution -system.membus.trans_dist::CleanEvict 14501 # Transaction distribution -system.membus.trans_dist::UpgradeReq 77693 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40094 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 44081 # Transaction distribution +system.membus.trans_dist::ReadResp 215279 # Transaction distribution +system.membus.trans_dist::WriteReq 30913 # Transaction distribution +system.membus.trans_dist::WriteResp 30913 # Transaction distribution +system.membus.trans_dist::WritebackDirty 137329 # Transaction distribution +system.membus.trans_dist::CleanEvict 16651 # Transaction distribution +system.membus.trans_dist::UpgradeReq 64792 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38133 # Transaction distribution system.membus.trans_dist::UpgradeResp 16 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 38557 # Transaction distribution -system.membus.trans_dist::ReadExResp 18075 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 165384 # Transaction distribution +system.membus.trans_dist::ReadExReq 40131 # Transaction distribution +system.membus.trans_dist::ReadExResp 19681 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 171198 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13706 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 641086 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 762740 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13736 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 650114 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 771800 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 835679 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 844739 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27412 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17788748 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17979022 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18707276 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18897612 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20296142 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 125256 # Total snoops (count) +system.membus.pkt_size::total 21214732 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123049 # Total snoops (count) system.membus.snoopTraffic 37632 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 432932 # Request fanout histogram -system.membus.snoop_fanout::mean 0.012007 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.108915 # Request fanout histogram +system.membus.snoop_fanout::samples 425474 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012172 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.109655 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 427734 98.80% 98.80% # Request fanout histogram -system.membus.snoop_fanout::1 5198 1.20% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 420295 98.78% 98.78% # Request fanout histogram +system.membus.snoop_fanout::1 5179 1.22% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 432932 # Request fanout histogram -system.membus.reqLayer0.occupancy 88248500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 425474 # Request fanout histogram +system.membus.reqLayer0.occupancy 88273000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11302499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11470000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 949242954 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 976922430 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1079420372 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1118158241 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1341881 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1366131 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3019,77 +3047,77 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 971913 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 526665 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 151758 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 18562 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 17727 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 835 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 44077 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 473751 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30904 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30904 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 349854 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 105962 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 111902 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 43122 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 155024 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 90 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 90 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50816 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50816 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 429676 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4592 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1183270 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 322305 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1505575 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 33366812 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4544754 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 37911566 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 376245 # Total snoops (count) -system.toL2Bus.snoopTraffic 15498572 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 834461 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.383881 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.488383 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1015113 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 540228 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 174806 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 29447 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 28379 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1068 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 44084 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 511780 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 361959 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 119582 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 109939 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 42732 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 152671 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 79 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51282 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51282 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 467698 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4573 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1273273 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 316945 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1590218 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35272632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5631700 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 40904332 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 389588 # Total snoops (count) +system.toL2Bus.snoopTraffic 15743116 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 889230 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.395392 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.491385 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 514962 61.71% 61.71% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 318664 38.19% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 835 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 538704 60.58% 60.58% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 349458 39.30% 99.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1068 0.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 834461 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 867249813 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 889230 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 894701567 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 360619 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 626009420 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 677372101 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 234312270 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 239236747 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 6cf90c5a5..dd34564a7 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.909583 # Number of seconds simulated -sim_ticks 2909582799500 # Number of ticks simulated -final_tick 2909582799500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.903737 # Number of seconds simulated +sim_ticks 2903736790500 # Number of ticks simulated +final_tick 2903736790500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 722784 # Simulator instruction rate (inst/s) -host_op_rate 871447 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18699971433 # Simulator tick rate (ticks/s) -host_mem_usage 573692 # Number of bytes of host memory used -host_seconds 155.59 # Real time elapsed on the host -sim_insts 112460013 # Number of instructions simulated -sim_ops 135590937 # Number of ops (including micro ops) simulated +host_inst_rate 515424 # Simulator instruction rate (inst/s) +host_op_rate 621448 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13306386787 # Simulator tick rate (ticks/s) +host_mem_usage 582748 # Number of bytes of host memory used +host_seconds 218.22 # Real time elapsed on the host +sim_insts 112476413 # Number of instructions simulated +sim_ops 135613231 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 512 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1186404 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8901988 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1188964 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9028260 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10089928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1186404 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1186404 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7511936 # Number of bytes written to this memory +system.physmem.bytes_read::total 10218824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1188964 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1188964 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7618752 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7529460 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7636276 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26991 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 139613 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 27031 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141586 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166628 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117374 # Number of write requests responded to by this memory +system.physmem.num_reads::total 168642 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 119043 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121755 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 123424 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 176 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 407757 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3059541 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3467826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 407757 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 407757 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2581791 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6023 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2587814 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2581791 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 409460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3109187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3519198 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 409460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 409460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2623775 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6035 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2629810 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2623775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 176 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 407757 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3065564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6055641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166628 # Number of read requests accepted -system.physmem.writeReqs 121755 # Number of write requests accepted -system.physmem.readBursts 166628 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121755 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10656448 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue -system.physmem.bytesWritten 7542016 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10089928 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7529460 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu.inst 409460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3115222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6149008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168642 # Number of read requests accepted +system.physmem.writeReqs 123424 # Number of write requests accepted +system.physmem.readBursts 168642 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123424 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10783744 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue +system.physmem.bytesWritten 7648256 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10218824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7636276 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10077 # Per bank write bursts -system.physmem.perBankRdBursts::1 9979 # Per bank write bursts -system.physmem.perBankRdBursts::2 10695 # Per bank write bursts -system.physmem.perBankRdBursts::3 10660 # Per bank write bursts -system.physmem.perBankRdBursts::4 18797 # Per bank write bursts -system.physmem.perBankRdBursts::5 9659 # Per bank write bursts -system.physmem.perBankRdBursts::6 9664 # Per bank write bursts -system.physmem.perBankRdBursts::7 10481 # Per bank write bursts -system.physmem.perBankRdBursts::8 9276 # Per bank write bursts -system.physmem.perBankRdBursts::9 9973 # Per bank write bursts -system.physmem.perBankRdBursts::10 9234 # Per bank write bursts -system.physmem.perBankRdBursts::11 8678 # Per bank write bursts -system.physmem.perBankRdBursts::12 9820 # Per bank write bursts -system.physmem.perBankRdBursts::13 10379 # Per bank write bursts -system.physmem.perBankRdBursts::14 9723 # Per bank write bursts -system.physmem.perBankRdBursts::15 9412 # Per bank write bursts -system.physmem.perBankWrBursts::0 7393 # Per bank write bursts -system.physmem.perBankWrBursts::1 7263 # Per bank write bursts -system.physmem.perBankWrBursts::2 8282 # Per bank write bursts -system.physmem.perBankWrBursts::3 8171 # Per bank write bursts -system.physmem.perBankWrBursts::4 7489 # Per bank write bursts -system.physmem.perBankWrBursts::5 7265 # Per bank write bursts -system.physmem.perBankWrBursts::6 7108 # Per bank write bursts -system.physmem.perBankWrBursts::7 7659 # Per bank write bursts -system.physmem.perBankWrBursts::8 7080 # Per bank write bursts -system.physmem.perBankWrBursts::9 7523 # Per bank write bursts -system.physmem.perBankWrBursts::10 6697 # Per bank write bursts -system.physmem.perBankWrBursts::11 6470 # Per bank write bursts -system.physmem.perBankWrBursts::12 7534 # Per bank write bursts -system.physmem.perBankWrBursts::13 7859 # Per bank write bursts -system.physmem.perBankWrBursts::14 7263 # Per bank write bursts -system.physmem.perBankWrBursts::15 6788 # Per bank write bursts +system.physmem.perBankRdBursts::0 9943 # Per bank write bursts +system.physmem.perBankRdBursts::1 9648 # Per bank write bursts +system.physmem.perBankRdBursts::2 10560 # Per bank write bursts +system.physmem.perBankRdBursts::3 10245 # Per bank write bursts +system.physmem.perBankRdBursts::4 18706 # Per bank write bursts +system.physmem.perBankRdBursts::5 9867 # Per bank write bursts +system.physmem.perBankRdBursts::6 9999 # Per bank write bursts +system.physmem.perBankRdBursts::7 10271 # Per bank write bursts +system.physmem.perBankRdBursts::8 9694 # Per bank write bursts +system.physmem.perBankRdBursts::9 10419 # Per bank write bursts +system.physmem.perBankRdBursts::10 9828 # Per bank write bursts +system.physmem.perBankRdBursts::11 9028 # Per bank write bursts +system.physmem.perBankRdBursts::12 10140 # Per bank write bursts +system.physmem.perBankRdBursts::13 10489 # Per bank write bursts +system.physmem.perBankRdBursts::14 10151 # Per bank write bursts +system.physmem.perBankRdBursts::15 9508 # Per bank write bursts +system.physmem.perBankWrBursts::0 7397 # Per bank write bursts +system.physmem.perBankWrBursts::1 7199 # Per bank write bursts +system.physmem.perBankWrBursts::2 8385 # Per bank write bursts +system.physmem.perBankWrBursts::3 7801 # Per bank write bursts +system.physmem.perBankWrBursts::4 7213 # Per bank write bursts +system.physmem.perBankWrBursts::5 7134 # Per bank write bursts +system.physmem.perBankWrBursts::6 7314 # Per bank write bursts +system.physmem.perBankWrBursts::7 7590 # Per bank write bursts +system.physmem.perBankWrBursts::8 7388 # Per bank write bursts +system.physmem.perBankWrBursts::9 8015 # Per bank write bursts +system.physmem.perBankWrBursts::10 7407 # Per bank write bursts +system.physmem.perBankWrBursts::11 6899 # Per bank write bursts +system.physmem.perBankWrBursts::12 7622 # Per bank write bursts +system.physmem.perBankWrBursts::13 7751 # Per bank write bursts +system.physmem.perBankWrBursts::14 7507 # Per bank write bursts +system.physmem.perBankWrBursts::15 6882 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 6 # Number of times write queue was full causing retry -system.physmem.totGap 2909582442500 # Total gap between requests +system.physmem.numWrRetry 9 # Number of times write queue was full causing retry +system.physmem.totGap 2903736355000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157056 # Read request sizes (log2) +system.physmem.readPktSize::6 159070 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117374 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165625 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 256 # What read queue length does an incoming req see +system.physmem.writePktSize::6 119043 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 167708 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 529 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 247 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -160,160 +160,163 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7024 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58757 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 309.723097 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 182.771096 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.648637 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21456 36.52% 36.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14672 24.97% 61.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6129 10.43% 71.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3189 5.43% 77.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2542 4.33% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1474 2.51% 84.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1037 1.76% 85.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1065 1.81% 87.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7193 12.24% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58757 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5617 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.641446 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 597.657190 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5616 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58618 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 314.441571 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 184.322128 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.751512 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21316 36.36% 36.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14773 25.20% 61.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5607 9.57% 71.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3267 5.57% 76.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2505 4.27% 80.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1471 2.51% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1045 1.78% 85.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1040 1.77% 87.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7594 12.96% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58618 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5878 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.661279 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 584.674226 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5877 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5617 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5617 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.979882 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.786754 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 15.023739 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4951 88.14% 88.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 84 1.50% 89.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 32 0.57% 90.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 37 0.66% 90.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 25 0.45% 91.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 16 0.28% 91.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 42 0.75% 92.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 8 0.14% 92.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 154 2.74% 95.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 13 0.23% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.09% 95.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 19 0.34% 95.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 65 1.16% 97.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.07% 97.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.11% 97.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 28 0.50% 97.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 101 1.80% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.14% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.04% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.12% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5617 # Writes before turning the bus around for reads -system.physmem.totQLat 1616687750 # Total ticks spent queuing -system.physmem.totMemAccLat 4738694000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 832535000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9709.43 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5878 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5878 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.330725 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.604611 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.460490 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5095 86.68% 86.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 41 0.70% 87.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 85 1.45% 88.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 37 0.63% 89.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 285 4.85% 94.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 59 1.00% 95.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 13 0.22% 95.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 14 0.24% 95.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 9 0.15% 95.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.07% 95.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.10% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.14% 96.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 168 2.86% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.05% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 2 0.03% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 6 0.10% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 7 0.12% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.03% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 5 0.09% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.19% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 6 0.10% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5878 # Writes before turning the bus around for reads +system.physmem.totQLat 1493636250 # Total ticks spent queuing +system.physmem.totMemAccLat 4652936250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 842480000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8864.52 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28459.43 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.59 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 27614.52 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.63 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.98 # Average write queue length when enqueuing -system.physmem.readRowHits 136114 # Number of row buffer hits during reads -system.physmem.writeRowHits 89479 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.75 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.92 # Row buffer hit rate for writes -system.physmem.avgGap 10089299.45 # Average gap between requests -system.physmem.pageHitRate 79.33 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 230655600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125853750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 702093600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392882400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 190039717920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 90278415450 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1666557438750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1948327057470 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.624450 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2772287034500 # Time in different power states -system.physmem_0.memoryStateTime::REF 97157320000 # Time in different power states +system.physmem.avgWrQLen 25.41 # Average write queue length when enqueuing +system.physmem.readRowHits 138583 # Number of row buffer hits during reads +system.physmem.writeRowHits 90798 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.96 # Row buffer hit rate for writes +system.physmem.avgGap 9942055.41 # Average gap between requests +system.physmem.pageHitRate 79.64 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 226187640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 123415875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 696064200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 389013840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 189657789360 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 86978464290 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1665943648500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1944014583705 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.487777 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2771286006000 # Time in different power states +system.physmem_0.memoryStateTime::REF 96962060000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 40137378000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35486192750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 213547320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116518875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 596653200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 370746720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 190039717920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 88164027810 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1668412164750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1947913376595 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.482271 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2775395780750 # Time in different power states -system.physmem_1.memoryStateTime::REF 97157320000 # Time in different power states +system.physmem_1.actEnergy 216964440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 118383375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 618196800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 385372080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 189657789360 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85605070095 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1667148388500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1943750164650 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.396712 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2773305848750 # Time in different power states +system.physmem_1.memoryStateTime::REF 96962060000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 37029550750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33468782750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -326,9 +329,9 @@ system.realview.nvmem.bw_inst_read::cpu.inst 7 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -336,7 +339,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -366,57 +369,58 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 9546 # Table walker walks requested -system.cpu.dtb.walker.walksShort 9546 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1255 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 9546 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 9546 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 9546 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7382 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 13159.103224 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 10921.089481 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8511.779920 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 7377 99.93% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.05% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7382 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 1638910500 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 1638910500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 1638910500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6174 83.64% 83.64% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1208 16.36% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7382 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9546 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 9520 # Table walker walks requested +system.cpu.dtb.walker.walksShort 9520 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1252 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8268 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 9520 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 9520 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 9520 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7356 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 10060.290919 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 8514.979061 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 6541.334463 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 6558 89.15% 89.15% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 793 10.78% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7356 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 941563500 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 941563500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 941563500 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6151 83.62% 83.62% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1205 16.38% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7356 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9520 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9546 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7382 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9520 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7356 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7382 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 16928 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7356 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 16876 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24520634 # DTB read hits -system.cpu.dtb.read_misses 8124 # DTB read misses -system.cpu.dtb.write_hits 19606945 # DTB write hits -system.cpu.dtb.write_misses 1422 # DTB write misses +system.cpu.dtb.read_hits 24525489 # DTB read hits +system.cpu.dtb.read_misses 8109 # DTB read misses +system.cpu.dtb.write_hits 19608938 # DTB write hits +system.cpu.dtb.write_misses 1411 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4208 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 4199 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1649 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 1636 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24528758 # DTB read accesses -system.cpu.dtb.write_accesses 19608367 # DTB write accesses +system.cpu.dtb.read_accesses 24533598 # DTB read accesses +system.cpu.dtb.write_accesses 19610349 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44127579 # DTB hits -system.cpu.dtb.misses 9546 # DTB misses -system.cpu.dtb.accesses 44137125 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 44134427 # DTB hits +system.cpu.dtb.misses 9520 # DTB misses +system.cpu.dtb.accesses 44143947 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -446,37 +450,39 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 4763 # Table walker walks requested -system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 4762 # Table walker walks requested +system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 309 # Level at which table walker walks with short descriptors terminate system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 4763 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 12722.007722 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 10527.196882 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7865.701982 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-16383 2410 77.54% 77.54% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-32767 696 22.39% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 1638383000 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 1638383000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 1638383000 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2798 90.03% 90.03% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 310 9.97% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3108 # Table walker page sizes translated +system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 10273.897650 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 8288.299297 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7346.561217 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1812 58.32% 58.32% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 745 23.98% 82.30% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 548 17.64% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 941232000 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 941232000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 941232000 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 115557255 # ITB inst hits -system.cpu.itb.inst_misses 4763 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 115574516 # ITB inst hits +system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -492,55 +498,55 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115562018 # ITB inst accesses -system.cpu.itb.hits 115557255 # DTB hits -system.cpu.itb.misses 4763 # DTB misses -system.cpu.itb.accesses 115562018 # DTB accesses -system.cpu.numPwrStateTransitions 6066 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 886755819.088361 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17463725487.376945 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 2967 97.82% 97.82% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 60 1.98% 99.80% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 115579278 # ITB inst accesses +system.cpu.itb.hits 115574516 # DTB hits +system.cpu.itb.misses 4762 # DTB misses +system.cpu.itb.accesses 115579278 # DTB accesses +system.cpu.numPwrStateTransitions 6062 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 3031 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 888232478.174860 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17469824950.226959 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 2968 97.92% 97.92% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 57 1.88% 99.80% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 499963874372 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 220052400205 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2689530399295 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5819165599 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 499964073052 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 3031 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 211504149152 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2692232641348 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 5807473581 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu.committedInsts 112460013 # Number of instructions committed -system.cpu.committedOps 135590937 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119896152 # Number of integer alu accesses +system.cpu.kern.inst.quiesce 3031 # number of quiesce instructions executed +system.cpu.committedInsts 112476413 # Number of instructions committed +system.cpu.committedOps 135613231 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119916333 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses -system.cpu.num_func_calls 9892206 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15230739 # number of instructions that are conditional controls -system.cpu.num_int_insts 119896152 # number of integer instructions +system.cpu.num_func_calls 9896179 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15232917 # number of instructions that are conditional controls +system.cpu.num_int_insts 119916333 # number of integer instructions system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218055319 # number of times the integer registers were read -system.cpu.num_int_register_writes 82647707 # number of times the integer registers were written +system.cpu.num_int_register_reads 218092554 # number of times the integer registers were read +system.cpu.num_int_register_writes 82663252 # number of times the integer registers were written system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489751912 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51896592 # number of times the CC registers were written -system.cpu.num_mem_refs 45408087 # number of memory refs -system.cpu.num_load_insts 24843122 # Number of load instructions -system.cpu.num_store_insts 20564965 # Number of store instructions -system.cpu.num_idle_cycles 5379060798.588152 # Number of idle cycles -system.cpu.num_busy_cycles 440104800.411849 # Number of busy cycles -system.cpu.not_idle_fraction 0.075630 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.924370 # Percentage of idle cycles -system.cpu.Branches 25916957 # Number of branches fetched +system.cpu.num_cc_register_reads 489835813 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51902110 # number of times the CC registers were written +system.cpu.num_mem_refs 45414800 # number of memory refs +system.cpu.num_load_insts 24847736 # Number of load instructions +system.cpu.num_store_insts 20567064 # Number of store instructions +system.cpu.num_idle_cycles 5384465282.694146 # Number of idle cycles +system.cpu.num_busy_cycles 423008298.305854 # Number of busy cycles +system.cpu.not_idle_fraction 0.072839 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.927161 # Percentage of idle cycles +system.cpu.Branches 25923023 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93177665 67.17% 67.18% # Class of executed instruction -system.cpu.op_class::IntMult 114484 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93194210 67.17% 67.18% # Class of executed instruction +system.cpu.op_class::IntMult 114540 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -568,501 +574,498 @@ system.cpu.op_class::SimdFloatMisc 8453 0.01% 67.26% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24843122 17.91% 85.17% # Class of executed instruction -system.cpu.op_class::MemWrite 20564965 14.83% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24847736 17.91% 85.18% # Class of executed instruction +system.cpu.op_class::MemWrite 20567064 14.82% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138711026 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 819269 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.702333 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43236296 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819781 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.741276 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.702333 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999419 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999419 # Average percentage of cache occupancy +system.cpu.op_class::total 138734340 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 819770 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.827215 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43243016 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 820282 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.717256 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1013099500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.827215 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999663 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999663 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 366 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177113149 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177113149 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 23112931 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23112931 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18824347 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18824347 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392800 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392800 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443238 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443238 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460213 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460213 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41937278 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41937278 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42330078 # number of overall hits -system.cpu.dcache.overall_hits::total 42330078 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 399955 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 399955 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 298727 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 298727 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118365 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118365 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22758 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22758 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 177141047 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177141047 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 23117557 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23117557 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18826251 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18826251 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 392764 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 392764 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443415 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443415 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460277 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460277 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41943808 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41943808 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42336572 # number of overall hits +system.cpu.dcache.overall_hits::total 42336572 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 400061 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 400061 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 298752 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 298752 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 118460 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 118460 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22645 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22645 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 698682 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 698682 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 817047 # number of overall misses -system.cpu.dcache.overall_misses::total 817047 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6484100500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6484100500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19100782000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19100782000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 294212000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 294212000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 25584882500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 25584882500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 25584882500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 25584882500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23512886 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23512886 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19123074 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19123074 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511165 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511165 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465996 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465996 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460215 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460215 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42635960 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42635960 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43147125 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43147125 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017010 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.017010 # miss rate for ReadReq accesses +system.cpu.dcache.demand_misses::cpu.data 698813 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 698813 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 817273 # number of overall misses +system.cpu.dcache.overall_misses::total 817273 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5967732500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5967732500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12596392000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12596392000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280149500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 280149500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 166000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 166000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18564124500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18564124500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18564124500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18564124500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23517618 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23517618 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19125003 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19125003 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511224 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511224 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466060 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 466060 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460279 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460279 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42642621 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42642621 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43153845 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43153845 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017011 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.017011 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015621 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.015621 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231559 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.231559 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048837 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048837 # miss rate for LoadLockedReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231718 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.231718 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048588 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048588 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016387 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016387 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018936 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018936 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16212.075108 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16212.075108 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63940.594590 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63940.594590 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12927.849547 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12927.849547 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36618.780074 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36618.780074 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31313.844246 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31313.844246 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 100 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.016388 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016388 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018939 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018939 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14917.056399 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14917.056399 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42163.372965 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42163.372965 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12371.362332 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12371.362332 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26565.224888 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26565.224888 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22714.716502 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22714.716502 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 683888 # number of writebacks -system.cpu.dcache.writebacks::total 683888 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 929 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 929 # number of ReadReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14248 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14248 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 929 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 929 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 929 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 929 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 399026 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 399026 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298727 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298727 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116307 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 116307 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8510 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8510 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 683946 # number of writebacks +system.cpu.dcache.writebacks::total 683946 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 680 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 680 # number of ReadReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14146 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14146 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 680 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 680 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 680 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 680 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 399381 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 399381 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298752 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298752 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116429 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 116429 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8499 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8499 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 697753 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 697753 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 814060 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 814060 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 698133 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 698133 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 814562 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 814562 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6054899500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6054899500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18802055000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 18802055000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1615129000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1615129000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115315500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115315500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24856954500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24856954500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26472083500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26472083500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6278142000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6278142000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6278142000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6278142000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016971 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016971 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5555392000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5555392000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12297640000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12297640000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1530002500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1530002500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 108858500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 108858500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 164000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17853032000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17853032000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19383034500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19383034500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6281205500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6281205500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6281205500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6281205500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016982 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016982 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015621 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015621 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227533 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227533 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018262 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018262 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227746 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227746 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018236 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018236 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016365 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016365 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018867 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.018867 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15174.197922 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15174.197922 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62940.594590 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62940.594590 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13886.773797 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13886.773797 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13550.587544 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13550.587544 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35624.288968 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35624.288968 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32518.590153 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32518.590153 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.161410 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.161410 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106903.843207 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106903.843207 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1695563 # number of replacements -system.cpu.icache.tags.tagsinuse 510.436859 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113861174 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1696075 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.132157 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 29070355500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.436859 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996947 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996947 # Average percentage of cache occupancy +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016372 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016372 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018876 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.018876 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13910.005734 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13910.005734 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41163.372965 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41163.372965 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13141.077395 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13141.077395 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12808.389222 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12808.389222 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25572.537038 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25572.537038 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23795.652756 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23795.652756 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201721.546021 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201721.546021 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106956.008310 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106956.008310 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1698000 # number of replacements +system.cpu.icache.tags.tagsinuse 510.728664 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 113875998 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1698512 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.044565 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 25832791500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.728664 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997517 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997517 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 117253336 # Number of tag accesses -system.cpu.icache.tags.data_accesses 117253336 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 113861174 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113861174 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 113861174 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 113861174 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 113861174 # number of overall hits -system.cpu.icache.overall_hits::total 113861174 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1696081 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1696081 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1696081 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1696081 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1696081 # number of overall misses -system.cpu.icache.overall_misses::total 1696081 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24265706000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24265706000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24265706000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24265706000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24265706000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24265706000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115557255 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115557255 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115557255 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115557255 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115557255 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115557255 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014677 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014677 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014677 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014677 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014677 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014677 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14306.926379 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14306.926379 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14306.926379 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14306.926379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14306.926379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14306.926379 # average overall miss latency +system.cpu.icache.tags.tag_accesses 117273034 # Number of tag accesses +system.cpu.icache.tags.data_accesses 117273034 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 113875998 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113875998 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113875998 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113875998 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 113875998 # number of overall hits +system.cpu.icache.overall_hits::total 113875998 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1698518 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1698518 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1698518 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1698518 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1698518 # number of overall misses +system.cpu.icache.overall_misses::total 1698518 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23414403500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23414403500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23414403500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23414403500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23414403500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23414403500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 115574516 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 115574516 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 115574516 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 115574516 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 115574516 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 115574516 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014696 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014696 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014696 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014696 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014696 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014696 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13785.195977 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13785.195977 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13785.195977 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13785.195977 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13785.195977 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13785.195977 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1695563 # number of writebacks -system.cpu.icache.writebacks::total 1695563 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696081 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1696081 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1696081 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1696081 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1696081 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1696081 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 1698000 # number of writebacks +system.cpu.icache.writebacks::total 1698000 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1698518 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1698518 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1698518 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1698518 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1698518 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1698518 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22569625000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22569625000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22569625000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22569625000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22569625000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22569625000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1142541000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 1142541000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014677 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014677 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014677 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014677 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014677 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014677 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13306.926379 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13306.926379 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13306.926379 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13306.926379 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13306.926379 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13306.926379 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 87565 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64865.266824 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4544306 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 152800 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 29.740223 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50196.788245 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.799337 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012648 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9701.702812 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4962.963782 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.765942 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.148036 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.075729 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989765 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65230 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6849 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56201 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995331 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40510666 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40510666 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7807 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4039 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 11846 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 683888 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 683888 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1664800 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1664800 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 167046 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 167046 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1678073 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1678073 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 511671 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 511671 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 7807 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 4039 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1678073 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 678717 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2368636 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 7807 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 4039 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1678073 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 678717 # number of overall hits -system.cpu.l2cache.overall_hits::total 2368636 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21715885500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21715885500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21715885500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21715885500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21715885500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21715885500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 687287000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 687287000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 687287000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 687287000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014696 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014696 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014696 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014696 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014696 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014696 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12785.195977 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12785.195977 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12785.195977 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12785.195977 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12785.195977 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12785.195977 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76179.006872 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76179.006872 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76179.006872 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76179.006872 # average overall mshr uncacheable latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 89464 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65017.694965 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4847707 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 154877 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 31.300367 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 144041988000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.877834 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.040783 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9524.120186 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 55489.656162 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.145327 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.846705 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.992091 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65407 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4600 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60798 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998032 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 40230644 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40230644 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5114 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2743 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 7857 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 683946 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 683946 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1666952 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1666952 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 2730 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 2730 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 166687 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 166687 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1680478 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1680478 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 512210 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 512210 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 5114 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 2743 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1680478 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 678897 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2367232 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 5114 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 2743 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1680478 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 678897 # number of overall hits +system.cpu.l2cache.overall_hits::total 2367232 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 8 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2742 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2742 # number of UpgradeReq misses +system.cpu.l2cache.ReadReq_misses::total 10 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 20 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 20 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 128916 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 128916 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17976 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 17976 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12172 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 12172 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 129315 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 129315 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18016 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 18016 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12099 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 12099 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 8 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 17976 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 141088 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 159073 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 18016 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 141414 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 159440 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 8 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 17976 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 141088 # number of overall misses -system.cpu.l2cache.overall_misses::total 159073 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 957500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 266000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1223500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1793500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 1793500 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16382163500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16382163500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2346906500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2346906500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1609809500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1609809500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 957500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 266000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2346906500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 17991973000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20340103000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 957500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 266000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2346906500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 17991973000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20340103000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7814 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4041 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 11855 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 683888 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 683888 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1664800 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1664800 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2765 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2765 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.inst 18016 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 141414 # number of overall misses +system.cpu.l2cache.overall_misses::total 159440 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 829500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 168000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 997500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 581000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 581000 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 161000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 161000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10066469000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10066469000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1464060500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1464060500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1012302000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1012302000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 829500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 168000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1464060500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11078771000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12543829000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 829500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 168000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1464060500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11078771000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12543829000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5122 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2745 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7867 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 683946 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 683946 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1666952 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1666952 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2750 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2750 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 295962 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 295962 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1696049 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1696049 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 523843 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 523843 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7814 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 4041 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1696049 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819805 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2527709 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7814 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 4041 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1696049 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819805 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2527709 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000896 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000495 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000759 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991682 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991682 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 296002 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 296002 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1698494 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1698494 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 524309 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 524309 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5122 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 2745 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1698494 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 820311 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2526672 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5122 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 2745 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1698494 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 820311 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2526672 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001562 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000729 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001271 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.007273 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.007273 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.435583 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.435583 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010599 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010599 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023236 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023236 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000896 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000495 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010599 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.172099 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.062932 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000896 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000495 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010599 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.172099 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.062932 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136785.714286 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 133000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 135944.444444 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 654.084610 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 654.084610 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127076.262838 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127076.262838 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130557.771473 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130557.771473 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132255.134735 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132255.134735 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130557.771473 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127523.056532 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 127866.470111 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130557.771473 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127523.056532 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 127866.470111 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436872 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.436872 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010607 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010607 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023076 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023076 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001562 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000729 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010607 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.172391 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.063103 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001562 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000729 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010607 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.172391 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.063103 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 103687.500000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 84000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 99750 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29050 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29050 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77844.557863 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77844.557863 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81264.459369 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81264.459369 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83668.237044 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83668.237044 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 103687.500000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 84000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81264.459369 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78342.816129 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78674.291269 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 103687.500000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 84000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81264.459369 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78342.816129 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78674.291269 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 81184 # number of writebacks -system.cpu.l2cache.writebacks::total 81184 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 82853 # number of writebacks +system.cpu.l2cache.writebacks::total 82853 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 8 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2742 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2742 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 10 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 20 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 20 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128916 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 128916 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17976 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17976 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12172 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12172 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 129315 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 129315 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 18016 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 18016 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12099 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12099 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 8 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 17976 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 141088 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 159073 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 18016 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141414 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 159440 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 8 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 17976 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 141088 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 159073 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 18016 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141414 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 159440 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable @@ -1071,147 +1074,147 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27589 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 887500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 246000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1133500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 186569500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 186569500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 139000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15093003500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15093003500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2167146500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2167146500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1488089500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1488089500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 887500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 246000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2167146500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16581093000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18749373000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 887500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 246000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2167146500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16581093000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18749373000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888796500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6918562500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1029766000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5888796500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6918562500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000759 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991682 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991682 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 749500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 148000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 897500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 381000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 381000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 141000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 141000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8773319000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8773319000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1283900500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1283900500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 891312000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 891312000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 749500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 148000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1283900500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9664631000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10949429000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 749500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 148000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1283900500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9664631000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10949429000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 574512000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5891860500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6466372500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 574512000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5891860500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6466372500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001562 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000729 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001271 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.007273 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.007273 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435583 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435583 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010599 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023236 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023236 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172099 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.062932 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172099 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.062932 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125944.444444 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68041.393144 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68041.393144 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117076.262838 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117076.262838 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120557.771473 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120557.771473 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122255.134735 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122255.134735 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120557.771473 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117523.056532 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117866.470111 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120557.771473 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117523.056532 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117866.470111 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.291541 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172274.962649 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100274.090282 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 102120.511004 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5052639 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536775 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38121 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436872 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436872 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010607 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023076 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023076 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001562 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000729 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172391 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063103 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001562 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000729 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172391 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063103 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 89750 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19050 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19050 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67844.557863 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67844.557863 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71264.459369 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71264.459369 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73668.237044 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73668.237044 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71264.459369 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68342.816129 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68674.291269 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71264.459369 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68342.816129 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68674.291269 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63679.006872 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189217.692209 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161015.251494 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63679.006872 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100326.263899 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 95446.021343 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5058492 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2539687 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38280 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 250 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 250 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 67213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2287350 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 67163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2290209 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 801268 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1695563 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 141990 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2765 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 766799 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1698000 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 142435 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2750 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2767 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295962 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295962 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696081 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 524071 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5105737 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2582080 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13257 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25651 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7726725 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217099256 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96433117 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16164 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31256 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 313579793 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 175884 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7588792 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2773896 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.020865 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.142933 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2752 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296002 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296002 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1698518 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 524530 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 4455 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5113056 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2583569 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 11960 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 22910 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7731495 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217411704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96469597 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 10980 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 20488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 313912769 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 113519 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5394688 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2710473 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.021286 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.144336 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2716018 97.91% 97.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 57878 2.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2652778 97.87% 97.87% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 57695 2.13% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2773896 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4957389000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2710473 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4962792000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 389377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2553143500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2556799000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1276023999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1276777495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17837000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 17788000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 30177 # Transaction distribution -system.iobus.trans_dist::ReadResp 30177 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 30183 # Transaction distribution +system.iobus.trans_dist::ReadResp 30183 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1234,9 +1237,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) @@ -1257,14 +1260,14 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46336000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 46334000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 338500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1272,7 +1275,7 @@ system.iobus.reqLayer4.occupancy 15500 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 95000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 643000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 642000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1294,56 +1297,56 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6279500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6273000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187079512 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187671849 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36418 # number of replacements -system.iocache.tags.tagsinuse 1.084047 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 36424 # number of replacements +system.iocache.tags.tagsinuse 1.078594 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 313815669000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.084047 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067753 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067753 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 309373303000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.078594 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067412 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067412 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328068 # Number of tag accesses -system.iocache.tags.data_accesses 328068 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses -system.iocache.ReadReq_misses::total 228 # number of ReadReq misses +system.iocache.tags.tag_accesses 328122 # Number of tag accesses +system.iocache.tags.data_accesses 328122 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses +system.iocache.ReadReq_misses::total 234 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36452 # number of demand (read+write) misses -system.iocache.demand_misses::total 36452 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36452 # number of overall misses -system.iocache.overall_misses::total 36452 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 30010377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 30010377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4549130135 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4549130135 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4579140512 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4579140512 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4579140512 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4579140512 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses +system.iocache.demand_misses::total 36458 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36458 # number of overall misses +system.iocache.overall_misses::total 36458 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28897377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28897377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4278807472 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4278807472 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4307704849 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4307704849 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4307704849 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4307704849 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36452 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36452 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36452 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36452 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1352,14 +1355,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 131624.460526 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 131624.460526 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125583.318656 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125583.318656 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125621.104795 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125621.104795 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125621.104795 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125621.104795 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 123493.064103 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123493.064103 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118120.789311 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118120.789311 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118155.270421 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118155.270421 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118155.270421 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118155.270421 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1368,22 +1371,22 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36452 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36452 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36452 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36452 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18610377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18610377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736516617 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2736516617 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2755126994 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2755126994 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2755126994 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2755126994 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17197377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17197377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2465502723 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2465502723 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2482700100 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2482700100 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2482700100 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2482700100 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1392,84 +1395,90 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 81624.460526 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 81624.460526 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75544.297068 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75544.297068 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75582.327280 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75582.327280 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75582.327280 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75582.327280 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73493.064103 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 73493.064103 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68062.685595 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68062.685595 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68097.539635 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68097.539635 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68097.539635 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68097.539635 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 321817 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 130498 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 40160 # Transaction distribution -system.membus.trans_dist::ReadResp 70545 # Transaction distribution +system.membus.trans_dist::ReadResp 70519 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117374 # Transaction distribution -system.membus.trans_dist::CleanEvict 6609 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution +system.membus.trans_dist::WritebackDirty 119043 # Transaction distribution +system.membus.trans_dist::CleanEvict 6845 # Transaction distribution +system.membus.trans_dist::UpgradeReq 128 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 127161 # Transaction distribution -system.membus.trans_dist::ReadExResp 127161 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30385 # Transaction distribution +system.membus.trans_dist::ReadExReq 129207 # Transaction distribution +system.membus.trans_dist::ReadExResp 129207 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30359 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 434329 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 541921 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72885 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72885 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 614806 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 435887 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543479 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 616376 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15302268 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15465621 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15537980 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15701333 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17782741 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 492 # Total snoops (count) -system.membus.snoopTraffic 31360 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 390007 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size::total 18018453 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 498 # Total snoops (count) +system.membus.snoopTraffic 31744 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 263669 # Request fanout histogram +system.membus.snoop_fanout::mean 0.018793 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.135792 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 390007 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 258714 98.12% 98.12% # Request fanout histogram +system.membus.snoop_fanout::1 4955 1.88% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 390007 # Request fanout histogram -system.membus.reqLayer0.occupancy 90458000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 263669 # Request fanout histogram +system.membus.reqLayer0.occupancy 90449000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1730000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1734500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 823140613 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 828323280 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 943221250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 954014500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1186373 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1219623 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1501,28 +1510,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2909582799500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 81757b1a0..5223c911e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu sim_ticks 2783854715000 # Number of ticks simulated final_tick 2783854715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 842839 # Simulator instruction rate (inst/s) -host_op_rate 1026021 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16434267548 # Simulator tick rate (ticks/s) -host_mem_usage 578044 # Number of bytes of host memory used -host_seconds 169.39 # Real time elapsed on the host +host_inst_rate 808320 # Simulator instruction rate (inst/s) +host_op_rate 984000 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15761202711 # Simulator tick rate (ticks/s) +host_mem_usage 583272 # Number of bytes of host memory used +host_seconds 176.63 # Real time elapsed on the host sim_insts 142771202 # Number of instructions simulated sim_ops 173801044 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -333,8 +333,8 @@ system.cpu0.dcache.ReadReq_hits::cpu0.data 15303909 # system.cpu0.dcache.ReadReq_hits::cpu1.data 14824794 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 30128703 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 10894549 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 11445217 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 22339766 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 11445218 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 22339767 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185793 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209252 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 395045 # number of SoftPFReq hits @@ -345,17 +345,17 @@ system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236699 system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223423 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits system.cpu0.dcache.demand_hits::cpu0.data 26198458 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 26270011 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 52468469 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 26270012 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 52468470 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::cpu0.data 26384251 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 26479263 # number of overall hits -system.cpu0.dcache.overall_hits::total 52863514 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 26479264 # number of overall hits +system.cpu0.dcache.overall_hits::total 52863515 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 197405 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu1.data 198906 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 396311 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 137584 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 164079 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 301663 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 164078 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 301662 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54365 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61704 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 116069 # number of SoftPFReq misses @@ -365,11 +365,11 @@ system.cpu0.dcache.LoadLockedReq_misses::total 8628 system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses system.cpu0.dcache.demand_misses::cpu0.data 334989 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 362985 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 697974 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 362984 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 697973 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 389354 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 424689 # number of overall misses -system.cpu0.dcache.overall_misses::total 814043 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 424688 # number of overall misses +system.cpu0.dcache.overall_misses::total 814042 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 15501314 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu1.data 15023700 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 30525014 # number of ReadReq accesses(hits+misses) @@ -417,8 +417,8 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 682241 # number of writebacks -system.cpu0.dcache.writebacks::total 682241 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 682362 # number of writebacks +system.cpu0.dcache.writebacks::total 682362 # number of writebacks system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 1698988 # number of replacements system.cpu0.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use @@ -801,92 +801,89 @@ system.iocache.writebacks::writebacks 36190 # nu system.iocache.writebacks::total 36190 # number of writebacks system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 109906 # number of replacements -system.l2c.tags.tagsinuse 65155.312233 # Cycle average of tags in use -system.l2c.tags.total_refs 4527993 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 175187 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 25.846627 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48764.096462 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924324 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000096 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5146.050132 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4729.659368 # Average occupied blocks per requestor +system.l2c.tags.tagsinuse 65246.862245 # Cycle average of tags in use +system.l2c.tags.total_refs 4830712 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 175332 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 27.551799 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 71491095000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.924122 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999998 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5146.889475 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 28219.641429 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.978701 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4022.536499 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2489.066650 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.744081 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.078522 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.072169 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 4023.136773 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 27850.291746 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000075 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.078535 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.430598 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.061379 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.037980 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65277 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 10699 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 50642 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 40604073 # Number of tag accesses -system.l2c.tags.data_accesses 40604073 # Number of data accesses +system.l2c.tags.occ_percent::cpu1.inst 0.061388 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.424962 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995588 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65419 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 9745 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55478 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.998215 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 40281361 # Number of tag accesses +system.l2c.tags.data_accesses 40281361 # Number of data accesses system.l2c.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 4711 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2279 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4978 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2423 # number of ReadReq hits -system.l2c.ReadReq_hits::total 14391 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 682241 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 682241 # number of WritebackDirty hits +system.l2c.ReadReq_hits::cpu0.dtb.walker 3721 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1793 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 3957 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1933 # number of ReadReq hits +system.l2c.ReadReq_hits::total 11404 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 682362 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 682362 # number of WritebackDirty hits system.l2c.WritebackClean_hits::writebacks 1666989 # number of WritebackClean hits system.l2c.WritebackClean_hits::total 1666989 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 72332 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 78800 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 151132 # number of ReadExReq hits +system.l2c.UpgradeReq_hits::cpu0.data 1257 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1489 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2746 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 73078 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 79712 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 152790 # number of ReadExReq hits system.l2c.ReadCleanReq_hits::cpu0.inst 833454 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::cpu1.inst 847737 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::total 1681191 # number of ReadCleanReq hits system.l2c.ReadSharedReq_hits::cpu0.data 246679 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.data 258766 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::total 505445 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4711 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2279 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.dtb.walker 3721 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1793 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.inst 833454 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 319011 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4978 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2423 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 319757 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 3957 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1933 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 847737 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 337566 # number of demand (read+write) hits -system.l2c.demand_hits::total 2352159 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4711 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2279 # number of overall hits +system.l2c.demand_hits::cpu1.data 338478 # number of demand (read+write) hits +system.l2c.demand_hits::total 2350830 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 3721 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1793 # number of overall hits system.l2c.overall_hits::cpu0.inst 833454 # number of overall hits -system.l2c.overall_hits::cpu0.data 319011 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4978 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2423 # number of overall hits +system.l2c.overall_hits::cpu0.data 319757 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 3957 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1933 # number of overall hits system.l2c.overall_hits::cpu1.inst 847737 # number of overall hits -system.l2c.overall_hits::cpu1.data 337566 # number of overall hits -system.l2c.overall_hits::total 2352159 # number of overall hits +system.l2c.overall_hits::cpu1.data 338478 # number of overall hits +system.l2c.overall_hits::total 2350830 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::total 8 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1250 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1478 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2728 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 9 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63990 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 83785 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 147775 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 63244 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 82873 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 146117 # number of ReadExReq misses system.l2c.ReadCleanReq_misses::cpu0.inst 10757 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::cpu1.inst 7541 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses @@ -896,31 +893,31 @@ system.l2c.ReadSharedReq_misses::total 15563 # nu system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 10757 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 73743 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 72997 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 7541 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 89595 # number of demand (read+write) misses -system.l2c.demand_misses::total 181644 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 88683 # number of demand (read+write) misses +system.l2c.demand_misses::total 179986 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.inst 10757 # number of overall misses -system.l2c.overall_misses::cpu0.data 73743 # number of overall misses +system.l2c.overall_misses::cpu0.data 72997 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses system.l2c.overall_misses::cpu1.inst 7541 # number of overall misses -system.l2c.overall_misses::cpu1.data 89595 # number of overall misses -system.l2c.overall_misses::total 181644 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4716 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 2280 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 4980 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 2423 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 14399 # number of ReadReq accesses(hits+misses) -system.l2c.WritebackDirty_accesses::writebacks 682241 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 682241 # number of WritebackDirty accesses(hits+misses) +system.l2c.overall_misses::cpu1.data 88683 # number of overall misses +system.l2c.overall_misses::total 179986 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 3726 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 1794 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 3959 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1933 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 11412 # number of ReadReq accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 682362 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 682362 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackClean_accesses::writebacks 1666989 # number of WritebackClean accesses(hits+misses) system.l2c.WritebackClean_accesses::total 1666989 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 1262 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1494 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1493 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2755 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 136322 # number of ReadExReq accesses(hits+misses) @@ -932,58 +929,58 @@ system.l2c.ReadCleanReq_accesses::total 1699489 # nu system.l2c.ReadSharedReq_accesses::cpu0.data 256432 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.data 264576 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4716 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 2280 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.dtb.walker 3726 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1794 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.inst 844211 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 392754 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 4980 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 2423 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 3959 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1933 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 855278 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 427161 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2533803 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4716 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 2280 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2530816 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 3726 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1794 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.inst 844211 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 392754 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 4980 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 2423 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 3959 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1933 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 855278 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 427161 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2533803 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001060 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000439 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000402 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.000556 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990491 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989290 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses +system.l2c.overall_accesses::total 2530816 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001342 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000557 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000505 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.000701 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.003962 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.002679 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.003267 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.469403 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.515330 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.494385 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.463931 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.509721 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.488838 # miss rate for ReadExReq accesses system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.012742 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.008817 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.038033 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021960 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::total 0.029871 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001060 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000439 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001342 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000557 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.012742 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.187759 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000402 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.185859 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000505 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.008817 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.209745 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.071688 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001060 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000439 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu1.data 0.207610 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.071118 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001342 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000557 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.012742 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.187759 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000402 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.185859 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000505 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.008817 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.209745 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.071688 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.207610 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.071118 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -992,8 +989,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.writebacks::writebacks 101943 # number of writebacks system.l2c.writebacks::total 101943 # number of writebacks -system.membus.snoop_filter.tot_requests 367174 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 155394 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 362797 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 151017 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 488 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. @@ -1005,9 +1002,9 @@ system.membus.trans_dist::WriteReq 27546 # Tr system.membus.trans_dist::WriteResp 27546 # Transaction distribution system.membus.trans_dist::WritebackDirty 138133 # Transaction distribution system.membus.trans_dist::CleanEvict 8203 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution +system.membus.trans_dist::UpgradeReq 130 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution +system.membus.trans_dist::UpgradeResp 132 # Transaction distribution system.membus.trans_dist::ReadExReq 145996 # Transaction distribution system.membus.trans_dist::ReadExResp 145996 # Transaction distribution system.membus.trans_dist::ReadSharedReq 34109 # Transaction distribution @@ -1016,11 +1013,11 @@ system.membus.trans_dist::InvalidateResp 36224 # Tr system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 506560 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 613920 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 497806 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 605166 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723278 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 714524 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) @@ -1031,17 +1028,17 @@ system.membus.pkt_size_system.iocache.mem_side::total 2331520 system.membus.pkt_size::total 20586073 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 434807 # Request fanout histogram -system.membus.snoop_fanout::mean 0.012707 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.112006 # Request fanout histogram +system.membus.snoop_fanout::samples 430430 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012836 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.112567 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 429282 98.73% 98.73% # Request fanout histogram -system.membus.snoop_fanout::1 5525 1.27% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 424905 98.72% 98.72% # Request fanout histogram +system.membus.snoop_fanout::1 5525 1.28% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 434807 # Request fanout histogram +system.membus.snoop_fanout::total 430430 # Request fanout histogram system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states @@ -1111,8 +1108,8 @@ system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5060295 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2540893 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5060294 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2540892 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. @@ -1122,38 +1119,38 @@ system.toL2Bus.trans_dist::ReadReq 71240 # Tr system.toL2Bus.trans_dist::ReadResp 2291754 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 682241 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 682362 # Transaction distribution system.toL2Bus.trans_dist::WritebackClean 1698988 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 137146 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 137025 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2757 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1699506 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5116044 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581955 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581953 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20756 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41550 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7760305 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7760303 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 217539704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96320737 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96328481 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41512 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83100 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 313985053 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 313992797 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 115320 # Total snoops (count) system.toL2Bus.snoopTraffic 6540928 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 5254492 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 5254491 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 0.018785 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0.135764 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5155788 98.12% 98.12% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5155787 98.12% 98.12% # Request fanout histogram system.toL2Bus.snoop_fanout::1 98704 1.88% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5254492 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5254491 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 8a51e33ba..0051059a3 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.903873 # Number of seconds simulated -sim_ticks 2903873346500 # Number of ticks simulated -final_tick 2903873346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.903767 # Number of seconds simulated +sim_ticks 2903766778500 # Number of ticks simulated +final_tick 2903766778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 468304 # Simulator instruction rate (inst/s) -host_op_rate 564635 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12090989758 # Simulator tick rate (ticks/s) -host_mem_usage 578040 # Number of bytes of host memory used -host_seconds 240.17 # Real time elapsed on the host -sim_insts 112471852 # Number of instructions simulated -sim_ops 135607518 # Number of ops (including micro ops) simulated +host_inst_rate 556763 # Simulator instruction rate (inst/s) +host_op_rate 671289 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14374691055 # Simulator tick rate (ticks/s) +host_mem_usage 583268 # Number of bytes of host memory used +host_seconds 202.01 # Real time elapsed on the host +sim_insts 112469247 # Number of instructions simulated +sim_ops 135604005 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 555940 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4011424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 555300 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4008928 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 630912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4981252 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 630848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4995972 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10181128 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 555940 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 630912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1186852 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7592512 # Number of bytes written to this memory +system.physmem.bytes_read::total 10192648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 555300 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 630848 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1186148 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7610112 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 7610036 # Number of bytes written to this memory +system.physmem.bytes_written::total 7627636 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 17140 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 63197 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 17130 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 63158 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9858 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 77833 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9857 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 78063 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168053 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118633 # Number of write requests responded to by this memory +system.physmem.num_reads::total 168233 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118908 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123014 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123289 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 66 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 191448 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1381405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 191234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1380596 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 110 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 217266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1715382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 217252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1720514 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3506051 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 191448 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 217266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 408713 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2614615 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3510147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 191234 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 217252 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 408486 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2620772 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6032 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2620650 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2614615 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2626807 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2620772 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 191448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1387437 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 191234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1386628 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 110 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 217266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1715385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 217252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1720517 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6126701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168053 # Number of read requests accepted -system.physmem.writeReqs 123014 # Number of write requests accepted -system.physmem.readBursts 168053 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123014 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10747264 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8128 # Total number of bytes read from write queue -system.physmem.bytesWritten 7624000 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10181128 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7610036 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 127 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6136954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168233 # Number of read requests accepted +system.physmem.writeReqs 123289 # Number of write requests accepted +system.physmem.readBursts 168233 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123289 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10759040 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7872 # Total number of bytes read from write queue +system.physmem.bytesWritten 7641600 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10192648 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7627636 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 123 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9950 # Per bank write bursts -system.physmem.perBankRdBursts::1 9635 # Per bank write bursts -system.physmem.perBankRdBursts::2 10758 # Per bank write bursts -system.physmem.perBankRdBursts::3 10205 # Per bank write bursts -system.physmem.perBankRdBursts::4 18891 # Per bank write bursts -system.physmem.perBankRdBursts::5 10113 # Per bank write bursts -system.physmem.perBankRdBursts::6 10004 # Per bank write bursts -system.physmem.perBankRdBursts::7 10172 # Per bank write bursts -system.physmem.perBankRdBursts::8 9614 # Per bank write bursts -system.physmem.perBankRdBursts::9 10312 # Per bank write bursts -system.physmem.perBankRdBursts::10 9759 # Per bank write bursts -system.physmem.perBankRdBursts::11 9150 # Per bank write bursts -system.physmem.perBankRdBursts::12 10005 # Per bank write bursts -system.physmem.perBankRdBursts::13 10185 # Per bank write bursts -system.physmem.perBankRdBursts::14 9904 # Per bank write bursts -system.physmem.perBankRdBursts::15 9269 # Per bank write bursts -system.physmem.perBankWrBursts::0 7437 # Per bank write bursts -system.physmem.perBankWrBursts::1 7207 # Per bank write bursts -system.physmem.perBankWrBursts::2 8535 # Per bank write bursts -system.physmem.perBankWrBursts::3 7773 # Per bank write bursts -system.physmem.perBankWrBursts::4 7341 # Per bank write bursts -system.physmem.perBankWrBursts::5 7352 # Per bank write bursts -system.physmem.perBankWrBursts::6 7319 # Per bank write bursts -system.physmem.perBankWrBursts::7 7510 # Per bank write bursts -system.physmem.perBankWrBursts::8 7314 # Per bank write bursts -system.physmem.perBankWrBursts::9 7939 # Per bank write bursts -system.physmem.perBankWrBursts::10 7417 # Per bank write bursts -system.physmem.perBankWrBursts::11 7018 # Per bank write bursts -system.physmem.perBankWrBursts::12 7499 # Per bank write bursts -system.physmem.perBankWrBursts::13 7483 # Per bank write bursts -system.physmem.perBankWrBursts::14 7310 # Per bank write bursts -system.physmem.perBankWrBursts::15 6671 # Per bank write bursts +system.physmem.perBankRdBursts::0 9792 # Per bank write bursts +system.physmem.perBankRdBursts::1 9632 # Per bank write bursts +system.physmem.perBankRdBursts::2 10568 # Per bank write bursts +system.physmem.perBankRdBursts::3 10165 # Per bank write bursts +system.physmem.perBankRdBursts::4 19064 # Per bank write bursts +system.physmem.perBankRdBursts::5 10189 # Per bank write bursts +system.physmem.perBankRdBursts::6 9914 # Per bank write bursts +system.physmem.perBankRdBursts::7 10188 # Per bank write bursts +system.physmem.perBankRdBursts::8 9623 # Per bank write bursts +system.physmem.perBankRdBursts::9 10301 # Per bank write bursts +system.physmem.perBankRdBursts::10 9773 # Per bank write bursts +system.physmem.perBankRdBursts::11 9030 # Per bank write bursts +system.physmem.perBankRdBursts::12 10231 # Per bank write bursts +system.physmem.perBankRdBursts::13 10348 # Per bank write bursts +system.physmem.perBankRdBursts::14 10027 # Per bank write bursts +system.physmem.perBankRdBursts::15 9265 # Per bank write bursts +system.physmem.perBankWrBursts::0 7302 # Per bank write bursts +system.physmem.perBankWrBursts::1 7227 # Per bank write bursts +system.physmem.perBankWrBursts::2 8385 # Per bank write bursts +system.physmem.perBankWrBursts::3 7804 # Per bank write bursts +system.physmem.perBankWrBursts::4 7523 # Per bank write bursts +system.physmem.perBankWrBursts::5 7419 # Per bank write bursts +system.physmem.perBankWrBursts::6 7240 # Per bank write bursts +system.physmem.perBankWrBursts::7 7527 # Per bank write bursts +system.physmem.perBankWrBursts::8 7332 # Per bank write bursts +system.physmem.perBankWrBursts::9 7919 # Per bank write bursts +system.physmem.perBankWrBursts::10 7392 # Per bank write bursts +system.physmem.perBankWrBursts::11 6920 # Per bank write bursts +system.physmem.perBankWrBursts::12 7696 # Per bank write bursts +system.physmem.perBankWrBursts::13 7626 # Per bank write bursts +system.physmem.perBankWrBursts::14 7423 # Per bank write bursts +system.physmem.perBankWrBursts::15 6665 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 6 # Number of times write queue was full causing retry -system.physmem.totGap 2903872984500 # Total gap between requests +system.physmem.totGap 2903766416500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 158481 # Read request sizes (log2) +system.physmem.readPktSize::6 158661 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118633 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167142 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 249 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118908 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 167323 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 527 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 248 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -166,185 +166,182 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 184 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 177 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6024 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 115 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58746 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 312.722568 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 182.930860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.291475 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21602 36.77% 36.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14804 25.20% 61.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5471 9.31% 71.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3214 5.47% 76.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2508 4.27% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1574 2.68% 83.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 969 1.65% 85.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1055 1.80% 87.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7549 12.85% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58746 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5821 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.848136 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 550.683804 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5819 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::43 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58622 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 313.885163 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.743064 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.844549 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21439 36.57% 36.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14755 25.17% 61.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5499 9.38% 71.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3328 5.68% 76.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2438 4.16% 80.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1485 2.53% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1033 1.76% 85.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1043 1.78% 87.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7602 12.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58622 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5829 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.840110 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 550.258858 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5827 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5821 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5821 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.464697 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.574066 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.714843 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 19 0.33% 0.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 13 0.22% 0.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 4 0.07% 0.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 16 0.27% 0.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4888 83.97% 84.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 79 1.36% 86.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 98 1.68% 87.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 80 1.37% 89.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 289 4.96% 94.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 57 0.98% 95.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 18 0.31% 95.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 15 0.26% 95.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 14 0.24% 96.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 4 0.07% 96.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.10% 96.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.05% 96.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 159 2.73% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.07% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.07% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 2 0.03% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 6 0.10% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.05% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.03% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.07% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 6 0.10% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 12 0.21% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.05% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.05% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5821 # Writes before turning the bus around for reads -system.physmem.totQLat 1465999500 # Total ticks spent queuing -system.physmem.totMemAccLat 4614612000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 839630000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8730.03 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5829 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5829 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.483788 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.629212 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.311611 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 18 0.31% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 13 0.22% 0.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 4 0.07% 0.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 13 0.22% 0.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4877 83.67% 84.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 64 1.10% 85.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 110 1.89% 87.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 91 1.56% 89.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 303 5.20% 94.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 58 1.00% 95.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 20 0.34% 95.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 11 0.19% 95.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 11 0.19% 95.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.10% 96.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.05% 96.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.12% 96.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 162 2.78% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.05% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 2 0.03% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.05% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 10 0.17% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.05% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 5 0.09% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 4 0.07% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.19% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.07% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5829 # Writes before turning the bus around for reads +system.physmem.totQLat 1480605750 # Total ticks spent queuing +system.physmem.totMemAccLat 4632668250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 840550000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8807.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27480.03 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.70 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27557.36 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.62 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.63 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.35 # Average write queue length when enqueuing -system.physmem.readRowHits 138262 # Number of row buffer hits during reads -system.physmem.writeRowHits 90042 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.59 # Row buffer hit rate for writes -system.physmem.avgGap 9976647.94 # Average gap between requests -system.physmem.pageHitRate 79.53 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 228894120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 124892625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 699878400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 391871520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 189666434880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 87151382055 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1665871386000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1944134739600 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.498637 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2771164197500 # Time in different power states -system.physmem_0.memoryStateTime::REF 96966480000 # Time in different power states +system.physmem.avgWrQLen 12.78 # Average write queue length when enqueuing +system.physmem.readRowHits 138260 # Number of row buffer hits during reads +system.physmem.writeRowHits 90627 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.24 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.90 # Row buffer hit rate for writes +system.physmem.avgGap 9960711.08 # Average gap between requests +system.physmem.pageHitRate 79.61 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 228296880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 124566750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 698193600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 391566960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 189659823600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 87381059850 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1665609181500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1944092689140 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.507494 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2770726429250 # Time in different power states +system.physmem_0.memoryStateTime::REF 96963100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35735947500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 36075874500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 215225640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 117434625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 609936600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 380058480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 189666434880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85517443710 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1667304665250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1943811199185 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.387220 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2773570809500 # Time in different power states -system.physmem_1.memoryStateTime::REF 96966480000 # Time in different power states +system.physmem_1.actEnergy 214885440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 117249000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 613056600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 382145040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 189659823600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85737221460 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1667051145000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1943775526140 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.398269 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2773140927250 # Time in different power states +system.physmem_1.memoryStateTime::REF 96963100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33335958000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33662652750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -357,9 +354,9 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 7 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -367,7 +364,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -397,59 +394,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 6853 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 6853 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2243 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4610 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 6853 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 6853 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 6853 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 5823 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12916.709600 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11256.445833 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6610.788578 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-8191 1557 26.74% 26.74% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::8192-16383 2962 50.87% 77.61% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-24575 1237 21.24% 98.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::24576-32767 65 1.12% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 6919 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 6919 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2260 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4659 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 6919 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 6919 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 6919 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 5896 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 11249.830393 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9924.741038 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5679.920137 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-8191 1980 33.58% 33.58% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::8192-16383 3242 54.99% 88.57% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-24575 672 11.40% 99.97% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::81920-90111 2 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 5823 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 5896 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 941563500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 941563500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 941563500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3601 61.84% 61.84% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 2222 38.16% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5823 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6853 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 3659 62.06% 62.06% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 2237 37.94% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5896 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6919 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6853 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5823 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6919 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5896 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5823 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 12676 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5896 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 12815 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12198930 # DTB read hits -system.cpu0.dtb.read_misses 5954 # DTB read misses -system.cpu0.dtb.write_hits 9656685 # DTB write hits -system.cpu0.dtb.write_misses 899 # DTB write misses +system.cpu0.dtb.read_hits 12202364 # DTB read hits +system.cpu0.dtb.read_misses 6026 # DTB read misses +system.cpu0.dtb.write_hits 9652425 # DTB write hits +system.cpu0.dtb.write_misses 893 # DTB write misses system.cpu0.dtb.flush_tlb 2938 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 472 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 471 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 4524 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 4544 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 886 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 884 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 224 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12204884 # DTB read accesses -system.cpu0.dtb.write_accesses 9657584 # DTB write accesses +system.cpu0.dtb.perms_faults 229 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12208390 # DTB read accesses +system.cpu0.dtb.write_accesses 9653318 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21855615 # DTB hits -system.cpu0.dtb.misses 6853 # DTB misses -system.cpu0.dtb.accesses 21862468 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 21854789 # DTB hits +system.cpu0.dtb.misses 6919 # DTB misses +system.cpu0.dtb.accesses 21861708 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -479,524 +475,523 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 3536 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3536 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 846 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2690 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3536 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3536 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3536 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2700 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 13506.851852 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11618.794043 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 7003.469294 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 708 26.22% 26.22% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1289 47.74% 73.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 690 25.56% 99.52% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 12 0.44% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 3587 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3587 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 847 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2740 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3587 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3587 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3587 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2736 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 11841.008772 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 10111.838069 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6604.852208 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 961 35.12% 35.12% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1280 46.78% 81.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 494 18.06% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2700 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2736 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 941232000 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 941232000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 941232000 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1854 68.67% 68.67% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 846 31.33% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2700 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 1889 69.04% 69.04% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 847 30.96% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2736 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3536 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3536 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3587 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3587 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2700 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2700 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6236 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 57475685 # ITB inst hits -system.cpu0.itb.inst_misses 3536 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2736 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2736 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6323 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 57467408 # ITB inst hits +system.cpu0.itb.inst_misses 3587 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 2938 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 472 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 471 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2662 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2707 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 57479221 # ITB inst accesses -system.cpu0.itb.hits 57475685 # DTB hits -system.cpu0.itb.misses 3536 # DTB misses -system.cpu0.itb.accesses 57479221 # DTB accesses -system.cpu0.numPwrStateTransitions 3084 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1542 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1561186798.199741 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23928880440.151150 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1496 97.02% 97.02% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 41 2.66% 99.68% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 57470995 # ITB inst accesses +system.cpu0.itb.hits 57467408 # DTB hits +system.cpu0.itb.misses 3587 # DTB misses +system.cpu0.itb.accesses 57470995 # DTB accesses +system.cpu0.numPwrStateTransitions 3112 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1556 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1547130345.667738 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23821374889.614185 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1511 97.11% 97.11% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 40 2.57% 99.68% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.06% 99.74% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.06% 99.81% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 3 0.19% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499963822636 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1542 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 496523303676 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2407350042824 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 2904047101 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 499963941844 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1556 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 496431960641 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2407334817859 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 2904051149 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3031 # number of quiesce instructions executed -system.cpu0.committedInsts 55938514 # Number of instructions committed -system.cpu0.committedOps 67284601 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 59484081 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5858 # Number of float alu accesses -system.cpu0.num_func_calls 4937125 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7562453 # number of instructions that are conditional controls -system.cpu0.num_int_insts 59484081 # number of integer instructions -system.cpu0.num_fp_insts 5858 # number of float instructions -system.cpu0.num_int_register_reads 108136226 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41105221 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4501 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1358 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 243174527 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 25739828 # number of times the CC registers were written -system.cpu0.num_mem_refs 22504110 # number of memory refs -system.cpu0.num_load_insts 12361128 # Number of load instructions -system.cpu0.num_store_insts 10142982 # Number of store instructions -system.cpu0.num_idle_cycles 2686495929.504804 # Number of idle cycles -system.cpu0.num_busy_cycles 217551171.495196 # Number of busy cycles -system.cpu0.not_idle_fraction 0.074913 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.925087 # Percentage of idle cycles -system.cpu0.Branches 12909756 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2203 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46277611 67.22% 67.22% # Class of executed instruction -system.cpu0.op_class::IntMult 59345 0.09% 67.31% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4401 0.01% 67.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.31% # Class of executed instruction -system.cpu0.op_class::MemRead 12361128 17.95% 85.27% # Class of executed instruction -system.cpu0.op_class::MemWrite 10142982 14.73% 100.00% # Class of executed instruction +system.cpu0.committedInsts 55929149 # Number of instructions committed +system.cpu0.committedOps 67264870 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 59473158 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5736 # Number of float alu accesses +system.cpu0.num_func_calls 4933883 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7554856 # number of instructions that are conditional controls +system.cpu0.num_int_insts 59473158 # number of integer instructions +system.cpu0.num_fp_insts 5736 # number of float instructions +system.cpu0.num_int_register_reads 108126384 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41101072 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4447 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1290 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 243127326 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 25718334 # number of times the CC registers were written +system.cpu0.num_mem_refs 22505711 # number of memory refs +system.cpu0.num_load_insts 12365331 # Number of load instructions +system.cpu0.num_store_insts 10140380 # Number of store instructions +system.cpu0.num_idle_cycles 2686639067.561983 # Number of idle cycles +system.cpu0.num_busy_cycles 217412081.438017 # Number of busy cycles +system.cpu0.not_idle_fraction 0.074865 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.925135 # Percentage of idle cycles +system.cpu0.Branches 12899208 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2204 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 46257774 67.21% 67.21% # Class of executed instruction +system.cpu0.op_class::IntMult 59366 0.09% 67.30% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4384 0.01% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::MemRead 12365331 17.97% 85.27% # Class of executed instruction +system.cpu0.op_class::MemWrite 10140380 14.73% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 68847670 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 819197 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.827216 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43241786 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 819709 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.752606 # Average number of references to valid blocks. +system.cpu0.op_class::total 68829439 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 818958 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.827210 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43240509 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 819470 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.766433 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1013369500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 311.277381 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 200.549835 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.607964 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.391699 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 311.506673 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 200.320536 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.608411 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.391251 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999663 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 366 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177132718 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177132718 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 11492240 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11624339 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23116579 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9270030 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9555793 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18825823 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200250 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 192633 # number of SoftPFReq hits +system.cpu0.dcache.tags.tag_accesses 177126395 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 177126395 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 11494682 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 11621262 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23115944 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 9265643 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 9559561 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18825204 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200295 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 192588 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 392883 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 225114 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 218358 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 443472 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 233001 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 227267 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460268 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20762270 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 21180132 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41942402 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20962520 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21372765 # number of overall hits -system.cpu0.dcache.overall_hits::total 42335285 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 199687 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 200107 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 399794 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 142706 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 155941 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 298647 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 56913 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61284 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 118197 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10855 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11725 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22580 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 225246 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 218223 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 443469 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 233094 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 227153 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 460247 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 20760325 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 21180823 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41941148 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 20960620 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 21373411 # number of overall hits +system.cpu0.dcache.overall_hits::total 42334031 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 200460 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 199220 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 399680 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 142763 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 155795 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 298558 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 57022 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61158 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 118180 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10816 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11741 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22557 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 342393 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 356048 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 698441 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 399306 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 417332 # number of overall misses -system.cpu0.dcache.overall_misses::total 816638 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2969454500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2995849000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5965303500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5762218500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6859127500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 12621346000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 131663000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 147690500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 279353500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 343223 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 355015 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 698238 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 400245 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 416173 # number of overall misses +system.cpu0.dcache.overall_misses::total 816418 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2980896000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2983113000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5964009000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5727893000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6844158000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 12572051000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 131628000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 147568500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 279196500 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 166000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 166000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8731673000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 9854976500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 18586649500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8731673000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 9854976500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 18586649500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 11691927 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 11824446 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23516373 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9412736 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9711734 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19124470 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 257163 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 253917 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511080 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 235969 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 230083 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 466052 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 233003 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 227267 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 460270 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 21104663 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 21536180 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42640843 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 21361826 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 21790097 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43151923 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.017079 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.016923 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.017001 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015161 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.016057 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.015616 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.221311 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.241354 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.231269 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046002 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.050960 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048450 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_latency::cpu0.data 8708789000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 9827271000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 18536060000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8708789000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 9827271000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 18536060000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 11695142 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 11820482 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23515624 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 9408406 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 9715356 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 19123762 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 257317 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 253746 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 511063 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 236062 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 229964 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 466026 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 233096 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 227153 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 460249 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 21103548 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 21535838 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42639386 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 21360865 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 21789584 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43150449 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.017140 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.016854 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.016996 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015174 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.016036 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.015612 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.221602 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.241021 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.231244 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045818 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.051056 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048403 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000009 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016224 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016533 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.016380 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018693 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.019152 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.018925 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14870.544903 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14971.235389 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14920.943036 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40378.249688 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 43985.401530 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42261.753843 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12129.249194 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12596.204691 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12371.722764 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016264 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016485 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016375 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018737 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.019100 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.018920 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14870.278360 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14973.963457 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14921.960068 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40121.691194 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 43930.536924 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42109.241755 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12169.748521 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12568.648326 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12377.377311 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 83000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25501.902784 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27678.786287 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26611.624318 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21867.121957 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23614.236387 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 22759.961574 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25373.558882 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27681.283889 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26546.908074 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21758.645330 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23613.427589 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22704.129502 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 683616 # number of writebacks -system.cpu0.dcache.writebacks::total 683616 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 284 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 384 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 668 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7115 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 6934 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14049 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 284 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 384 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 668 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 284 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 384 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 668 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 199403 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 199723 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 399126 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 142706 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 155941 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 298647 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 56023 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 60170 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 116193 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 3740 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4791 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8531 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 683415 # number of writebacks +system.cpu0.dcache.writebacks::total 683415 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 291 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 383 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 674 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7100 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 6929 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14029 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 291 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 383 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 674 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 291 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 383 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 674 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 200169 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 198837 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 399006 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 142763 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 155795 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 298558 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 56128 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 60039 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 116167 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 3716 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4812 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8528 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 342109 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 355664 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 697773 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 398132 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 415834 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 813966 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14422 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16716 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.demand_mshr_misses::cpu0.data 342932 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 354632 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 697564 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 399060 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 414671 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 813731 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14396 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16742 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15099 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 12490 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15072 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 12517 # number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 29521 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 29206 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 29468 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 29259 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2764008500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2789776500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5553785000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5619512500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6703186500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12322699000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 725372500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 799789000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1525161500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 48172500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 61674000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 109846500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2774512000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2777407500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5551919500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5585130000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6688363000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12273493000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 725295500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 799071500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1524367000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 47708500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 61547000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 109255500 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 164000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8383521000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9492963000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 17876484000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9108893500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10292752000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 19401645500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2833740000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3447478500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6281218500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2833740000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3447478500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6281218500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017055 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016891 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016972 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015161 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016057 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015616 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.217850 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.236967 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227348 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.015850 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020823 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018305 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8359642000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9465770500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 17825412500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9084937500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10264842000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 19349779500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2828734500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3452490500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6281225000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2828734500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3452490500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6281225000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017116 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016821 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016968 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015174 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016036 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015612 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.218128 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.236611 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227305 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.015742 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020925 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018299 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016210 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016515 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016364 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018638 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019084 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018863 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13861.418835 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13968.228496 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13914.866483 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39378.249688 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42985.401530 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41261.753843 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12947.762526 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13292.155559 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13126.104843 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12880.347594 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12872.886662 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12876.157543 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016250 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016467 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016360 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018682 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019031 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018858 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13860.847584 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13968.262949 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13914.375974 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39121.691194 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42930.536924 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41109.241755 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12922.168971 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13309.207349 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13122.203380 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12838.670614 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12790.315877 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12811.386023 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 82000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24505.409095 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26690.817738 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25619.340387 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22879.079049 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24752.069335 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23835.940936 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196487.311053 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 206238.244795 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201721.963517 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95990.650723 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 118040.077381 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 106956.229673 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1698024 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.728400 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 113871338 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1698536 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.040874 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 25838751500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 417.467812 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 93.260588 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.815367 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.182150 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24376.966862 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26691.811512 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25553.802232 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22765.843482 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24754.183437 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23779.086086 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196494.477633 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 206217.327679 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201722.172265 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95993.433555 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 117997.556307 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 106956.340355 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1697713 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.728355 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 113868966 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1698225 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.051755 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 25837690500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 418.792461 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 91.935894 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.817954 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.179562 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.997516 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 117268422 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 117268422 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 56621226 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 57250112 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 113871338 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 56621226 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 57250112 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 113871338 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 56621226 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 57250112 # number of overall hits -system.cpu0.icache.overall_hits::total 113871338 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 854459 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 844083 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1698542 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 854459 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 844083 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1698542 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 854459 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 844083 # number of overall misses -system.cpu0.icache.overall_misses::total 1698542 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11710586000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11696136000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 23406722000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11710586000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 11696136000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 23406722000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11710586000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 11696136000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 23406722000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 57475685 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 58094195 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 115569880 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 57475685 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 58094195 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 115569880 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 57475685 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 58094195 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 115569880 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014866 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014530 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014697 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014866 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014530 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014697 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014866 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014530 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014697 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13705.263798 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13856.618366 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13780.478787 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13705.263798 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13856.618366 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13780.478787 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13705.263798 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13856.618366 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13780.478787 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 117265428 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 117265428 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 56611241 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 57257725 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 113868966 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 56611241 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 57257725 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 113868966 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 56611241 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 57257725 # number of overall hits +system.cpu0.icache.overall_hits::total 113868966 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 856167 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 842064 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1698231 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 856167 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 842064 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1698231 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 856167 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 842064 # number of overall misses +system.cpu0.icache.overall_misses::total 1698231 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11730872000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11666474000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 23397346000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11730872000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 11666474000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 23397346000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11730872000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 11666474000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 23397346000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 57467408 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 58099789 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 115567197 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 57467408 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 58099789 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 115567197 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 57467408 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 58099789 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 115567197 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014898 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014493 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014695 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014898 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014493 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014695 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014898 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014493 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014695 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13701.616624 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13854.616751 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13777.481391 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13701.616624 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13854.616751 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13777.481391 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13701.616624 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13854.616751 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13777.481391 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1698024 # number of writebacks -system.cpu0.icache.writebacks::total 1698024 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 854459 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 844083 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1698542 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 854459 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 844083 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1698542 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 854459 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 844083 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1698542 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1697713 # number of writebacks +system.cpu0.icache.writebacks::total 1697713 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 856167 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 842064 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1698231 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 856167 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 842064 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1698231 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 856167 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 842064 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1698231 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10856127000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10852053000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 21708180000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10856127000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10852053000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 21708180000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10856127000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10852053000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 21708180000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10874705000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10824410000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 21699115000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10874705000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10824410000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 21699115000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10874705000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10824410000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 21699115000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 687287000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 687287000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 687287000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 687287000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014866 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014530 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014697 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014866 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014530 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014697 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014866 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014530 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014697 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12705.263798 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12856.618366 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12780.478787 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12705.263798 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12856.618366 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12780.478787 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12705.263798 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12856.618366 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12780.478787 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014898 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014493 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014695 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014898 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014493 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014695 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014898 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014493 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014695 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12701.616624 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12854.616751 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12777.481391 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12701.616624 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12854.616751 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12777.481391 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12701.616624 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12854.616751 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12777.481391 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 76179.006872 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 76179.006872 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 76179.006872 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 76179.006872 # average overall mshr uncacheable latency -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1026,59 +1021,59 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 6542 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6542 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1888 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4654 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 6542 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6542 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6542 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5408 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12327.385355 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10604.258699 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7039.389746 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 4342 80.29% 80.29% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 1062 19.64% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 6570 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6570 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1884 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4686 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 6570 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6570 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6570 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5429 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 10846.104255 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9462.707245 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6203.102162 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 4870 89.70% 89.70% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 555 10.22% 99.93% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::81920-98303 2 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::98304-114687 1 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::163840-180223 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5408 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5429 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 1000192500 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000192500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000192500 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3546 65.57% 65.57% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1862 34.43% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5408 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6542 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 3569 65.74% 65.74% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1860 34.26% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5429 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6570 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6542 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5408 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6570 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5429 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5408 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 11950 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5429 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 11999 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12325162 # DTB read hits -system.cpu1.dtb.read_misses 5607 # DTB read misses -system.cpu1.dtb.write_hits 9951712 # DTB write hits -system.cpu1.dtb.write_misses 935 # DTB write misses +system.cpu1.dtb.read_hits 12320936 # DTB read hits +system.cpu1.dtb.read_misses 5629 # DTB read misses +system.cpu1.dtb.write_hits 9955242 # DTB write hits +system.cpu1.dtb.write_misses 941 # DTB write misses system.cpu1.dtb.flush_tlb 2932 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 445 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3942 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 3977 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 892 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 890 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 221 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12330769 # DTB read accesses -system.cpu1.dtb.write_accesses 9952647 # DTB write accesses +system.cpu1.dtb.perms_faults 216 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12326565 # DTB read accesses +system.cpu1.dtb.write_accesses 9956183 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 22276874 # DTB hits -system.cpu1.dtb.misses 6542 # DTB misses -system.cpu1.dtb.accesses 22283416 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 22276178 # DTB hits +system.cpu1.dtb.misses 6570 # DTB misses +system.cpu1.dtb.accesses 22282748 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1108,135 +1103,134 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 3192 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3192 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 694 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2498 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 3192 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3192 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3192 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2373 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12622.418879 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10730.148321 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 7022.179008 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-8191 765 32.24% 32.24% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-16383 1087 45.81% 78.04% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-24575 508 21.41% 99.45% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-32767 12 0.51% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 3169 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3169 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 693 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2476 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 3169 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3169 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3169 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2365 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11411.839323 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 9688.359834 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6654.367944 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 919 38.86% 38.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 1055 44.61% 83.47% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 390 16.49% 99.96% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2373 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2365 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000178000 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000178000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000178000 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1679 70.75% 70.75% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 694 29.25% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2373 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 1672 70.70% 70.70% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 693 29.30% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2365 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3192 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3192 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3169 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3169 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2373 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2373 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 5565 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 58094195 # ITB inst hits -system.cpu1.itb.inst_misses 3192 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2365 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2365 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 5534 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 58099789 # ITB inst hits +system.cpu1.itb.inst_misses 3169 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 2932 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 445 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2321 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2313 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 58097387 # ITB inst accesses -system.cpu1.itb.hits 58094195 # DTB hits -system.cpu1.itb.misses 3192 # DTB misses -system.cpu1.itb.accesses 58097387 # DTB accesses -system.cpu1.numPwrStateTransitions 2962 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 1481 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1715351950.690074 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 49199578788.066856 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1468 99.12% 99.12% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 58102958 # ITB inst accesses +system.cpu1.itb.hits 58099789 # DTB hits +system.cpu1.itb.misses 3169 # DTB misses +system.cpu1.itb.accesses 58102958 # DTB accesses +system.cpu1.numPwrStateTransitions 2934 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 1467 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1731723114.831629 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 49433684554.113754 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1454 99.11% 99.11% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1000-5e+10 10 0.68% 99.80% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.07% 99.86% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.07% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::overflows 1 0.07% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 1799694213001 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 1481 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 363437107528 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2540436238972 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 2903699592 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 1799695172501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 1467 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 363328969042 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2540437809458 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 2903482408 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 56533338 # Number of instructions committed -system.cpu1.committedOps 68322917 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 60427301 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5303 # Number of float alu accesses -system.cpu1.num_func_calls 4958033 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7669947 # number of instructions that are conditional controls -system.cpu1.num_int_insts 60427301 # number of integer instructions -system.cpu1.num_fp_insts 5303 # number of float instructions -system.cpu1.num_int_register_reads 109946331 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41554232 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3948 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1358 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 246640123 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26160975 # number of times the CC registers were written -system.cpu1.num_mem_refs 22909081 # number of memory refs -system.cpu1.num_load_insts 12485523 # Number of load instructions -system.cpu1.num_store_insts 10423558 # Number of store instructions -system.cpu1.num_idle_cycles 2692719592.304736 # Number of idle cycles -system.cpu1.num_busy_cycles 210979999.695264 # Number of busy cycles -system.cpu1.not_idle_fraction 0.072659 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.927341 # Percentage of idle cycles -system.cpu1.Branches 13011724 # Number of branches fetched -system.cpu1.op_class::No_OpClass 134 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 46912423 67.13% 67.13% # Class of executed instruction -system.cpu1.op_class::IntMult 55213 0.08% 67.21% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.21% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4054 0.01% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::MemRead 12485523 17.87% 85.08% # Class of executed instruction -system.cpu1.op_class::MemWrite 10423558 14.92% 100.00% # Class of executed instruction +system.cpu1.committedInsts 56540098 # Number of instructions committed +system.cpu1.committedOps 68339135 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 60434834 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5361 # Number of float alu accesses +system.cpu1.num_func_calls 4961252 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7677275 # number of instructions that are conditional controls +system.cpu1.num_int_insts 60434834 # number of integer instructions +system.cpu1.num_fp_insts 5361 # number of float instructions +system.cpu1.num_int_register_reads 109950382 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41555809 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3938 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1426 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 246673704 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26181408 # number of times the CC registers were written +system.cpu1.num_mem_refs 22905703 # number of memory refs +system.cpu1.num_load_insts 12480329 # Number of load instructions +system.cpu1.num_store_insts 10425374 # Number of store instructions +system.cpu1.num_idle_cycles 2692560639.134501 # Number of idle cycles +system.cpu1.num_busy_cycles 210921768.865499 # Number of busy cycles +system.cpu1.not_idle_fraction 0.072644 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.927356 # Percentage of idle cycles +system.cpu1.Branches 13021982 # Number of branches fetched +system.cpu1.op_class::No_OpClass 133 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 46930380 67.14% 67.14% # Class of executed instruction +system.cpu1.op_class::IntMult 55203 0.08% 67.22% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4061 0.01% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::MemRead 12480329 17.86% 85.08% # Class of executed instruction +system.cpu1.op_class::MemWrite 10425374 14.92% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69880905 # Class of executed instruction -system.iobus.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states +system.cpu1.op_class::total 69895480 # Class of executed instruction +system.iobus.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1287,7 +1281,7 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46332000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46333500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 98000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1299,7 +1293,7 @@ system.iobus.reqLayer4.occupancy 15500 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 96000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 643000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 642500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1321,32 +1315,32 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6280000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6283500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36460500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36461000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187670847 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187683390 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.079286 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.078668 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 309377087000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.079286 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067455 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067455 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 309389193000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.078668 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067417 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067417 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328122 # Number of tag accesses system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses system.iocache.ReadReq_misses::total 234 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -1355,14 +1349,14 @@ system.iocache.demand_misses::realview.ide 36458 # system.iocache.demand_misses::total 36458 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36458 # number of overall misses system.iocache.overall_misses::total 36458 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29588377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29588377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4277963470 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4277963470 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4307551847 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4307551847 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4307551847 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4307551847 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28897377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28897377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4277880013 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4277880013 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4306777390 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4306777390 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4306777390 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4306777390 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1379,14 +1373,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 126446.055556 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126446.055556 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118097.489786 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118097.489786 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118151.073756 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118151.073756 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118151.073756 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118151.073756 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 123493.064103 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123493.064103 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118095.185871 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118095.185871 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118129.831313 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118129.831313 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118129.831313 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118129.831313 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1403,14 +1397,14 @@ system.iocache.demand_mshr_misses::realview.ide 36458 system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17888377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17888377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2464657470 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2464657470 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2482545847 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2482545847 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2482545847 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2482545847 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17197377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17197377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2464564473 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2464564473 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2481761850 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2481761850 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2481761850 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2481761850 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1419,540 +1413,537 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76446.055556 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76446.055556 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68039.351535 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68039.351535 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68093.308657 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68093.308657 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68093.308657 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68093.308657 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 88931 # number of replacements -system.l2c.tags.tagsinuse 64921.532624 # Cycle average of tags in use -system.l2c.tags.total_refs 4554640 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 154190 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 29.539140 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50439.017527 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.855331 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000489 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4116.974919 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2621.771037 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.860553 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.964520 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5479.024389 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2258.063860 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.769638 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73493.064103 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 73493.064103 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68036.784259 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68036.784259 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68071.804542 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68071.804542 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68071.804542 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68071.804542 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 89096 # number of replacements +system.l2c.tags.tagsinuse 65019.507372 # Cycle average of tags in use +system.l2c.tags.total_refs 4852978 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 154522 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 31.406389 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 142568433000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.855347 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999676 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4118.843503 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 26763.314787 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.933925 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.964521 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5511.371420 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 28618.224194 # Average occupied blocks per requestor system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000044 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.062820 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.040005 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.062849 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.408376 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.083603 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.034455 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.990624 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65253 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2127 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6981 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56097 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.995682 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 40592832 # Number of tag accesses -system.l2c.tags.data_accesses 40592832 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 6060 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3335 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5248 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2709 # number of ReadReq hits -system.l2c.ReadReq_hits::total 17352 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 683616 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 683616 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1666963 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1666963 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 11 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 24 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 83335 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 82122 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 165457 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 846325 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 834210 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1680535 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 253515 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 258250 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 511765 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6060 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3335 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 846325 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 336850 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5248 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2709 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 834210 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 340372 # number of demand (read+write) hits -system.l2c.demand_hits::total 2375109 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6060 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3335 # number of overall hits -system.l2c.overall_hits::cpu0.inst 846325 # number of overall hits -system.l2c.overall_hits::cpu0.data 336850 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5248 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2709 # number of overall hits -system.l2c.overall_hits::cpu1.inst 834210 # number of overall hits -system.l2c.overall_hits::cpu1.data 340372 # number of overall hits -system.l2c.overall_hits::total 2375109 # number of overall hits +system.l2c.tags.occ_percent::cpu1.inst 0.084097 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.436679 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.992119 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65419 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4596 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 60809 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.998215 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 40264611 # Number of tag accesses +system.l2c.tags.data_accesses 40264611 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.l2c.ReadReq_hits::cpu0.dtb.walker 5009 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2735 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 4338 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 2269 # number of ReadReq hits +system.l2c.ReadReq_hits::total 14351 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 683415 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 683415 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 1666661 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1666661 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 1319 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1420 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2739 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 84291 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 82554 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 166845 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 848044 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 832191 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1680235 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 254366 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 257240 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 511606 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 5009 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 2735 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 848044 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 338657 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 4338 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 2269 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 832191 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 339794 # number of demand (read+write) hits +system.l2c.demand_hits::total 2373037 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 5009 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 2735 # number of overall hits +system.l2c.overall_hits::cpu0.inst 848044 # number of overall hits +system.l2c.overall_hits::cpu0.data 338657 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 4338 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 2269 # number of overall hits +system.l2c.overall_hits::cpu1.inst 832191 # number of overall hits +system.l2c.overall_hits::cpu1.data 339794 # number of overall hits +system.l2c.overall_hits::total 2373037 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::total 10 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1333 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1402 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2735 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 10 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 11 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 21 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 58027 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 72404 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130431 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 8123 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 9860 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 17983 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 5651 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 6434 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 12085 # number of ReadSharedReq misses +system.l2c.ReadExReq_misses::cpu0.data 57143 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 71810 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 128953 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 8113 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 9859 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 17972 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 5647 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 6448 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 12095 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 3 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 8123 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 63678 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 8113 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 62790 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 9860 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 78838 # number of demand (read+write) misses -system.l2c.demand_misses::total 160509 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 9859 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 78258 # number of demand (read+write) misses +system.l2c.demand_misses::total 159030 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 3 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 8123 # number of overall misses -system.l2c.overall_misses::cpu0.data 63678 # number of overall misses +system.l2c.overall_misses::cpu0.inst 8113 # number of overall misses +system.l2c.overall_misses::cpu0.data 62790 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 5 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 9860 # number of overall misses -system.l2c.overall_misses::cpu1.data 78838 # number of overall misses -system.l2c.overall_misses::total 160509 # number of overall misses +system.l2c.overall_misses::cpu1.inst 9859 # number of overall misses +system.l2c.overall_misses::cpu1.data 78258 # number of overall misses +system.l2c.overall_misses::total 159030 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 251000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 84000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 433000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 83500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 851500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 321500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 201500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 523000 # number of UpgradeReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 84000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 852000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 288000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 321500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 609500 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu0.data 161000 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 161000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4489796500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5564391000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10054187500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 658512500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 797268000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1455780500 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 478395500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 533868000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 1012263500 # number of ReadSharedReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4469976500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5570866000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10040842500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 656455500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 793875000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1450330500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 478141500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 532781500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 1010923000 # number of ReadSharedReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 251000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 84000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 658512500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 4968192000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 656455500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 4948118000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 433000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 83500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 797268000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 6098259000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 12523083000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 84000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 793875000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 6103647500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 12502948000 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 251000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 84000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 658512500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 4968192000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 656455500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 4948118000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 433000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 83500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 797268000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 6098259000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 12523083000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 6063 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3336 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5253 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 2710 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 17362 # number of ReadReq accesses(hits+misses) -system.l2c.WritebackDirty_accesses::writebacks 683616 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 683616 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 1666963 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 1666963 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1344 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1415 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2759 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu1.itb.walker 84000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 793875000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 6103647500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 12502948000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 5012 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 2736 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 4343 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 2270 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 14361 # number of ReadReq accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 683415 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 683415 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 1666661 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 1666661 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1329 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1431 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2760 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 141362 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 154526 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 295888 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 854448 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 844070 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1698518 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 259166 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 264684 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 523850 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 6063 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3336 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 854448 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 400528 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5253 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 2710 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 844070 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 419210 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2535618 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 6063 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3336 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 854448 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 400528 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5253 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 2710 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 844070 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 419210 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2535618 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000495 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000300 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000952 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000369 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.000576 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.991815 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990813 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.991301 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 141434 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 154364 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295798 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 856157 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 842050 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1698207 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 260013 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 263688 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 523701 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 5012 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 2736 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 856157 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 401447 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 4343 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 2270 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 842050 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 418052 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2532067 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 5012 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 2736 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 856157 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 401447 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 4343 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 2270 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 842050 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 418052 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2532067 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000599 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000365 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001151 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000441 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.000696 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.007524 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.007687 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.007609 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.410485 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.468555 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.440812 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.009507 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.011681 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.010587 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.021805 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.024308 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.023070 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000495 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000300 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.009507 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.158985 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000952 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000369 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.011681 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.188063 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.063302 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000495 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000300 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.009507 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.158985 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000952 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000369 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.011681 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.188063 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.063302 # miss rate for overall accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.404026 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.465199 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.435950 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.009476 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.011708 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.010583 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.021718 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.024453 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.023095 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000599 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000365 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.009476 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.156409 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001151 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000441 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.011708 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.187197 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.062806 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000599 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000365 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.009476 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.156409 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001151 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000441 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.011708 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.187197 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.062806 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83666.666667 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 84000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 86600 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 83500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 85150 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 241.185296 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 143.723252 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 191.224863 # average UpgradeReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 84000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 85200 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 28800 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 29227.272727 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 29023.809524 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 80500 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 77374.265428 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76851.983316 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 77084.339613 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 81067.647421 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80858.823529 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 80953.150197 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 84656.786409 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82976.064657 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 83761.977658 # average ReadSharedReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 78224.393189 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77577.858237 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 77864.357557 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 80914.026870 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80522.872502 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 80699.449143 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 84671.772623 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82627.403846 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 83581.893344 # average ReadSharedReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83666.666667 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 84000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 81067.647421 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 78020.540846 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 80914.026870 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 78804.236343 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 86600 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 80858.823529 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 77351.771988 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 78021.064239 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 84000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 80522.872502 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 77993.911166 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 78620.059108 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83666.666667 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 84000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 81067.647421 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 78020.540846 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 80914.026870 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 78804.236343 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 86600 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 80858.823529 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 77351.771988 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 78021.064239 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 84000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 80522.872502 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 77993.911166 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 78620.059108 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 82443 # number of writebacks -system.l2c.writebacks::total 82443 # number of writebacks +system.l2c.writebacks::writebacks 82718 # number of writebacks +system.l2c.writebacks::total 82718 # number of writebacks system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 3 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 5 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 10 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1333 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1402 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2735 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 10 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 11 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 21 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 2 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 58027 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 72404 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 130431 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 8123 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 9860 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 17983 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 5651 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 6434 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 12085 # number of ReadSharedReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 57143 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 71810 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 128953 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 8113 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 9859 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 17972 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 5647 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 6448 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 12095 # number of ReadSharedReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 3 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 8123 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 63678 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 8113 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 62790 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 5 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 9860 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 78838 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 160509 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 9859 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 78258 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 159030 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 3 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 8123 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 63678 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 8113 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 62790 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 5 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 9860 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 78838 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 160509 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 9859 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 78258 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 159030 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 14422 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 16716 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 14396 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 16742 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 15099 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 12490 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 15072 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 12517 # number of WriteReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 29521 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 29206 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 29468 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 29259 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 221000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 74000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 383000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 73500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 751500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25378000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 26687500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 52065500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 74000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 752000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 188000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 211500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 399500 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 141000 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 141000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3909526500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4840351000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8749877500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 577282500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 698668000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 1275950500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 421885500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 469528000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 891413500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3898546500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4852766000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8751312500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 575325500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 695285000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1270610500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 421671500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 468301500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 889973000 # number of ReadSharedReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 221000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 74000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 577282500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 4331412000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 575325500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 4320218000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 383000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 73500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 698668000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 5309879000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 10917993000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 74000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 695285000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 5321067500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 10912648000 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 221000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 74000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 577282500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 4331412000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 575325500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 4320218000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 383000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 73500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 698668000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 5309879000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 10917993000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 74000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 695285000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 5321067500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 10912648000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 574512000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2653414500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3238477000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6466403500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2648734000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3243164500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6466410500 # number of ReadReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 574512000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2653414500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3238477000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 6466403500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000495 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000300 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000952 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000369 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.000576 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.991815 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.990813 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.991301 # mshr miss rate for UpgradeReq accesses +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2648734000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3243164500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6466410500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000599 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000365 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001151 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000441 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.000696 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.007524 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.007687 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.007609 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.410485 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.468555 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.440812 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.009507 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011681 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010587 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.021805 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.024308 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023070 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000495 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000300 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009507 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.158985 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000952 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000369 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011681 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.188063 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.063302 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000495 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000300 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009507 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.158985 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000952 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000369 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011681 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.188063 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.063302 # mshr miss rate for overall accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.404026 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.465199 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.435950 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.009476 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011708 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010583 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.021718 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.024453 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023095 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000599 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000365 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009476 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.156409 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001151 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000441 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011708 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.187197 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.062806 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000599 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000365 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009476 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.156409 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001151 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000441 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011708 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.187197 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.062806 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 73666.666667 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76600 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 75150 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19038.259565 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19035.306705 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19036.745887 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 74000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 75200 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18800 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19227.272727 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19023.809524 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 70500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 67374.265428 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66851.983316 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 67084.339613 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 71067.647421 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70858.823529 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 70953.150197 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74656.786409 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72976.064657 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 73761.977658 # average ReadSharedReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68224.393189 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67577.858237 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 67864.357557 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 70914.026870 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70522.872502 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 70699.449143 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74671.772623 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72627.403846 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 73581.893344 # average ReadSharedReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 73666.666667 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71067.647421 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68020.540846 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70914.026870 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68804.236343 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76600 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70858.823529 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67351.771988 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 68021.064239 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 74000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70522.872502 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67993.911166 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 68620.059108 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73666.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71067.647421 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68020.540846 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70914.026870 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68804.236343 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76600 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70858.823529 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67351.771988 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 68021.064239 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 74000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70522.872502 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67993.911166 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 68620.059108 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63679.006872 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183983.809458 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193735.163915 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 161016.023406 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183990.969714 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193714.281448 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 161016.197709 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63679.006872 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 89882.270248 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 110883.962200 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 95446.478915 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 325065 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 134281 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 89885.095697 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 110843.313169 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 95446.582237 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 321037 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 130073 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 40160 # Transaction distribution -system.membus.trans_dist::ReadResp 70472 # Transaction distribution +system.membus.trans_dist::ReadResp 70471 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::WritebackDirty 118633 # Transaction distribution -system.membus.trans_dist::CleanEvict 6722 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4501 # Transaction distribution +system.membus.trans_dist::WritebackDirty 118908 # Transaction distribution +system.membus.trans_dist::CleanEvict 6612 # Transaction distribution +system.membus.trans_dist::UpgradeReq 128 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 128665 # Transaction distribution -system.membus.trans_dist::ReadExResp 128665 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30312 # Transaction distribution +system.membus.trans_dist::ReadExReq 128846 # Transaction distribution +system.membus.trans_dist::ReadExResp 128846 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30311 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438549 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 546141 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 434701 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 542293 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 619038 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 615190 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15474044 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15637397 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15503164 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15666517 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17954517 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17983637 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 498 # Total snoops (count) system.membus.snoopTraffic 31744 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 267453 # Request fanout histogram -system.membus.snoop_fanout::mean 0.018325 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.134123 # Request fanout histogram +system.membus.snoop_fanout::samples 263260 # Request fanout histogram +system.membus.snoop_fanout::mean 0.018617 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.135167 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 262552 98.17% 98.17% # Request fanout histogram -system.membus.snoop_fanout::1 4901 1.83% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 258359 98.14% 98.14% # Request fanout histogram +system.membus.snoop_fanout::1 4901 1.86% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 267453 # Request fanout histogram -system.membus.reqLayer0.occupancy 90447000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 263260 # Request fanout histogram +system.membus.reqLayer0.occupancy 90452000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1735500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1733000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 831225280 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 826968490 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 950869500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 951904000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1219123 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1219623 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1984,85 +1975,85 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5058632 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2540376 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 38310 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 5057608 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2539902 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 38289 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 250 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 250 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2903873346500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 74735 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2297346 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 74966 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2297117 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 766059 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1698024 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 142069 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2759 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 766133 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1697713 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 141921 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2760 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295888 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295888 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1698542 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 524071 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2762 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295798 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295798 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1698231 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 523922 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 4401 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5113128 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581868 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17962 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 33975 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7746933 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 217414776 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96411805 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24184 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 45264 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 313896029 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 111009 # Total snoops (count) -system.toL2Bus.snoopTraffic 5360756 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2716918 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021699 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.145698 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5112195 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581153 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 16978 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 32189 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7742515 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 217374968 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96383645 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20024 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 37420 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 313816057 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 114406 # Total snoops (count) +system.toL2Bus.snoopTraffic 5391284 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 2716765 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021720 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.145768 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2657964 97.83% 97.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 58954 2.17% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2657757 97.83% 97.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 59008 2.17% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2716918 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4965727500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2716765 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4964781500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 389377 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2556835000 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2556368500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1275921497 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1275563497 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11916000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11972000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 22659000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 22834000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |