diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
commit | 54227f9e57f625a66e3fd1d0d67fbd53b5408bf2 (patch) | |
tree | 77faeed4436765032a90ede56ba9d231f1c717aa /tests/quick/fs/10.linux-boot/ref/arm/linux | |
parent | 1c321b88473d65ff4bd9a7b65a91351781fd31d8 (diff) | |
download | gem5-54227f9e57f625a66e3fd1d0d67fbd53b5408bf2.tar.xz |
Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux')
-rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt | 1008 |
1 files changed, 504 insertions, 504 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 4a0324f9e..07e356a30 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,54 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.629150 # Number of seconds simulated -sim_ticks 2629149747000 # Number of ticks simulated -final_tick 2629149747000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.624688 # Number of seconds simulated +sim_ticks 2624688029000 # Number of ticks simulated +final_tick 2624688029000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 556259 # Simulator instruction rate (inst/s) -host_op_rate 707830 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24290841486 # Simulator tick rate (ticks/s) -host_mem_usage 380276 # Number of bytes of host memory used -host_seconds 108.24 # Real time elapsed on the host -sim_insts 60207390 # Number of instructions simulated -sim_ops 76612873 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 705696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9115408 # Number of bytes read from this memory -system.physmem.bytes_read::total 134077744 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 705696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705696 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3736256 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6752328 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17229 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142462 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15691729 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58379 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812397 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47261004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 97 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 268412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3467055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50996618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 268412 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 268412 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1421089 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1147166 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2568255 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1421089 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47261004 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 97 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 268412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4614222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53564873 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 388710 # Simulator instruction rate (inst/s) +host_op_rate 494628 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16947208284 # Simulator tick rate (ticks/s) +host_mem_usage 385844 # Number of bytes of host memory used +host_seconds 154.87 # Real time elapsed on the host +sim_insts 60201138 # Number of instructions simulated +sim_ops 76605123 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -61,244 +23,44 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 62933 # number of replacements -system.cpu.l2cache.tagsinuse 51862.510726 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1683379 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 128318 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 13.118806 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2576532162000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 38450.903251 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 2.914018 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000670 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 7005.048584 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6403.644203 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.586714 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000044 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.106889 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.097712 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.791359 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8836 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3549 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 844195 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 370308 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226888 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 596416 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 596416 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113846 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113846 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 8836 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3549 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 844195 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 484154 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1340734 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 8836 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3549 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 844195 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 484154 # number of overall hits -system.cpu.l2cache.overall_hits::total 1340734 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 4 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 10613 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10261 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 20880 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2845 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2845 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133824 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133824 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 4 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 10613 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 144085 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 154704 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 4 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 10613 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 144085 # number of overall misses -system.cpu.l2cache.overall_misses::total 154704 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 208000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 104000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 553137500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 534185000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1087634500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6961477000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6961477000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 208000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 104000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 553137500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7495662000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8049111500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 208000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 104000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 553137500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7495662000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8049111500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8840 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 854808 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 380569 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1247768 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 596416 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 596416 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2871 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2871 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247670 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247670 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8840 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 854808 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 628239 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1495438 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8840 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 854808 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 628239 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1495438 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000452 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000563 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012416 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026962 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016734 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990944 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990944 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540332 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.540332 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000452 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000563 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012416 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.229347 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.103451 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000452 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000563 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012416 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.229347 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.103451 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52118.863658 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52059.740766 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52089.774904 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 365.553603 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 365.553603 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52019.645206 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52019.645206 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52029.110430 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52029.110430 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 58379 # number of writebacks -system.cpu.l2cache.writebacks::total 58379 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 4 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10613 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10261 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 20880 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2845 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2845 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133824 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133824 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 4 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10613 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 144085 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 154704 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10613 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 144085 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 154704 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 160000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 80000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 425775500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 411049000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 837064500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 114083000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 114083000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5355569000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5355569000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 80000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425775500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5766618000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6192633500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 80000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425775500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5766618000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6192633500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166753837500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167018677500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31852864000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31852864000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198606701500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198871541500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026962 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016734 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990944 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990944 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540332 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540332 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.103451 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.103451 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.298313 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40059.350940 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40089.295977 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40099.472759 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40099.472759 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40019.495756 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40019.495756 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 705824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9049616 # Number of bytes read from this memory +system.physmem.bytes_read::total 134012208 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 705824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3676928 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6693000 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17231 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141434 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690705 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57452 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811470 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47341343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 73 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 268917 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3447883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51058338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 268917 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 268917 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1400901 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1149116 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2550017 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1400901 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47341343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 73 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 268917 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4596999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53608355 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -307,26 +69,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14998169 # DTB read hits -system.cpu.dtb.read_misses 7372 # DTB read misses -system.cpu.dtb.write_hits 11231565 # DTB write hits -system.cpu.dtb.write_misses 2270 # DTB write misses +system.cpu.dtb.read_hits 14996726 # DTB read hits +system.cpu.dtb.read_misses 7357 # DTB read misses +system.cpu.dtb.write_hits 11231612 # DTB write hits +system.cpu.dtb.write_misses 2211 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3524 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3491 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 231 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 186 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15005541 # DTB read accesses -system.cpu.dtb.write_accesses 11233835 # DTB write accesses +system.cpu.dtb.read_accesses 15004083 # DTB read accesses +system.cpu.dtb.write_accesses 11233823 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26229734 # DTB hits -system.cpu.dtb.misses 9642 # DTB misses -system.cpu.dtb.accesses 26239376 # DTB accesses -system.cpu.itb.inst_hits 61501359 # ITB inst hits +system.cpu.dtb.hits 26228338 # DTB hits +system.cpu.dtb.misses 9568 # DTB misses +system.cpu.dtb.accesses 26237906 # DTB accesses +system.cpu.itb.inst_hits 61495107 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -343,79 +105,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61505830 # ITB inst accesses -system.cpu.itb.hits 61501359 # DTB hits +system.cpu.itb.inst_accesses 61499578 # ITB inst accesses +system.cpu.itb.hits 61495107 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61505830 # DTB accesses -system.cpu.numCycles 5258299494 # number of cpu cycles simulated +system.cpu.itb.accesses 61499578 # DTB accesses +system.cpu.numCycles 5249376058 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60207390 # Number of instructions committed -system.cpu.committedOps 76612873 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68878830 # Number of integer alu accesses +system.cpu.committedInsts 60201138 # Number of instructions committed +system.cpu.committedOps 76605123 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68872510 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2140176 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948958 # number of instructions that are conditional controls -system.cpu.num_int_insts 68878830 # number of integer instructions +system.cpu.num_func_calls 2139913 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7948064 # number of instructions that are conditional controls +system.cpu.num_int_insts 68872510 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394820534 # number of times the integer registers were read -system.cpu.num_int_register_writes 74191435 # number of times the integer registers were written +system.cpu.num_int_register_reads 394780312 # number of times the integer registers were read +system.cpu.num_int_register_writes 74180713 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27397151 # number of memory refs -system.cpu.num_load_insts 15662227 # Number of load instructions -system.cpu.num_store_insts 11734924 # Number of store instructions -system.cpu.num_idle_cycles 4567780450.602262 # Number of idle cycles -system.cpu.num_busy_cycles 690519043.397737 # Number of busy cycles -system.cpu.not_idle_fraction 0.131320 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.868680 # Percentage of idle cycles +system.cpu.num_mem_refs 27395681 # number of memory refs +system.cpu.num_load_insts 15660705 # Number of load instructions +system.cpu.num_store_insts 11734976 # Number of store instructions +system.cpu.num_idle_cycles 4573668194.612258 # Number of idle cycles +system.cpu.num_busy_cycles 675707863.387743 # Number of busy cycles +system.cpu.not_idle_fraction 0.128722 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.871278 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83013 # number of quiesce instructions executed -system.cpu.icache.replacements 855930 # number of replacements -system.cpu.icache.tagsinuse 510.898307 # Cycle average of tags in use -system.cpu.icache.total_refs 60644917 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 856442 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.810302 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 19819985000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.898307 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997848 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997848 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60644917 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60644917 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60644917 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60644917 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60644917 # number of overall hits -system.cpu.icache.overall_hits::total 60644917 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856442 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856442 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856442 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856442 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856442 # number of overall misses -system.cpu.icache.overall_misses::total 856442 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12566277500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12566277500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12566277500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12566277500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12566277500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12566277500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61501359 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61501359 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61501359 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61501359 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61501359 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61501359 # number of overall (read+write) accesses +system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed +system.cpu.icache.replacements 855878 # number of replacements +system.cpu.icache.tagsinuse 510.920723 # Cycle average of tags in use +system.cpu.icache.total_refs 60638717 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 856390 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 70.807362 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 19300651000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.920723 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.997892 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.997892 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 60638717 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60638717 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60638717 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60638717 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60638717 # number of overall hits +system.cpu.icache.overall_hits::total 60638717 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856390 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856390 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856390 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856390 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856390 # number of overall misses +system.cpu.icache.overall_misses::total 856390 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11565472500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11565472500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11565472500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11565472500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11565472500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11565472500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61495107 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61495107 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61495107 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61495107 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61495107 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61495107 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013926 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14672.654424 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14672.654424 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14672.654424 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14672.654424 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14672.654424 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14672.654424 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.913065 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13504.913065 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.913065 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13504.913065 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.913065 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13504.913065 # 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average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22896.463737 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22896.463737 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22896.463737 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,54 +300,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 596416 # number of writebacks -system.cpu.dcache.writebacks::total 596416 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 369069 # 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number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166763732500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167028572500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31856780000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31856780000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198620512500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198885352500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025935 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016422 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991031 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991031 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537844 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537844 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227865 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.102795 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227865 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.102795 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.040509 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40042.402110 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40081.587813 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40033.762617 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40033.762617 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40065.154382 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40065.154382 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.040509 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40063.586280 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40067.344800 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.040509 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40063.586280 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40067.344800 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -607,10 +607,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1358668189629 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1358668189629 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1358668189629 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1358668189629 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1358750753218 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1358750753218 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1358750753218 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1358750753218 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |