diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
| commit | 5a15909bac241dc795c691d49c4e2c68cab745f4 (patch) | |
| tree | d0ae694e320c725ed8116943c7179516567279f3 /tests/quick/fs/10.linux-boot/ref/arm/linux | |
| parent | ac515d7a9b131ffc9e128bd209fcddb2f383808b (diff) | |
| download | gem5-5a15909bac241dc795c691d49c4e2c68cab745f4.tar.xz | |
stats: Update stats for monitor, cache and bus changes
This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux')
5 files changed, 2281 insertions, 2264 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 57671b2bd..29541c768 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -233,29 +233,29 @@ system.realview.nvmem.bw_total::total 75 # To system.membus.throughput 64986577 # Throughput (bytes/s) system.membus.data_through_bus 59274047 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.l2c.replacements 70658 # number of replacements -system.l2c.tagsinuse 51560.149653 # Cycle average of tags in use -system.l2c.total_refs 1623339 # Total number of references to valid blocks. -system.l2c.sampled_refs 135810 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.953015 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.786745 # Average percentage of cache occupancy +system.l2c.tags.replacements 70658 # number of replacements +system.l2c.tags.tagsinuse 51560.149653 # Cycle average of tags in use +system.l2c.tags.total_refs 1623339 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 135810 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.953015 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.786745 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits @@ -486,15 +486,15 @@ system.cpu0.not_idle_fraction 0.021750 # Pe system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed -system.cpu0.icache.replacements 428546 # number of replacements -system.cpu0.icache.tagsinuse 511.015216 # Cycle average of tags in use -system.cpu0.icache.total_refs 29811115 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 429058 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 69.480385 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998077 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 428546 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.015216 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 29811115 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 69.480385 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998077 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits @@ -528,15 +528,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 323609 # number of replacements -system.cpu0.dcache.tagsinuse 494.763091 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12467604 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 323981 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 38.482516 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.966334 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 323609 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.763091 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 12467604 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 323981 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 38.482516 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 6512305 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 6512305 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 5630881 # number of WriteReq hits @@ -662,15 +662,15 @@ system.cpu1.not_idle_fraction 0.022362 # Pe system.cpu1.idle_fraction 0.977638 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 40379 # number of quiesce instructions executed -system.cpu1.icache.replacements 433942 # number of replacements -system.cpu1.icache.tagsinuse 475.447912 # Cycle average of tags in use -system.cpu1.icache.total_refs 31979125 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 434454 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 73.607620 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.928609 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 433942 # number of replacements +system.cpu1.icache.tags.tagsinuse 475.447912 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 31979125 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 434454 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 73.607620 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.928609 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 31979125 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 31979125 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 31979125 # number of demand (read+write) hits @@ -704,15 +704,15 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 294289 # number of replacements -system.cpu1.dcache.tagsinuse 447.573682 # Cycle average of tags in use -system.cpu1.dcache.total_refs 11707745 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 294801 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 39.714061 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.874167 # Average percentage of cache occupancy +system.cpu1.dcache.tags.replacements 294289 # number of replacements +system.cpu1.dcache.tags.tagsinuse 447.573682 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 11707745 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 294801 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 39.714061 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.874167 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 7002209 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 7002209 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 4520313 # number of WriteReq hits @@ -772,12 +772,12 @@ system.cpu1.dcache.cache_copies 0 # nu system.cpu1.dcache.writebacks::writebacks 266849 # number of writebacks system.cpu1.dcache.writebacks::total 266849 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 979b75345..486d98045 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -284,15 +284,15 @@ system.cpu.not_idle_fraction 0.016889 # Pe system.cpu.idle_fraction 0.983111 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed -system.cpu.icache.replacements 850590 # number of replacements -system.cpu.icache.tagsinuse 511.678593 # Cycle average of tags in use -system.cpu.icache.total_refs 60583498 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 851102 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 71.182418 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 850590 # number of replacements +system.cpu.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60583498 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 60583498 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 60583498 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 60583498 # number of demand (read+write) hits @@ -326,23 +326,23 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 62243 # number of replacements -system.cpu.l2cache.tagsinuse 50007.272909 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1669922 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 127628 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 13.084292 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.763050 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 62243 # number of replacements +system.cpu.l2cache.tags.tagsinuse 50007.272909 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1669922 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 127628 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 13.084292 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.763050 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits @@ -434,15 +434,15 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks system.cpu.l2cache.writebacks::total 57863 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 623337 # number of replacements -system.cpu.dcache.tagsinuse 511.997031 # Cycle average of tags in use -system.cpu.dcache.total_refs 23628343 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 623849 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.875100 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 623337 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 23628343 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 623849 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.875100 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits @@ -501,12 +501,12 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.toL2Bus.throughput 59102649 # Throughput (bytes/s) system.cpu.toL2Bus.data_through_bus 137875266 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 7372967ce..7e08761d9 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.194897 # Number of seconds simulated -sim_ticks 1194896580500 # Number of ticks simulated -final_tick 1194896580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.194911 # Number of seconds simulated +sim_ticks 1194911360500 # Number of ticks simulated +final_tick 1194911360500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 311660 # Simulator instruction rate (inst/s) -host_op_rate 397163 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6068013925 # Simulator tick rate (ticks/s) -host_mem_usage 403588 # Number of bytes of host memory used -host_seconds 196.92 # Real time elapsed on the host -sim_insts 61371297 # Number of instructions simulated -sim_ops 78208202 # Number of ops (including micro ops) simulated +host_inst_rate 773513 # Simulator instruction rate (inst/s) +host_op_rate 985724 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15060857671 # Simulator tick rate (ticks/s) +host_mem_usage 403580 # Number of bytes of host memory used +host_seconds 79.34 # Real time elapsed on the host +sim_insts 61369589 # Number of instructions simulated +sim_ops 78206230 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 463972 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6626100 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 464036 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6626228 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 255836 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2904240 # Number of bytes read from this memory -system.physmem.bytes_read::total 62155108 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 463972 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 255836 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 719808 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4136192 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 256092 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2904304 # Number of bytes read from this memory +system.physmem.bytes_read::total 62155620 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 464036 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 256092 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 720128 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4136576 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 7163536 # Number of bytes written to this memory +system.physmem.bytes_written::total 7163920 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13468 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 103605 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13469 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 103607 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4079 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 45405 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654628 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64628 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4083 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 45406 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654636 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64634 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821464 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43438497 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821470 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43437960 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 388295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 5545333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 388343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 5545372 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 214107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2430537 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52017144 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 388295 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 214107 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 602402 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3461548 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 2533528 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 214319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2430560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52016930 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 388343 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 214319 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 602662 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3461827 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 2533497 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5995110 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3461548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43438497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 5995357 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3461827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43437960 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 388295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 8078862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 388343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 8078869 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 214107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2430570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58012254 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654628 # Total number of read requests seen -system.physmem.writeReqs 821464 # Total number of write requests seen +system.physmem.bw_total::cpu1.inst 214319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2430594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58012286 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654636 # Total number of read requests seen +system.physmem.writeReqs 821470 # Total number of write requests seen system.physmem.cpureqs 235013 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 425896192 # Total number of bytes read from memory -system.physmem.bytesWritten 52573696 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62155108 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7163536 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 139 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 10646 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 415731 # Track reads on a per bank basis +system.physmem.bytesRead 425896704 # Total number of bytes read from memory +system.physmem.bytesWritten 52574080 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62155620 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7163920 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 138 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 10632 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 415730 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 415559 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 414958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 414961 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 415336 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 422399 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 415419 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 415520 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 415298 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 415301 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 415351 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 415631 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 415270 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 414902 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 415547 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 416079 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 416081 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 415762 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 415727 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 415729 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 50036 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 49924 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51324 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51325 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 51581 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 51864 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 51435 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 51646 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51464 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51467 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 51327 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 51592 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 51318 # Track writes on a per bank basis @@ -106,41 +106,41 @@ system.physmem.perBankWrReqs::11 51082 # Tr system.physmem.perBankWrReqs::12 51567 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 51872 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 51738 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51694 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51696 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1194892168500 # Total gap between requests +system.physmem.totGap 1194906959500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6825 # Categorize read packet sizes system.physmem.readPktSize::3 6488064 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159739 # Categorize read packet sizes +system.physmem.readPktSize::6 159747 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 64628 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 581008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 419779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 439715 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1589810 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1189300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1185139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1157962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 13029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 10446 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 15424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 15138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 4570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 4445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 4046 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 75 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64634 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 581277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 421174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 435266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1590102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1186915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1183214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1164468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 13127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 10448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 15751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 21053 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 15489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 4169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 4068 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 3980 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 77 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -156,10 +156,10 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35716 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 35716 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 35716 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 35716 # What write queue length does an incoming req see @@ -175,304 +175,302 @@ system.physmem.wrQLenPdf::15 35716 # Wh system.physmem.wrQLenPdf::16 35716 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 35716 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 34609 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 13824.665723 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 735.190153 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 27804.066503 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 7914 22.87% 22.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 4043 11.68% 34.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2692 7.78% 42.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1927 5.57% 47.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1400 4.05% 51.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1123 3.24% 55.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 878 2.54% 57.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 878 2.54% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 638 1.84% 62.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 541 1.56% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 480 1.39% 65.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 476 1.38% 66.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 262 0.76% 67.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 253 0.73% 67.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 191 0.55% 68.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 292 0.84% 69.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 145 0.42% 69.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 146 0.42% 70.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 123 0.36% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 107 0.31% 70.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 79 0.23% 71.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 170 0.49% 71.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 949 2.74% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 246 0.71% 74.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 151 0.44% 75.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 129 0.37% 75.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 98 0.28% 76.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 72 0.21% 76.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 65 0.19% 76.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 51 0.15% 76.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 51 0.15% 76.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 71 0.21% 76.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 44 0.13% 77.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 29 0.08% 77.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 19 0.05% 77.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 34668 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 13801.223030 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 734.240341 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 27780.651463 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-127 7945 22.92% 22.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-191 4005 11.55% 34.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-255 2676 7.72% 42.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-319 1963 5.66% 47.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-383 1415 4.08% 51.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-447 1138 3.28% 55.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-511 895 2.58% 57.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-575 859 2.48% 60.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-639 666 1.92% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-703 565 1.63% 63.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-767 463 1.34% 65.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-831 439 1.27% 66.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-895 280 0.81% 67.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-959 254 0.73% 67.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-1023 189 0.55% 68.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1087 312 0.90% 69.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1151 134 0.39% 69.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1215 136 0.39% 70.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1279 130 0.37% 70.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1343 99 0.29% 70.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1407 89 0.26% 71.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1471 164 0.47% 71.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1535 949 2.74% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1599 269 0.78% 75.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1663 135 0.39% 75.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1727 116 0.33% 75.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1791 100 0.29% 76.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1855 85 0.25% 76.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1919 65 0.19% 76.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1983 50 0.14% 76.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2047 50 0.14% 76.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2111 59 0.17% 77.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2175 33 0.10% 77.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2239 32 0.09% 77.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2303 20 0.06% 77.24% # Bytes accessed per row activation system.physmem.bytesPerActivate::2304-2367 23 0.07% 77.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 27 0.08% 77.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 13 0.04% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 27 0.08% 77.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 12 0.03% 77.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 9 0.03% 77.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 14 0.04% 77.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 11 0.03% 77.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 12 0.03% 77.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 14 0.04% 77.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 6 0.02% 77.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 7 0.02% 77.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 15 0.04% 77.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 4 0.01% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 7 0.02% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 4 0.01% 77.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 14 0.04% 77.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 11 0.03% 77.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 7 0.02% 77.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 7 0.02% 77.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 11 0.03% 77.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2431 11 0.03% 77.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2495 23 0.07% 77.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2559 27 0.08% 77.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2623 12 0.03% 77.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2687 11 0.03% 77.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2751 15 0.04% 77.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2815 7 0.02% 77.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2879 13 0.04% 77.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2943 8 0.02% 77.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-3007 13 0.04% 77.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3071 9 0.03% 77.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3135 14 0.04% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3199 9 0.03% 77.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3263 16 0.05% 77.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3327 6 0.02% 77.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3391 9 0.03% 77.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3455 7 0.02% 77.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3519 9 0.03% 77.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3583 6 0.02% 77.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3647 6 0.02% 77.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::3648-3711 8 0.02% 78.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 5 0.01% 78.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 12 0.03% 78.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 4 0.01% 78.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 5 0.01% 78.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 8 0.02% 78.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 6 0.02% 78.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 41 0.12% 78.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 3 0.01% 78.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 4 0.01% 78.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 5 0.01% 78.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 4 0.01% 78.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 5 0.01% 78.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 4 0.01% 78.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 5 0.01% 78.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 9 0.03% 78.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 4 0.01% 78.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 2 0.01% 78.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 4 0.01% 78.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 4 0.01% 78.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4991 1 0.00% 78.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 5 0.01% 78.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5119 3 0.01% 78.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 10 0.03% 78.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5247 3 0.01% 78.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5375 2 0.01% 78.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 5 0.01% 78.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5503 2 0.01% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 5 0.01% 78.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5695 3 0.01% 78.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5759 6 0.02% 78.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5823 2 0.01% 78.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5887 3 0.01% 78.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 5 0.01% 78.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-6015 4 0.01% 78.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6079 3 0.01% 78.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6143 3 0.01% 78.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 170 0.49% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6271 3 0.01% 79.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 1 0.00% 79.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6399 4 0.01% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6463 4 0.01% 79.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 1 0.00% 79.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6655 2 0.01% 79.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 5 0.01% 79.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 3 0.01% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3775 9 0.03% 78.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3839 8 0.02% 78.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3903 6 0.02% 78.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3967 7 0.02% 78.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-4031 9 0.03% 78.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4095 6 0.02% 78.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4159 45 0.13% 78.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4223 4 0.01% 78.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4287 6 0.02% 78.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4351 9 0.03% 78.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4415 2 0.01% 78.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4479 4 0.01% 78.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4543 6 0.02% 78.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4607 8 0.02% 78.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4671 6 0.02% 78.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4735 4 0.01% 78.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4799 3 0.01% 78.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4863 3 0.01% 78.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4927 5 0.01% 78.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4991 2 0.01% 78.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5055 8 0.02% 78.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5119 2 0.01% 78.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5183 3 0.01% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5247 1 0.00% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5439 2 0.01% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5503 1 0.00% 78.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5567 1 0.00% 78.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5631 5 0.01% 78.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5695 6 0.02% 78.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5759 2 0.01% 78.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5823 1 0.00% 78.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5887 1 0.00% 78.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5951 6 0.02% 78.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6079 6 0.02% 78.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6207 180 0.52% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6271 1 0.00% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6335 4 0.01% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6399 1 0.00% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6463 5 0.01% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6527 1 0.00% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6591 1 0.00% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6655 1 0.00% 79.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6719 3 0.01% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6783 2 0.01% 79.14% # Bytes accessed per row activation system.physmem.bytesPerActivate::6784-6847 21 0.06% 79.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6911 3 0.01% 79.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6911 2 0.01% 79.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::6912-6975 1 0.00% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 1 0.00% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7167 1 0.00% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 4 0.01% 79.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7295 3 0.01% 79.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7359 2 0.01% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7423 1 0.00% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7487 3 0.01% 79.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 4 0.01% 79.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7039 1 0.00% 79.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7103 2 0.01% 79.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7167 2 0.01% 79.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7231 6 0.02% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7359 1 0.00% 79.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7423 1 0.00% 79.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7551 3 0.01% 79.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::7552-7615 3 0.01% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 3 0.01% 79.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 4 0.01% 79.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 2 0.01% 79.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 5 0.01% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 2 0.01% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 2 0.01% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 7 0.02% 79.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 4 0.01% 79.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 318 0.92% 80.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8511 1 0.00% 80.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8767 1 0.00% 80.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-9023 2 0.01% 80.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9279 4 0.01% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9471 1 0.00% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9535 2 0.01% 80.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9663 1 0.00% 80.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9791 2 0.01% 80.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10303 17 0.05% 80.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10559 2 0.01% 80.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10815 1 0.00% 80.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11071 2 0.01% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11263 1 0.00% 80.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7679 3 0.01% 79.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7743 3 0.01% 79.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7807 1 0.00% 79.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7871 3 0.01% 79.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7935 6 0.02% 79.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7999 6 0.02% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8063 3 0.01% 79.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8127 7 0.02% 79.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8191 5 0.01% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8255 319 0.92% 80.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8511 2 0.01% 80.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8767 1 0.00% 80.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-9023 1 0.00% 80.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9279 2 0.01% 80.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9471 1 0.00% 80.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9535 1 0.00% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9663 1 0.00% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-10047 2 0.01% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10303 18 0.05% 80.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10559 2 0.01% 80.38% # Bytes accessed per row activation system.physmem.bytesPerActivate::11264-11327 2 0.01% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11583 2 0.01% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11583 1 0.00% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11839 1 0.00% 80.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::12032-12095 1 0.00% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12799 1 0.00% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13375 1 0.00% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13631 2 0.01% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13887 1 0.00% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14399 1 0.00% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15423 2 0.01% 80.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15679 1 0.00% 80.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15935 1 0.00% 80.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16191 1 0.00% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16447 1 0.00% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16767 1 0.00% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17215 1 0.00% 80.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17343 1 0.00% 80.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17471 2 0.01% 80.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17791 1 0.00% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17856-17919 1 0.00% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18239 1 0.00% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18495 2 0.01% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19263 1 0.00% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20543 13 0.04% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20799 1 0.00% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-21055 1 0.00% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21567 2 0.01% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21823 1 0.00% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22591 3 0.01% 80.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22847 1 0.00% 80.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23103 2 0.01% 80.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 3 0.01% 80.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23871 1 0.00% 80.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24127 1 0.00% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24128-24191 1 0.00% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24383 1 0.00% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24639 1 0.00% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24895 2 0.01% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25216-25279 1 0.00% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25663 3 0.01% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25919 2 0.01% 80.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26687 1 0.00% 80.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26943 3 0.01% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27199 1 0.00% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27455 2 0.01% 80.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27711 1 0.00% 80.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27840-27903 1 0.00% 80.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27967 1 0.00% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27968-28031 1 0.00% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28479 1 0.00% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28735 2 0.01% 80.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28991 2 0.01% 80.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29247 1 0.00% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29567 1 0.00% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29759 4 0.01% 80.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-30015 5 0.01% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30271 1 0.00% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30527 1 0.00% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30783 1 0.00% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31040-31103 1 0.00% 80.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31423 1 0.00% 80.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31680-31743 1 0.00% 80.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31807 2 0.01% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32063 2 0.01% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32319 1 0.00% 80.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32831 6 0.02% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33343 1 0.00% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33472-33535 5 0.01% 80.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33599 49 0.14% 80.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33663 2 0.01% 80.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34879 1 0.00% 80.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35135 1 0.00% 80.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35903 1 0.00% 80.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38016-38079 1 0.00% 80.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38463 1 0.00% 80.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39487 1 0.00% 80.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-41023 1 0.00% 80.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42047 2 0.01% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42112-42175 1 0.00% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43071 1 0.00% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43327 1 0.00% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46911 1 0.00% 80.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48447 1 0.00% 80.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48576-48639 1 0.00% 80.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53311 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53504-53567 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53760-53823 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54016-54079 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54272-54335 1 0.00% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54528-54591 1 0.00% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55296-55359 1 0.00% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55744-55807 1 0.00% 80.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55808-55871 2 0.01% 80.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56383 3 0.01% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56576-56639 1 0.00% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58880-58943 1 0.00% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59520-59583 1 0.00% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60416-60479 1 0.00% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60608-60671 1 0.00% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62464-62527 1 0.00% 80.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63488-63551 1 0.00% 80.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65087 7 0.02% 80.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65152-65215 2 0.01% 81.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65216-65279 1 0.00% 81.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65344-65407 1 0.00% 81.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65535 6 0.02% 81.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 6201 17.92% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65920-65983 1 0.00% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::66304-66367 1 0.00% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74240-74303 1 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::76480-76543 1 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::76864-76927 1 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::84416-84479 1 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::86848-86911 1 0.00% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::87040-87103 1 0.00% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::87424-87487 1 0.00% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::97024-97087 1 0.00% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::97472-97535 1 0.00% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::97600-97663 1 0.00% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::99520-99583 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12607 1 0.00% 80.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12863 2 0.01% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12991 1 0.00% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13119 1 0.00% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13375 3 0.01% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13887 1 0.00% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14143 1 0.00% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14399 1 0.00% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14847 1 0.00% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15167 2 0.01% 80.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15423 3 0.01% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15679 1 0.00% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16447 1 0.00% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16703 2 0.01% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16895 1 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16959 2 0.01% 80.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17215 2 0.01% 80.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17727 1 0.00% 80.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18239 2 0.01% 80.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18495 1 0.00% 80.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18752-18815 1 0.00% 80.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19391 1 0.00% 80.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19519 4 0.01% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19775 1 0.00% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20287 1 0.00% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20543 13 0.04% 80.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20799 1 0.00% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-21055 2 0.01% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21567 2 0.01% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21823 1 0.00% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22079 2 0.01% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22335 2 0.01% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22591 1 0.00% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22847 1 0.00% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23615 4 0.01% 80.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24383 2 0.01% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24639 4 0.01% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25407 1 0.00% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25663 3 0.01% 80.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25919 1 0.00% 80.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26175 2 0.01% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26431 3 0.01% 80.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26687 2 0.01% 80.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27455 2 0.01% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27711 1 0.00% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28479 1 0.00% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28735 1 0.00% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29312-29375 1 0.00% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29567 1 0.00% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29759 3 0.01% 80.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-30015 1 0.00% 80.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30271 2 0.01% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30400-30463 1 0.00% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30527 3 0.01% 80.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30783 6 0.02% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31295 2 0.01% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31551 3 0.01% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31807 2 0.01% 80.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31935 1 0.00% 80.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32319 1 0.00% 80.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32575 1 0.00% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33087 16 0.05% 80.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33088-33151 1 0.00% 80.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33215 2 0.01% 80.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33343 36 0.10% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34367 1 0.00% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35647 1 0.00% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35903 1 0.00% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38207 1 0.00% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38463 1 0.00% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39488-39551 1 0.00% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41279 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41344-41407 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42047 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43071 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43584-43647 1 0.00% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44095 1 0.00% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44607 1 0.00% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45119 1 0.00% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45887 1 0.00% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48703 2 0.01% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49215 1 0.00% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50239 1 0.00% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50495 2 0.01% 80.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51520-51583 1 0.00% 80.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52287 4 0.01% 80.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52800-52863 1 0.00% 80.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54272-54335 2 0.01% 80.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55296-55359 1 0.00% 80.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56064-56127 1 0.00% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56320-56383 2 0.01% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61440-61503 2 0.01% 81.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61696-61759 1 0.00% 81.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62080-62143 1 0.00% 81.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62208-62271 1 0.00% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62464-62527 1 0.00% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62976-63039 1 0.00% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63488-63551 2 0.01% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64512-64575 2 0.01% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64832-64895 1 0.00% 81.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65087 6 0.02% 81.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65152-65215 2 0.01% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65216-65279 1 0.00% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65344-65407 1 0.00% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65535 6 0.02% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65599 6196 17.87% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::72768-72831 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73920-73983 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::75008-75071 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::82944-83007 1 0.00% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::84480-84543 1 0.00% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::85376-85439 1 0.00% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::85568-85631 1 0.00% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::94656-94719 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::95552-95615 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::98944-99007 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::99520-99583 1 0.00% 98.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::109120-109183 1 0.00% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::109696-109759 1 0.00% 98.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::110080-110143 1 0.00% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::111168-111231 1 0.00% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::114496-114559 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::120896-120959 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::121152-121215 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::121728-121791 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::122112-122175 1 0.00% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::117440-117503 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::117952-118015 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::120256-120319 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::120640-120703 1 0.00% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::121152-121215 1 0.00% 99.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::129856-129919 1 0.00% 99.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::130112-130175 1 0.00% 99.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::131072-131135 336 0.97% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::136576-136639 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196032-196095 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196160-196223 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::196608-196671 2 0.01% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 34609 # Bytes accessed per row activation -system.physmem.totQLat 134116991750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 175932036750 # Sum of mem lat for all requests -system.physmem.totBusLat 33272445000 # Total cycles spent in databus access -system.physmem.totBankLat 8542600000 # Total cycles spent in bank access -system.physmem.avgQLat 20154.36 # Average queueing delay per request -system.physmem.avgBankLat 1283.73 # Average bank access latency per request +system.physmem.bytesPerActivate::total 34668 # Bytes accessed per row activation +system.physmem.totQLat 132807422500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 174630638750 # Sum of mem lat for all requests +system.physmem.totBusLat 33272490000 # Total cycles spent in databus access +system.physmem.totBankLat 8550726250 # Total cycles spent in bank access +system.physmem.avgQLat 19957.54 # Average queueing delay per request +system.physmem.avgBankLat 1284.95 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26438.10 # Average memory access latency +system.physmem.avgMemAccLat 26242.50 # Average memory access latency system.physmem.avgRdBW 356.43 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 44.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 52.02 # Average consumed read bandwidth in MB/s @@ -480,12 +478,12 @@ system.physmem.avgConsumedWrBW 6.00 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.13 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 12.03 # Average write queue length over time -system.physmem.readRowHits 6636609 # Number of row buffer hits during reads -system.physmem.writeRowHits 804716 # Number of row buffer hits during writes +system.physmem.avgWrQLen 11.97 # Average write queue length over time +system.physmem.readRowHits 6636574 # Number of row buffer hits during reads +system.physmem.writeRowHits 804724 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.96 # Row buffer hit rate for writes -system.physmem.avgGap 159828.45 # Average gap between requests +system.physmem.avgGap 159830.13 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -504,298 +502,298 @@ system.realview.nvmem.bw_inst_read::total 57 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 60028731 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703147 # Transaction distribution -system.membus.trans_dist::ReadResp 7703147 # Transaction distribution +system.membus.throughput 60028739 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703151 # Transaction distribution +system.membus.trans_dist::ReadResp 7703151 # Transaction distribution system.membus.trans_dist::WriteReq 767201 # Transaction distribution system.membus.trans_dist::WriteResp 767201 # Transaction distribution -system.membus.trans_dist::Writeback 64628 # Transaction distribution -system.membus.trans_dist::UpgradeReq 27727 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 16403 # Transaction distribution -system.membus.trans_dist::UpgradeResp 10646 # Transaction distribution -system.membus.trans_dist::ReadExReq 137752 # Transaction distribution -system.membus.trans_dist::ReadExResp 137298 # Transaction distribution +system.membus.trans_dist::Writeback 64634 # Transaction distribution +system.membus.trans_dist::UpgradeReq 27614 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 16407 # Transaction distribution +system.membus.trans_dist::UpgradeResp 10632 # Transaction distribution +system.membus.trans_dist::ReadExReq 137758 # Transaction distribution +system.membus.trans_dist::ReadExResp 137302 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382564 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966658 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966559 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8856 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4359022 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4358923 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.bridge.slave 2382564 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 14942786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 14942687 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.gic.pio 8856 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17335150 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 17335051 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389882 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17414132 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17415028 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17712 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19823614 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19824510 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.bridge.slave 2389882 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 69318644 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 69319540 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.gic.pio 17712 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71728126 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71728126 # Total data (bytes) +system.membus.tot_pkt_size::total 71729022 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71729022 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1224802500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1208299500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9206920000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9149149500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.8 # Layer utilization (%) -system.membus.reqLayer3.occupancy 7965000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 7960500 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) system.membus.reqLayer6.occupancy 777000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 5076821641 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5034294617 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 14663419999 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 14663453747 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) -system.l2c.replacements 69621 # number of replacements -system.l2c.tagsinuse 53152.412760 # Cycle average of tags in use -system.l2c.total_refs 1651309 # Total number of references to valid blocks. -system.l2c.sampled_refs 134782 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.251703 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40039.064508 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 2.667880 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001518 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4643.192238 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 5788.281913 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.001659 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 1923.389950 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 755.813095 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.610948 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.070849 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.088322 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.029349 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.011533 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.811041 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4524 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1439 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 483114 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 241880 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 3782 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1868 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 372301 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 110577 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1219485 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 576235 # number of Writeback hits -system.l2c.Writeback_hits::total 576235 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1306 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 431 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1737 # number of UpgradeReq hits +system.l2c.tags.replacements 69629 # number of replacements +system.l2c.tags.tagsinuse 53155.534639 # Cycle average of tags in use +system.l2c.tags.total_refs 1651678 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 134776 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 12.254986 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 40041.185718 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667860 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001521 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4638.655043 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5789.348152 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001660 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1927.060090 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 756.614595 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.610980 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.070780 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.088338 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.029405 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011545 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.811089 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 4625 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1507 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 482925 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 242050 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 3554 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1806 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 372304 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 110721 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1219492 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 576641 # number of Writeback hits +system.l2c.Writeback_hits::total 576641 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1408 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 418 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51385.888946 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 53001.306767 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57979.667167 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51394.217678 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 53012.744542 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -977,56 +975,56 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 118409228 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2504917 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2504917 # Transaction distribution +system.toL2Bus.throughput 118431561 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2504925 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2504925 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 767201 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 767201 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 576235 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 27028 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 16759 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 576641 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 27027 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 16760 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 43787 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 262464 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 262464 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 993919 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2951089 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 5837 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 14921 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 753559 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 2879854 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 6195 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 11995 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 7617369 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 31383352 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 53719796 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 5764 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 18112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 24083148 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 27940806 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 7476 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 15128 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 137173582 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 137173582 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4313200 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4765991701 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::ReadExReq 262499 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 262499 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 993555 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2951402 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 5905 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 15026 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 753554 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 2880607 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 6133 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 11768 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 7617950 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 31371320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 53730420 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 6036 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 18516 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 24083596 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 27977862 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 7228 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 14216 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 137209194 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 137209194 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4306024 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4767819743 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2214801410 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2217282985 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2446229482 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2471819696 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 4396500 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 10393499 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 10398000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1696938433 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 1697865710 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 2203617971 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 2215426419 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 4326998 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 4326250 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 8213499 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 8214499 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45438572 # Throughput (bytes/s) +system.iobus.throughput 45438010 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7671400 # Transaction distribution system.iobus.trans_dist::ReadResp 7671400 # Transaction distribution system.iobus.trans_dist::WriteReq 7946 # Transaction distribution @@ -1184,13 +1182,13 @@ system.iobus.reqLayer25.occupancy 6488064000 # La system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374618000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 12976128000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 17765827253 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9653493 # DTB read hits -system.cpu0.dtb.read_misses 3738 # DTB read misses -system.cpu0.dtb.write_hits 7597651 # DTB write hits +system.cpu0.dtb.read_hits 9651794 # DTB read hits +system.cpu0.dtb.read_misses 3741 # DTB read misses +system.cpu0.dtb.write_hits 7596285 # DTB write hits system.cpu0.dtb.write_misses 1585 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -1198,16 +1196,16 @@ system.cpu0.dtb.flush_tlb_mva_asid 1439 # Nu system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9657231 # DTB read accesses -system.cpu0.dtb.write_accesses 7599236 # DTB write accesses +system.cpu0.dtb.read_accesses 9655535 # DTB read accesses +system.cpu0.dtb.write_accesses 7597870 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 17251144 # DTB hits -system.cpu0.dtb.misses 5323 # DTB misses -system.cpu0.dtb.accesses 17256467 # DTB accesses -system.cpu0.itb.inst_hits 43299111 # ITB inst hits +system.cpu0.dtb.hits 17248079 # DTB hits +system.cpu0.dtb.misses 5326 # DTB misses +system.cpu0.dtb.accesses 17253405 # DTB accesses +system.cpu0.itb.inst_hits 43295611 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1224,79 +1222,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 43301316 # ITB inst accesses -system.cpu0.itb.hits 43299111 # DTB hits +system.cpu0.itb.inst_accesses 43297816 # ITB inst accesses +system.cpu0.itb.hits 43295611 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 43301316 # DTB accesses -system.cpu0.numCycles 2389793161 # number of cpu cycles simulated +system.cpu0.itb.accesses 43297816 # DTB accesses +system.cpu0.numCycles 2389822721 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 42572187 # Number of instructions committed -system.cpu0.committedOps 53304847 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 48061724 # Number of integer alu accesses +system.cpu0.committedInsts 42568710 # Number of instructions committed +system.cpu0.committedOps 53298123 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 48055390 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1403541 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5582883 # number of instructions that are conditional controls -system.cpu0.num_int_insts 48061724 # number of integer instructions +system.cpu0.num_func_calls 1403445 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5582451 # number of instructions that are conditional controls +system.cpu0.num_int_insts 48055390 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 272457591 # number of times the integer registers were read -system.cpu0.num_int_register_writes 52272439 # number of times the integer registers were written +system.cpu0.num_int_register_reads 272420788 # number of times the integer registers were read +system.cpu0.num_int_register_writes 52266741 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 18020656 # number of memory refs -system.cpu0.num_load_insts 10037354 # Number of load instructions -system.cpu0.num_store_insts 7983302 # Number of store instructions -system.cpu0.num_idle_cycles 2150335736.878201 # Number of idle cycles -system.cpu0.num_busy_cycles 239457424.121800 # Number of busy cycles -system.cpu0.not_idle_fraction 0.100200 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.899800 # Percentage of idle cycles +system.cpu0.num_mem_refs 18017454 # number of memory refs +system.cpu0.num_load_insts 10035613 # Number of load instructions +system.cpu0.num_store_insts 7981841 # Number of store instructions +system.cpu0.num_idle_cycles 2150296210.870201 # Number of idle cycles +system.cpu0.num_busy_cycles 239526510.129800 # Number of busy cycles +system.cpu0.not_idle_fraction 0.100228 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.899772 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 51313 # number of quiesce instructions executed -system.cpu0.icache.replacements 490180 # number of replacements -system.cpu0.icache.tagsinuse 509.396236 # Cycle average of tags in use -system.cpu0.icache.total_refs 42808401 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 490692 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 87.240878 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 76020026000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.396236 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.994915 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.994915 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 42808401 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 42808401 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 42808401 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 42808401 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 42808401 # number of overall hits -system.cpu0.icache.overall_hits::total 42808401 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 490693 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 490693 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 490693 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 490693 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 490693 # number of overall misses -system.cpu0.icache.overall_misses::total 490693 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6812744000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6812744000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6812744000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6812744000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6812744000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6812744000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 43299094 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 43299094 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 43299094 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 43299094 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 43299094 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 43299094 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011333 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011333 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011333 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011333 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011333 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011333 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13883.923349 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13883.923349 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13883.923349 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13883.923349 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13883.923349 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13883.923349 # average overall miss latency +system.cpu0.kern.inst.quiesce 51308 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 490004 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.392438 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 42805077 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 490516 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 87.265404 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 76030513250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.392438 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994907 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994907 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 42805077 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 42805077 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 42805077 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 42805077 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 42805077 # number of overall hits +system.cpu0.icache.overall_hits::total 42805077 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 490517 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 490517 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 490517 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 490517 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 490517 # number of overall misses +system.cpu0.icache.overall_misses::total 490517 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6812396235 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6812396235 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6812396235 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6812396235 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6812396235 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6812396235 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 43295594 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 43295594 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 43295594 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 43295594 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 43295594 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 43295594 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011329 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011329 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011329 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011329 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011329 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011329 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13888.195995 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13888.195995 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13888.195995 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13888.195995 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13888.195995 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13888.195995 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1305,120 +1303,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490693 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 490693 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 490693 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 490693 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 490693 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 490693 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5831313090 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5831313090 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5831313090 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5831313090 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5831313090 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5831313090 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 430167000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 430167000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 430167000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 430167000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011333 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011333 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011333 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011333 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011333 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011333 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11883.831826 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11883.831826 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11883.831826 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11883.831826 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11883.831826 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11883.831826 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490517 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 490517 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 490517 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 490517 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 490517 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 490517 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5828002765 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5828002765 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5828002765 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5828002765 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5828002765 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5828002765 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 431776750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 431776750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 431776750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 431776750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011329 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011329 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011329 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011329 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011329 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011329 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11881.347160 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11881.347160 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11881.347160 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11881.347160 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11881.347160 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11881.347160 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # 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number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 6495058 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156529 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 156529 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 159015 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 159015 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 15632646 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 15632646 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 15632646 # number of overall hits -system.cpu0.dcache.overall_hits::total 15632646 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 263671 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 263671 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 176701 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 176701 # 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number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6671759 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166446 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 166446 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166389 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 166389 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 16073018 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 16073018 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 16073018 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 16073018 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028046 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.028046 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026485 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.026485 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059581 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059581 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044318 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044318 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027398 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.027398 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027398 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.027398 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14678.798579 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14678.798579 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42511.318555 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42511.318555 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9995.664011 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9995.664011 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5462.096555 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5462.096555 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25846.706875 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25846.706875 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25846.706875 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 25846.706875 # average overall miss latency +system.cpu0.dcache.tags.replacements 406612 # number of replacements +system.cpu0.dcache.tags.tagsinuse 470.882465 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 15965290 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 407124 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 39.214809 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 659626250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 470.882465 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.919692 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.919692 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 9135819 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 9135819 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 6493762 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 6493762 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156506 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 156506 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 158999 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 158999 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 15629581 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 15629581 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 15629581 # number of overall hits +system.cpu0.dcache.overall_hits::total 15629581 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 263761 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 263761 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 176647 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 176647 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9920 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9920 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7375 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7375 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 440408 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 440408 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 440408 # number of overall misses +system.cpu0.dcache.overall_misses::total 440408 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3882137498 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3882137498 # 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number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 9399580 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6670409 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6670409 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166426 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 166426 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166374 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 166374 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 16069989 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 16069989 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 16069989 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 16069989 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028061 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.028061 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026482 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.026482 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059606 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059606 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044328 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044328 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027406 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027406 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027406 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.027406 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14718.390884 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14718.390884 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42736.801593 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42736.801593 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9929.233871 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9929.233871 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5495.306712 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5495.306712 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25956.534143 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25956.534143 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25956.534143 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 25956.534143 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1427,66 +1425,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 376588 # number of writebacks -system.cpu0.dcache.writebacks::total 376588 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263671 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 263671 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176701 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 176701 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9917 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9917 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7370 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7370 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 440372 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 440372 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 440372 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 440372 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3343027009 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3343027009 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7158388504 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7158388504 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79292501 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79292501 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25539500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25539500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 376581 # number of writebacks +system.cpu0.dcache.writebacks::total 376581 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263761 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 263761 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176647 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 176647 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9920 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9920 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7371 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7371 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 440408 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 440408 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 440408 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 440408 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3349960502 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3349960502 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7149928209 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7149928209 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78594000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 78594000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25787113 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25787113 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10501415513 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10501415513 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10501415513 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10501415513 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13765210500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13765210500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807067504 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807067504 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39572278004 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39572278004 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028046 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028046 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026485 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026485 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059581 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059581 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044294 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044294 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027398 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027398 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12678.781546 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12678.781546 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40511.307259 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40511.307259 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7995.613694 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7995.613694 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3465.332429 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3465.332429 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10499888711 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10499888711 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10499888711 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10499888711 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13764207250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13764207250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807935730 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807935730 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39572142980 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39572142980 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028061 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028061 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026482 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026482 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059606 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059606 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044304 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044304 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027406 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027406 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027406 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027406 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12700.742346 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12700.742346 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40475.797545 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40475.797545 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7922.782258 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7922.782258 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3498.455162 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3498.455162 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23846.692144 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23846.692144 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23846.692144 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23846.692144 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23841.276069 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23841.276069 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23841.276069 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23841.276069 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1496,26 +1494,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 5706432 # DTB read hits -system.cpu1.dtb.read_misses 3576 # DTB read misses -system.cpu1.dtb.write_hits 3873109 # DTB write hits -system.cpu1.dtb.write_misses 645 # DTB write misses +system.cpu1.dtb.read_hits 5707792 # DTB read hits +system.cpu1.dtb.read_misses 3579 # DTB read misses +system.cpu1.dtb.write_hits 3874264 # DTB write hits +system.cpu1.dtb.write_misses 643 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 150 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 5710008 # DTB read accesses -system.cpu1.dtb.write_accesses 3873754 # DTB write accesses +system.cpu1.dtb.read_accesses 5711371 # DTB read accesses +system.cpu1.dtb.write_accesses 3874907 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 9579541 # DTB hits -system.cpu1.dtb.misses 4221 # DTB misses -system.cpu1.dtb.accesses 9583762 # DTB accesses -system.cpu1.itb.inst_hits 19379683 # ITB inst hits +system.cpu1.dtb.hits 9582056 # DTB hits +system.cpu1.dtb.misses 4222 # DTB misses +system.cpu1.dtb.accesses 9586278 # DTB accesses +system.cpu1.itb.inst_hits 19381456 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1532,79 +1530,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 19381854 # ITB inst accesses -system.cpu1.itb.hits 19379683 # DTB hits +system.cpu1.itb.inst_accesses 19383627 # ITB inst accesses +system.cpu1.itb.hits 19381456 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 19381854 # DTB accesses -system.cpu1.numCycles 2388360365 # number of cpu cycles simulated +system.cpu1.itb.accesses 19383627 # DTB accesses +system.cpu1.numCycles 2388389320 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 18799110 # Number of instructions committed -system.cpu1.committedOps 24903355 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22267252 # Number of integer alu accesses +system.cpu1.committedInsts 18800879 # Number of instructions committed +system.cpu1.committedOps 24908107 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22271769 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 796685 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2514656 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22267252 # number of integer instructions +system.cpu1.num_func_calls 796713 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2514831 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22271769 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 130770555 # number of times the integer registers were read -system.cpu1.num_int_register_writes 23319815 # number of times the integer registers were written +system.cpu1.num_int_register_reads 130796956 # number of times the integer registers were read +system.cpu1.num_int_register_writes 23323418 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 10014978 # number of memory refs -system.cpu1.num_load_insts 5983060 # Number of load instructions -system.cpu1.num_store_insts 4031918 # Number of store instructions -system.cpu1.num_idle_cycles 1968746844.438183 # Number of idle cycles -system.cpu1.num_busy_cycles 419613520.561817 # Number of busy cycles -system.cpu1.not_idle_fraction 0.175691 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.824309 # Percentage of idle cycles +system.cpu1.num_mem_refs 10017504 # number of memory refs +system.cpu1.num_load_insts 5984439 # Number of load instructions +system.cpu1.num_store_insts 4033065 # Number of store instructions +system.cpu1.num_idle_cycles 1968748229.220572 # Number of idle cycles +system.cpu1.num_busy_cycles 419641090.779428 # Number of busy cycles +system.cpu1.not_idle_fraction 0.175700 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.824300 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 39066 # number of quiesce instructions executed -system.cpu1.icache.replacements 376556 # number of replacements -system.cpu1.icache.tagsinuse 474.951242 # Cycle average of tags in use -system.cpu1.icache.total_refs 19002611 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 377068 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 50.395714 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 327008186500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 474.951242 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.927639 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.927639 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 19002611 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 19002611 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 19002611 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 19002611 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 19002611 # number of overall hits -system.cpu1.icache.overall_hits::total 19002611 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 377068 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 377068 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 377068 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 377068 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 377068 # number of overall misses -system.cpu1.icache.overall_misses::total 377068 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5155062500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5155062500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5155062500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5155062500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5155062500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5155062500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 19379679 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 19379679 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 19379679 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 19379679 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 19379679 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 19379679 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019457 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.019457 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019457 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.019457 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019457 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.019457 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13671.439899 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13671.439899 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13671.439899 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13671.439899 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13671.439899 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13671.439899 # average overall miss latency +system.cpu1.kern.inst.quiesce 39064 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 376544 # number of replacements +system.cpu1.icache.tags.tagsinuse 474.938465 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 19004396 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 377056 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 50.402052 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 327017678500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.938465 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927614 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.927614 # 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number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1653824236 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1653824236 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3737179210 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3737179210 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 78087000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 78087000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49049473 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 49049473 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 5391003446 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5391003446 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5391003446 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5391003446 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4524530 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4524530 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3787181 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3787181 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83209 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 83209 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83134 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 83134 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 8311711 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 8311711 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 8311711 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 8311711 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029606 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.029606 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029806 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.029806 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117115 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117115 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112974 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112974 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029697 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.029697 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029697 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.029697 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12346.486670 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12346.486670 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33107.834141 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 33107.834141 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8013.032324 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8013.032324 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5222.473701 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5222.473701 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21840.957120 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 21840.957120 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21840.957120 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21840.957120 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1735,66 +1733,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 199647 # number of writebacks -system.cpu1.dcache.writebacks::total 199647 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133853 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 133853 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112791 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 112791 # number of WriteReq MSHR misses +system.cpu1.dcache.writebacks::writebacks 200060 # number of writebacks +system.cpu1.dcache.writebacks::total 200060 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133951 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 133951 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112879 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 112879 # number of WriteReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9745 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9745 # number of LoadLockedReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9391 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 9391 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 246644 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 246644 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 246644 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 246644 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1384976517 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1384976517 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3477593010 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3477593010 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58436502 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58436502 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30157000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30157000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_misses::cpu1.data 246830 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 246830 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 246830 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 246830 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1384995764 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1384995764 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3490409790 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3490409790 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58580000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58580000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30268527 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30268527 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4862569527 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4862569527 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4862569527 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4862569527 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168387734500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168387734500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531024500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531024500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168918759000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168918759000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029593 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029593 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029791 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029791 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117122 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117122 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112973 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112973 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029683 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029683 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029683 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.029683 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10346.996459 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10346.996459 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30832.185281 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30832.185281 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 5996.562545 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 5996.562545 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3211.266106 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3211.266106 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4875405554 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4875405554 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4875405554 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4875405554 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168372273000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168372273000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531015000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531015000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168903288000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168903288000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029606 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029606 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029806 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029806 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117115 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117115 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112962 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112962 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029697 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029697 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029697 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.029697 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10339.570171 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10339.570171 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30921.693052 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30921.693052 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6011.287840 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6011.287840 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3223.142051 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3223.142051 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19714.931346 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19714.931346 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19714.931346 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19714.931346 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19752.078572 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19752.078572 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19752.078572 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19752.078572 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1802,12 +1800,12 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1816,10 +1814,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 626235127001 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 626235127001 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 626235127001 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 626235127001 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 624927975253 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 624927975253 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 624927975253 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 624927975253 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 934a4cb6c..955e513bb 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,129 +1,129 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.615622 # Number of seconds simulated -sim_ticks 2615622384000 # Number of ticks simulated -final_tick 2615622384000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.615733 # Number of seconds simulated +sim_ticks 2615733285000 # Number of ticks simulated +final_tick 2615733285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 264818 # Simulator instruction rate (inst/s) -host_op_rate 336993 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11506330329 # Simulator tick rate (ticks/s) -host_mem_usage 396436 # Number of bytes of host memory used -host_seconds 227.32 # Real time elapsed on the host -sim_insts 60198587 # Number of instructions simulated -sim_ops 76605405 # Number of ops (including micro ops) simulated +host_inst_rate 250012 # Simulator instruction rate (inst/s) +host_op_rate 318151 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10863402189 # Simulator tick rate (ticks/s) +host_mem_usage 396412 # Number of bytes of host memory used +host_seconds 240.78 # Real time elapsed on the host +sim_insts 60198861 # Number of instructions simulated +sim_ops 76605713 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093200 # Number of bytes read from this memory -system.physmem.bytes_read::total 132481840 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3709760 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 704864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093712 # Number of bytes read from this memory +system.physmem.bytes_read::total 132482416 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704864 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3710144 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6725832 # Number of bytes written to this memory +system.physmem.bytes_written::total 6726216 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142115 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494761 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57965 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17216 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142123 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494770 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57971 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811983 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46904092 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811989 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46902103 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 269458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3476496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50650216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 269458 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269458 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1418309 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1153099 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2571408 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1418309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46904092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 269471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3476544 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50648289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 269471 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269471 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1418395 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1153050 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2571446 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1418395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46902103 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 269458 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4629595 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53221624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494761 # Total number of read requests seen -system.physmem.writeReqs 811983 # Total number of write requests seen -system.physmem.cpureqs 215166 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 991664704 # Total number of bytes read from memory -system.physmem.bytesWritten 51966912 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132481840 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6725832 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 301 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4516 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 968108 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 967904 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 967765 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 967946 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 974722 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 968494 # Track reads on a per bank basis +system.physmem.bw_total::cpu.inst 269471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4629594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53219735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494770 # Total number of read requests seen +system.physmem.writeReqs 811989 # Total number of write requests seen +system.physmem.cpureqs 215180 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 991665280 # Total number of bytes read from memory +system.physmem.bytesWritten 51967296 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 132482416 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6726216 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 299 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4515 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 968107 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 967905 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 967771 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 967944 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 974725 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 968490 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 967971 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 967832 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 968523 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 968301 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 967958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 967840 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 968519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 968300 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 967957 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 967809 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 967930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 967935 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 967629 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 967885 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 967683 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49152 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 49010 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50853 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51127 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51430 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51246 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51368 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50878 # Track writes on a per bank basis +system.physmem.perBankRdReqs::14 967887 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 967682 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49150 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 49013 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50857 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50909 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51128 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51425 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51254 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51364 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50876 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 50797 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 50871 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 50874 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 50522 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50825 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 50676 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50827 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 50677 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2615618000000 # Total gap between requests +system.physmem.totGap 2615728912000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6652 # Categorize read packet sizes system.physmem.readPktSize::3 15335424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152685 # Categorize read packet sizes +system.physmem.readPktSize::6 152694 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 57965 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1126555 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 973164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1018253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3775658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2831038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2826406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2774250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 21901 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 19136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 31670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 43534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 30921 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 5697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 5598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 40 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57971 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1128832 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 975833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1007328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3775576 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2827750 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2822812 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2787859 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 21456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 32464 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 45819 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 32079 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 4562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 4458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 4308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 45 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -139,8 +139,8 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35301 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 35303 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 35304 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 35304 # What write queue length does an incoming req see @@ -153,17 +153,17 @@ system.physmem.wrQLenPdf::10 35304 # Wh system.physmem.wrQLenPdf::11 35304 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 35304 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35304 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35303 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35303 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,308 +171,327 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38567 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 27059.676926 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2495.376643 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 33105.439598 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 5489 14.23% 14.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 3331 8.64% 22.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2176 5.64% 28.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1697 4.40% 32.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1162 3.01% 35.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1046 2.71% 38.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 828 2.15% 40.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 748 1.94% 42.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 582 1.51% 44.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 509 1.32% 45.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 411 1.07% 46.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 479 1.24% 47.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 285 0.74% 48.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 248 0.64% 49.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 187 0.48% 49.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 239 0.62% 50.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 141 0.37% 50.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 137 0.36% 51.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 106 0.27% 51.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 105 0.27% 51.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 92 0.24% 51.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 151 0.39% 52.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 970 2.52% 54.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 203 0.53% 55.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 135 0.35% 55.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 110 0.29% 55.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 91 0.24% 56.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 77 0.20% 56.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 66 0.17% 56.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 47 0.12% 56.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 51 0.13% 56.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 64 0.17% 56.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 37 0.10% 57.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 25 0.06% 57.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 18 0.05% 57.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2367 25 0.06% 57.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 26 0.07% 57.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 13 0.03% 57.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 25 0.06% 57.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 11 0.03% 57.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 14 0.04% 57.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 8 0.02% 57.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 18 0.05% 57.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 9 0.02% 57.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 8 0.02% 57.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 14 0.04% 57.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 7 0.02% 57.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 17 0.04% 57.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 7 0.02% 57.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 8 0.02% 57.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 12 0.03% 57.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 12 0.03% 57.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 3 0.01% 57.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 9 0.02% 57.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 3 0.01% 57.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 6 0.02% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3711 12 0.03% 57.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 9 0.02% 57.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 7 0.02% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 9 0.02% 57.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 4 0.01% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 6 0.02% 57.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 9 0.02% 57.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 44 0.11% 58.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 3 0.01% 58.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 2 0.01% 58.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 3 0.01% 58.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 5 0.01% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 6 0.02% 58.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 2 0.01% 58.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 5 0.01% 58.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 2 0.01% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 1 0.00% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 1 0.00% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 3 0.01% 58.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 7 0.02% 58.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 6 0.02% 58.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5119 1 0.00% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 12 0.03% 58.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5247 1 0.00% 58.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5311 5 0.01% 58.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5375 3 0.01% 58.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 5 0.01% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5503 7 0.02% 58.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5567 2 0.01% 58.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 2 0.01% 58.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5695 2 0.01% 58.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5759 6 0.02% 58.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5887 3 0.01% 58.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 2 0.01% 58.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-6015 3 0.01% 58.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6079 2 0.01% 58.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6143 2 0.01% 58.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 180 0.47% 58.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6271 1 0.00% 58.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 1 0.00% 58.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6399 3 0.01% 58.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6463 5 0.01% 58.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6527 2 0.01% 58.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 3 0.01% 58.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6655 1 0.00% 58.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 2 0.01% 58.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 1 0.00% 58.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6847 15 0.04% 58.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6911 3 0.01% 58.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6975 1 0.00% 58.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7039 2 0.01% 58.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 2 0.01% 58.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7295 3 0.01% 58.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7423 1 0.00% 58.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7487 2 0.01% 58.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 3 0.01% 58.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7615 3 0.01% 58.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 3 0.01% 58.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 11 0.03% 59.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 3 0.01% 59.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7871 4 0.01% 59.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 4 0.01% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 3 0.01% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 1 0.00% 59.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 6 0.02% 59.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 4 0.01% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 327 0.85% 59.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8511 5 0.01% 59.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8895 1 0.00% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-9023 1 0.00% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9279 3 0.01% 59.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9535 2 0.01% 59.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10303 18 0.05% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10559 1 0.00% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10815 1 0.00% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11263 1 0.00% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11327 2 0.01% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11583 2 0.01% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11647 1 0.00% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11839 1 0.00% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12095 1 0.00% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12351 3 0.01% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12607 1 0.00% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13119 1 0.00% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13631 1 0.00% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14143 1 0.00% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14399 2 0.01% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14655 2 0.01% 60.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15423 3 0.01% 60.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15743 1 0.00% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15935 1 0.00% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16191 2 0.01% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16447 1 0.00% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17471 2 0.01% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17727 1 0.00% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17983 1 0.00% 60.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18239 1 0.00% 60.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18495 2 0.01% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19008-19071 1 0.00% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19263 1 0.00% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19519 3 0.01% 60.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19775 3 0.01% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-20031 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20287 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20543 2 0.01% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20799 1 0.00% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21311 1 0.00% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21567 1 0.00% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21823 2 0.01% 60.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22591 4 0.01% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22847 1 0.00% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23103 3 0.01% 60.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 5 0.01% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23871 1 0.00% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24127 2 0.01% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24639 1 0.00% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24895 1 0.00% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24960-25023 1 0.00% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25663 3 0.01% 60.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25919 2 0.01% 60.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26431 1 0.00% 60.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26687 4 0.01% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26943 1 0.00% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27199 1 0.00% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27967 1 0.00% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28096-28159 1 0.00% 60.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28735 1 0.00% 60.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28991 1 0.00% 60.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29376-29439 1 0.00% 60.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29759 6 0.02% 60.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-30015 2 0.01% 60.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30527 3 0.01% 60.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30783 3 0.01% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31168-31231 1 0.00% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31295 2 0.01% 60.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31807 5 0.01% 60.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32063 1 0.00% 60.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32831 2 0.01% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33343 4 0.01% 60.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33599 56 0.15% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33663 1 0.00% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34111 1 0.00% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34879 1 0.00% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35903 1 0.00% 60.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37439 1 0.00% 60.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38975 1 0.00% 60.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39999 2 0.01% 60.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42303 1 0.00% 60.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42559 2 0.01% 60.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43071 1 0.00% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43583 1 0.00% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45119 1 0.00% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45631 1 0.00% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46143 1 0.00% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47423 1 0.00% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48191 1 0.00% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49215 2 0.01% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49664-49727 2 0.01% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50239 1 0.00% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51263 1 0.00% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52480-52543 1 0.00% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52992-53055 1 0.00% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56383 3 0.01% 60.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57088-57151 1 0.00% 60.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59392-59455 1 0.00% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60416-60479 2 0.01% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61440-61503 1 0.00% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63488-63551 2 0.01% 60.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63808-63871 1 0.00% 60.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64512-64575 1 0.00% 60.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65087 19 0.05% 60.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65088-65151 6 0.02% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65152-65215 2 0.01% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65343 6 0.02% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65344-65407 6 0.02% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65408-65471 14 0.04% 60.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65535 6 0.02% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 14789 38.35% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::71360-71423 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73984-74047 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::83008-83071 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 38488 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 27115.229266 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2500.122459 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 33119.773163 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-127 5498 14.28% 14.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-191 3288 8.54% 22.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-255 2221 5.77% 28.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-319 1687 4.38% 32.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-383 1187 3.08% 36.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-447 1056 2.74% 38.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-511 814 2.11% 40.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-575 739 1.92% 42.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-639 550 1.43% 44.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-703 512 1.33% 45.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-767 421 1.09% 46.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-831 397 1.03% 47.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-895 314 0.82% 48.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-959 250 0.65% 49.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-1023 198 0.51% 49.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1087 236 0.61% 50.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1151 133 0.35% 50.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1215 138 0.36% 51.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1279 98 0.25% 51.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1343 109 0.28% 51.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1407 78 0.20% 51.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1471 154 0.40% 52.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1535 969 2.52% 54.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1599 195 0.51% 55.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1663 143 0.37% 55.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1727 120 0.31% 55.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1791 89 0.23% 56.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1855 73 0.19% 56.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1919 63 0.16% 56.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1983 55 0.14% 56.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2047 51 0.13% 56.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2111 51 0.13% 56.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2175 31 0.08% 56.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2239 29 0.08% 57.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2303 27 0.07% 57.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2367 16 0.04% 57.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2431 18 0.05% 57.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2495 16 0.04% 57.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2559 22 0.06% 57.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2623 11 0.03% 57.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2687 16 0.04% 57.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2751 9 0.02% 57.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2815 14 0.04% 57.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2879 16 0.04% 57.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2943 11 0.03% 57.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-3007 14 0.04% 57.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3071 8 0.02% 57.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3135 19 0.05% 57.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3199 9 0.02% 57.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3263 4 0.01% 57.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3327 13 0.03% 57.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3391 10 0.03% 57.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3455 6 0.02% 57.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3519 7 0.02% 57.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3583 3 0.01% 57.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3647 6 0.02% 57.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3711 13 0.03% 57.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3775 10 0.03% 57.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3839 5 0.01% 57.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3903 10 0.03% 57.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3967 3 0.01% 57.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-4031 7 0.02% 57.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4095 8 0.02% 57.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4159 40 0.10% 57.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4223 2 0.01% 57.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4287 4 0.01% 58.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4351 3 0.01% 58.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4415 6 0.02% 58.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4479 4 0.01% 58.04% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5247 2 0.01% 58.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5311 5 0.01% 58.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5375 4 0.01% 58.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5439 3 0.01% 58.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5503 5 0.01% 58.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5567 4 0.01% 58.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5631 4 0.01% 58.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5695 6 0.02% 58.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5759 2 0.01% 58.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5951 4 0.01% 58.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-6015 1 0.00% 58.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6079 2 0.01% 58.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6143 1 0.00% 58.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6207 184 0.48% 58.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6271 2 0.01% 58.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6335 1 0.00% 58.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6463 2 0.01% 58.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6527 3 0.01% 58.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6591 4 0.01% 58.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6655 1 0.00% 58.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6719 2 0.01% 58.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6783 1 0.00% 58.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6847 15 0.04% 58.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6911 3 0.01% 58.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6975 1 0.00% 58.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7039 2 0.01% 58.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7295 4 0.01% 58.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7359 1 0.00% 58.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7487 2 0.01% 58.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7551 3 0.01% 58.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7615 5 0.01% 58.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7679 3 0.01% 58.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7743 6 0.02% 58.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7807 4 0.01% 58.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7871 4 0.01% 58.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7935 4 0.01% 58.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7999 1 0.00% 58.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8063 1 0.00% 58.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8127 6 0.02% 58.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8191 3 0.01% 58.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8255 327 0.85% 59.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8319 1 0.00% 59.83% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15679 1 0.00% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15743 1 0.00% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16191 1 0.00% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16447 1 0.00% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17087 1 0.00% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17215 3 0.01% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17983 1 0.00% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18048-18111 1 0.00% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18239 1 0.00% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18367 1 0.00% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18495 3 0.01% 60.01% # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49215 1 0.00% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49983 1 0.00% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50239 1 0.00% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50495 1 0.00% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51263 2 0.01% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51519 1 0.00% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52736-52799 1 0.00% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54272-54335 1 0.00% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55296-55359 1 0.00% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56320-56383 2 0.01% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59392-59455 1 0.00% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62464-62527 1 0.00% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64000-64063 1 0.00% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64768-64831 1 0.00% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65087 19 0.05% 60.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65088-65151 6 0.02% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65152-65215 2 0.01% 60.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65343 6 0.02% 60.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65344-65407 6 0.02% 60.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65408-65471 14 0.04% 60.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65535 6 0.02% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65599 14794 38.44% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::71360-71423 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::76928-76991 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::81536-81599 1 0.00% 99.05% # Bytes accessed per row activation system.physmem.bytesPerActivate::85504-85567 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::93120-93183 1 0.00% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::97152-97215 1 0.00% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::97408-97471 1 0.00% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::95680-95743 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::96064-96127 1 0.00% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::98880-98943 1 0.00% 99.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::100672-100735 1 0.00% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::103680-103743 1 0.00% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::104768-104831 1 0.00% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::106432-106495 1 0.00% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::109760-109823 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::103488-103551 1 0.00% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::106240-106303 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::106624-106687 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::109440-109503 1 0.00% 99.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::110848-110911 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::110912-110975 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::114240-114303 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::115328-115391 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::116992-117055 1 0.00% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::120320-120383 1 0.00% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::111232-111295 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::114048-114111 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::117184-117247 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::118272-118335 1 0.00% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::120000-120063 1 0.00% 99.09% # Bytes accessed per row activation system.physmem.bytesPerActivate::121408-121471 1 0.00% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::121472-121535 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::124416-124479 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::127552-127615 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128640-128703 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130176-130239 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::121792-121855 1 0.00% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::124608-124671 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::125696-125759 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128832-128895 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130176-130239 1 0.00% 99.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::130368-130431 1 0.00% 99.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::130432-130495 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130496-130559 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130624-130687 1 0.00% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130560-130623 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130624-130687 1 0.00% 99.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::130688-130751 1 0.00% 99.12% # Bytes accessed per row activation system.physmem.bytesPerActivate::130880-130943 1 0.00% 99.12% # Bytes accessed per row activation system.physmem.bytesPerActivate::131072-131135 328 0.85% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::136576-136639 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::161408-161471 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::190336-190399 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196032-196095 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::156992-157055 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::193280-193343 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196096-196159 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::196608-196671 2 0.01% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38567 # Bytes accessed per row activation -system.physmem.totQLat 306544443250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 400266823250 # Sum of mem lat for all requests -system.physmem.totBusLat 77472300000 # Total cycles spent in databus access -system.physmem.totBankLat 16250080000 # Total cycles spent in bank access -system.physmem.avgQLat 19784.13 # Average queueing delay per request -system.physmem.avgBankLat 1048.77 # Average bank access latency per request +system.physmem.bytesPerActivate::total 38488 # Bytes accessed per row activation +system.physmem.totQLat 303199099750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 396944112250 # Sum of mem lat for all requests +system.physmem.totBusLat 77472355000 # Total cycles spent in databus access +system.physmem.totBankLat 16272657500 # Total cycles spent in bank access +system.physmem.avgQLat 19568.21 # Average queueing delay per request +system.physmem.avgBankLat 1050.22 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25832.90 # Average memory access latency -system.physmem.avgRdBW 379.13 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25618.44 # Average memory access latency +system.physmem.avgRdBW 379.12 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 19.87 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 50.65 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.12 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 10.80 # Average write queue length over time -system.physmem.readRowHits 15469403 # Number of row buffer hits during reads -system.physmem.writeRowHits 798459 # Number of row buffer hits during writes +system.physmem.avgWrQLen 10.84 # Average write queue length over time +system.physmem.readRowHits 15469547 # Number of row buffer hits during reads +system.physmem.writeRowHits 798405 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate 98.33 # Row buffer hit rate for writes -system.physmem.avgGap 160401.00 # Average gap between requests +system.physmem.avgGap 160407.65 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -485,59 +504,59 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54138467 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16546589 # Transaction distribution -system.membus.trans_dist::ReadResp 16546589 # Transaction distribution +system.membus.throughput 54136540 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16546595 # Transaction distribution +system.membus.trans_dist::ReadResp 16546595 # Transaction distribution system.membus.trans_dist::WriteReq 763368 # Transaction distribution system.membus.trans_dist::WriteResp 763368 # Transaction distribution -system.membus.trans_dist::Writeback 57965 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution -system.membus.trans_dist::ReadExReq 132246 # Transaction distribution -system.membus.trans_dist::ReadExResp 132246 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 57971 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution +system.membus.trans_dist::ReadExReq 132250 # Transaction distribution +system.membus.trans_dist::ReadExResp 132250 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893707 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893729 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280555 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280579 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 32564555 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 32564577 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34951403 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34951427 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16524280 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16525240 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18922393 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18923357 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 139207672 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 139208632 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141605785 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141605785 # Total data (bytes) +system.membus.tot_pkt_size::total 141606749 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141606749 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1206150500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1206151500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 17904777500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 17903854000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) system.membus.reqLayer3.occupancy 3613000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4945376509 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4944443675 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34635651750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34633310000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -545,13 +564,13 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 47817981 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16518751 # Transaction distribution -system.iobus.trans_dist::ReadResp 16518751 # Transaction distribution +system.iobus.throughput 47815955 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16518752 # Transaction distribution +system.iobus.trans_dist::ReadResp 16518752 # Transaction distribution system.iobus.trans_dist::WriteReq 8166 # Transaction distribution system.iobus.trans_dist::WriteResp 8166 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -573,11 +592,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -600,9 +619,9 @@ system.iobus.pkt_count::system.realview.aaci_fake.pio 16 system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33053834 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33053836 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -624,11 +643,11 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -651,11 +670,11 @@ system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 125073781 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 125073781 # Total data (bytes) +system.iobus.tot_pkt_size::total 125073785 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 125073785 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -701,32 +720,32 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374820000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374822000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 30670848000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) +system.iobus.respLayer1.occupancy 42022039000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14996055 # DTB read hits -system.cpu.dtb.read_misses 7342 # DTB read misses -system.cpu.dtb.write_hits 11230429 # DTB write hits -system.cpu.dtb.write_misses 2216 # DTB write misses +system.cpu.dtb.read_hits 14996132 # DTB read hits +system.cpu.dtb.read_misses 7340 # DTB read misses +system.cpu.dtb.write_hits 11230462 # DTB write hits +system.cpu.dtb.write_misses 2218 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15003397 # DTB read accesses -system.cpu.dtb.write_accesses 11232645 # DTB write accesses +system.cpu.dtb.read_accesses 15003472 # DTB read accesses +system.cpu.dtb.write_accesses 11232680 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226484 # DTB hits +system.cpu.dtb.hits 26226594 # DTB hits system.cpu.dtb.misses 9558 # DTB misses -system.cpu.dtb.accesses 26236042 # DTB accesses -system.cpu.itb.inst_hits 61492425 # ITB inst hits +system.cpu.dtb.accesses 26236152 # DTB accesses +system.cpu.itb.inst_hits 61492700 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -743,79 +762,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61496896 # ITB inst accesses -system.cpu.itb.hits 61492425 # DTB hits +system.cpu.itb.inst_accesses 61497171 # ITB inst accesses +system.cpu.itb.hits 61492700 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61496896 # DTB accesses -system.cpu.numCycles 5231244768 # number of cpu cycles simulated +system.cpu.itb.accesses 61497171 # DTB accesses +system.cpu.numCycles 5231466570 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60198587 # Number of instructions committed -system.cpu.committedOps 76605405 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68872209 # Number of integer alu accesses +system.cpu.committedInsts 60198861 # Number of instructions committed +system.cpu.committedOps 76605713 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68872503 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2140451 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948368 # number of instructions that are conditional controls -system.cpu.num_int_insts 68872209 # number of integer instructions +system.cpu.num_func_calls 2140458 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7948408 # number of instructions that are conditional controls +system.cpu.num_int_insts 68872503 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394776354 # number of times the integer registers were read -system.cpu.num_int_register_writes 74181797 # number of times the integer registers were written +system.cpu.num_int_register_reads 394778081 # number of times the integer registers were read +system.cpu.num_int_register_writes 74182147 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27393915 # number of memory refs -system.cpu.num_load_insts 15660071 # Number of load instructions -system.cpu.num_store_insts 11733844 # Number of store instructions -system.cpu.num_idle_cycles 4582065338.612248 # Number of idle cycles -system.cpu.num_busy_cycles 649179429.387752 # Number of busy cycles -system.cpu.not_idle_fraction 0.124097 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.875903 # Percentage of idle cycles +system.cpu.num_mem_refs 27394052 # number of memory refs +system.cpu.num_load_insts 15660178 # Number of load instructions +system.cpu.num_store_insts 11733874 # Number of store instructions +system.cpu.num_idle_cycles 4581968820.612248 # Number of idle cycles +system.cpu.num_busy_cycles 649497749.387752 # Number of busy cycles +system.cpu.not_idle_fraction 0.124152 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.875848 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed -system.cpu.icache.replacements 856250 # number of replacements -system.cpu.icache.tagsinuse 510.885364 # Cycle average of tags in use -system.cpu.icache.total_refs 60635663 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 856762 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.773054 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 19768699000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.885364 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997823 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997823 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60635663 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60635663 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60635663 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60635663 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60635663 # number of overall hits -system.cpu.icache.overall_hits::total 60635663 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856762 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856762 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856762 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856762 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856762 # number of overall misses -system.cpu.icache.overall_misses::total 856762 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11759087500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11759087500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11759087500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11759087500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11759087500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11759087500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61492425 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61492425 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61492425 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61492425 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61492425 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61492425 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 856294 # number of replacements +system.cpu.icache.tags.tagsinuse 510.881133 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60635894 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 856806 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.769689 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19815360250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.881133 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997815 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997815 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 60635894 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60635894 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60635894 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60635894 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60635894 # number of overall hits +system.cpu.icache.overall_hits::total 60635894 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856806 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856806 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856806 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856806 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856806 # number of overall misses +system.cpu.icache.overall_misses::total 856806 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11768628750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11768628750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11768628750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11768628750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11768628750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11768628750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61492700 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61492700 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61492700 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61492700 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61492700 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61492700 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13725.033907 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13725.033907 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13725.033907 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13725.033907 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13725.033907 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13725.033907 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.464913 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13735.464913 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.464913 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13735.464913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.464913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13735.464913 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -824,174 +843,174 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856762 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 856762 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 856762 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 856762 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 856762 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 856762 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10045563500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10045563500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10045563500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10045563500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10045563500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10045563500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 429084500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 429084500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 429084500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 429084500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856806 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 856806 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 856806 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 856806 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 856806 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 856806 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10049829250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10049829250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10049829250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10049829250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10049829250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10049829250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 430705250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 430705250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 430705250 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 430705250 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11725.033907 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11725.033907 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11725.033907 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11725.033907 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11725.033907 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11725.033907 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11729.410450 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11729.410450 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11729.410450 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11729.410450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11729.410450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11729.410450 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 62577 # number of replacements -system.cpu.l2cache.tagsinuse 50733.086800 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1684914 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 128011 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 13.162259 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2564823166000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 37695.331461 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.884612 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000689 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 6997.589035 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6036.281004 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.575185 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247798 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247797 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247797 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23787190 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23787190 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23787190 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23787190 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027156 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.027156 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024482 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024482 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046219 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046219 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026007 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026007 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026007 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026007 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14601.844185 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14601.844185 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42080.679961 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42080.679961 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13870.601589 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13870.601589 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25719.022479 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25719.022479 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25719.022479 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25719.022479 # average overall miss latency +system.cpu.dcache.tags.replacements 626803 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.877792 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 23655579 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 627315 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.709251 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 657281250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.877792 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999761 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999761 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13195771 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13195771 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9972807 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9972807 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236302 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236302 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247801 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247801 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 23168578 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23168578 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23168578 # number of overall hits +system.cpu.dcache.overall_hits::total 23168578 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368488 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368488 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250225 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250225 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11500 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11500 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 618713 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 618713 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 618713 # number of overall misses +system.cpu.dcache.overall_misses::total 618713 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5386574000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5386574000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10624198015 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10624198015 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 159892750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 159892750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16010772015 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16010772015 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16010772015 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16010772015 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13564259 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13564259 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10223032 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10223032 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247802 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247802 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247801 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247801 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 23787291 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23787291 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23787291 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23787291 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027166 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027166 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024477 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024477 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046408 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046408 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026010 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026010 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026010 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026010 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14618.044550 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14618.044550 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42458.579339 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42458.579339 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13903.717391 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13903.717391 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25877.542601 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25877.542601 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25877.542601 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25877.542601 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1176,54 +1195,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 595512 # number of writebacks -system.cpu.dcache.writebacks::total 595512 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368347 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368347 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250279 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250279 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11453 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11453 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 618626 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 618626 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 618626 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 618626 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4641851500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4641851500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10031352500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10031352500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135954000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135954000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14673204000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14673204000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14673204000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14673204000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050723500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050723500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234076500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234076500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284800000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284800000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027156 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027156 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046219 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046219 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026007 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026007 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12601.844185 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12601.844185 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40080.679961 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40080.679961 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11870.601589 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11870.601589 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23719.022479 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23719.022479 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23719.022479 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23719.022479 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 595786 # number of writebacks +system.cpu.dcache.writebacks::total 595786 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368488 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368488 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250225 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250225 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11500 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11500 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 618713 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 618713 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 618713 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 618713 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4644879500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4644879500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10059088985 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10059088985 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 136816250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 136816250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14703968485 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14703968485 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14703968485 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14703968485 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050953750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050953750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234980190 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234980190 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208285933940 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208285933940 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027166 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027166 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024477 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024477 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046408 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046408 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026010 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026010 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12605.239519 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12605.239519 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40200.175782 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40200.175782 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11897.065217 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11897.065217 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23765.410594 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23765.410594 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23765.410594 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23765.410594 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1231,44 +1250,44 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 53002965 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2454953 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2454953 # Transaction distribution +system.cpu.toL2Bus.throughput 53012095 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2455185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2455185 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 595512 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2911 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2911 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247368 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1725126 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5750616 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 12461 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 27468 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 7515671 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54754292 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 83665829 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 14140 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 34916 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 138469177 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 138469177 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 166564 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3009252000 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 595786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2898 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2898 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247327 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247327 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1725213 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5751160 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 12463 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 27463 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7516299 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54757044 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 83692777 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 14148 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 34900 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 138498869 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 138498869 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 166632 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3009752500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1291764000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1296058500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2507996500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2542947575 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 8926500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 18739000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 18739250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1277,10 +1296,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1470128900250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1470128900250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1470128900250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1470128900250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1466807214000 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1466807214000 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1466807214000 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1466807214000 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 35b3a08bb..b5f8111f8 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -223,27 +223,27 @@ system.realview.nvmem.bw_total::total 9 # To system.membus.throughput 55969561 # Throughput (bytes/s) system.membus.data_through_bus 130566366 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.l2c.replacements 62242 # number of replacements -system.l2c.tagsinuse 50006.300222 # Cycle average of tags in use -system.l2c.total_refs 1678485 # Total number of references to valid blocks. -system.l2c.sampled_refs 127627 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.151488 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36900.571453 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.993823 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4917.298419 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3152.525311 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2097.421525 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2936.495759 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563058 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.075032 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.048104 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.032004 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.044807 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.763036 # Average percentage of cache occupancy +system.l2c.tags.replacements 62242 # number of replacements +system.l2c.tags.tagsinuse 50006.300222 # Cycle average of tags in use +system.l2c.tags.total_refs 1678485 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127627 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.151488 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36900.571453 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993823 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4917.298419 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3152.525311 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2097.421525 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2936.495759 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.563058 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.075032 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.048104 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.032004 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.044807 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.763036 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.dtb.walker 9005 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3277 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 473134 # number of ReadReq hits @@ -456,17 +456,17 @@ system.cpu0.not_idle_fraction 0.959732 # Pe system.cpu0.idle_fraction 0.040268 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82795 # number of quiesce instructions executed -system.cpu0.icache.replacements 850590 # number of replacements -system.cpu0.icache.tagsinuse 511.678593 # Cycle average of tags in use -system.cpu0.icache.total_refs 60583498 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 851102 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 71.182418 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 444.510252 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 67.168341 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.868184 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.131188 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 850590 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60583498 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 444.510252 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.168341 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.868184 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131188 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 32064735 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 28518763 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 60583498 # number of ReadReq hits @@ -512,17 +512,17 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 623334 # number of replacements -system.cpu0.dcache.tagsinuse 511.997031 # Cycle average of tags in use -system.cpu0.dcache.total_refs 23628284 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 623846 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.875187 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 451.298938 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 60.698093 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.881443 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.118551 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 623334 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 23628284 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 623846 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 37.875187 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.298938 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.698093 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.881443 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.118551 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 6995590 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 6184430 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 13180020 # number of ReadReq hits @@ -666,12 +666,12 @@ system.cpu1.not_idle_fraction -0.942843 # Pe system.cpu1.idle_fraction 1.942843 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked |