diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-21 04:48:24 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-21 04:48:24 -0400 |
| commit | b006ad26d45dae3e336d7fc422adab0a330ba24a (patch) | |
| tree | 306fd2f75944fe4ad8f19f0a374d7c72ad97a5cc /tests/quick/fs/10.linux-boot/ref/arm/linux | |
| parent | 5a1dea51d2d4e2798eade7bbe3362098fc5f7f91 (diff) | |
| download | gem5-b006ad26d45dae3e336d7fc422adab0a330ba24a.tar.xz | |
stats: Update stats to reflect cache changes
Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux')
7 files changed, 193 insertions, 343 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt index f7d0d7b39..b93cd163b 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu sim_ticks 2783854535000 # Number of ticks simulated final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1852974 # Simulator instruction rate (inst/s) -host_op_rate 2255698 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36130480826 # Simulator tick rate (ticks/s) -host_mem_usage 581484 # Number of bytes of host memory used -host_seconds 77.05 # Real time elapsed on the host +host_inst_rate 1211130 # Simulator instruction rate (inst/s) +host_op_rate 1474356 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23615387886 # Simulator tick rate (ticks/s) +host_mem_usage 581436 # Number of bytes of host memory used +host_seconds 117.88 # Real time elapsed on the host sim_insts 142771651 # Number of instructions simulated sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -346,11 +346,8 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks system.cpu.dcache.writebacks::total 682017 # number of writebacks -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1698998 # number of replacements system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use system.cpu.icache.tags.total_refs 145341757 # Total number of references to valid blocks. @@ -398,11 +395,8 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 1698998 # number of writebacks system.cpu.icache.writebacks::total 1698998 # number of writebacks -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109913 # number of replacements system.cpu.l2cache.tags.tagsinuse 65155.314985 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4524855 # Total number of references to valid blocks. @@ -536,11 +530,8 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks system.cpu.l2cache.writebacks::total 101950 # number of writebacks -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 5059903 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540486 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -651,18 +642,18 @@ system.iocache.ReadReq_misses::realview.ide 240 # system.iocache.ReadReq_misses::total 240 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses -system.iocache.demand_misses::total 240 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 240 # number of overall misses -system.iocache.overall_misses::total 240 # number of overall misses +system.iocache.demand_misses::realview.ide 36464 # number of demand (read+write) misses +system.iocache.demand_misses::total 36464 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36464 # number of overall misses +system.iocache.overall_misses::total 36464 # number of overall misses system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 240 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36464 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36464 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36464 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36464 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -677,11 +668,8 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40087 # Transaction distribution system.membus.trans_dist::ReadResp 74202 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index df10533fc..4464ff885 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.802883 # Nu sim_ticks 2802882879000 # Number of ticks simulated final_tick 2802882879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1272297 # Simulator instruction rate (inst/s) -host_op_rate 1550275 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24287502010 # Simulator tick rate (ticks/s) -host_mem_usage 596572 # Number of bytes of host memory used -host_seconds 115.40 # Real time elapsed on the host +host_inst_rate 1338296 # Simulator instruction rate (inst/s) +host_op_rate 1630694 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25547394462 # Simulator tick rate (ticks/s) +host_mem_usage 592020 # Number of bytes of host memory used +host_seconds 109.71 # Real time elapsed on the host sim_insts 146828562 # Number of instructions simulated sim_ops 178908371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -365,11 +365,8 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 693475 # number of writebacks system.cpu0.dcache.writebacks::total 693475 # number of writebacks -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 1109624 # number of replacements system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 96331795 # Total number of references to valid blocks. @@ -416,11 +413,8 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 1109624 # number of writebacks system.cpu0.icache.writebacks::total 1109624 # number of writebacks -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue @@ -555,11 +549,8 @@ system.cpu0.l2cache.blocked::no_mshrs 0 # nu system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.fast_writes 0 # number of fast writes performed -system.cpu0.l2cache.cache_copies 0 # number of cache copies performed system.cpu0.l2cache.writebacks::writebacks 193020 # number of writebacks system.cpu0.l2cache.writebacks::total 193020 # number of writebacks -system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.toL2Bus.snoop_filter.tot_requests 3720001 # Total number of requests made to the snoop filter. system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860202 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -876,11 +867,8 @@ system.cpu1.dcache.blocked::no_mshrs 0 # nu system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 191946 # number of writebacks system.cpu1.dcache.writebacks::total 191946 # number of writebacks -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 523401 # number of replacements system.cpu1.icache.tags.tagsinuse 499.711077 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 53148863 # Total number of references to valid blocks. @@ -926,11 +914,8 @@ system.cpu1.icache.blocked::no_mshrs 0 # nu system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks::writebacks 523401 # number of writebacks system.cpu1.icache.writebacks::total 523401 # number of writebacks -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue @@ -1064,11 +1049,8 @@ system.cpu1.l2cache.blocked::no_mshrs 0 # nu system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.fast_writes 0 # number of fast writes performed -system.cpu1.l2cache.cache_copies 0 # number of cache copies performed system.cpu1.l2cache.writebacks::writebacks 32706 # number of writebacks system.cpu1.l2cache.writebacks::total 32706 # number of writebacks -system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.toL2Bus.snoop_filter.tot_requests 1533509 # Total number of requests made to the snoop filter. system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773310 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -1178,18 +1160,18 @@ system.iocache.ReadReq_misses::realview.ide 252 # system.iocache.ReadReq_misses::total 252 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses -system.iocache.demand_misses::total 252 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 252 # number of overall misses -system.iocache.overall_misses::total 252 # number of overall misses +system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses +system.iocache.demand_misses::total 36476 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36476 # number of overall misses +system.iocache.overall_misses::total 36476 # number of overall misses system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1204,11 +1186,8 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 107729 # number of replacements system.l2c.tags.tagsinuse 62410.633039 # Cycle average of tags in use system.l2c.tags.total_refs 243914 # Total number of references to valid blocks. @@ -1384,11 +1363,8 @@ system.l2c.blocked::no_mshrs 0 # nu system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 96268 # number of writebacks system.l2c.writebacks::total 96268 # number of writebacks -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 43996 # Transaction distribution system.membus.trans_dist::ReadResp 75724 # Transaction distribution system.membus.trans_dist::WriteReq 30846 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index ef75cc834..d5c7e4211 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu sim_ticks 2783854535000 # Number of ticks simulated final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1173204 # Simulator instruction rate (inst/s) -host_op_rate 1428188 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22875895912 # Simulator tick rate (ticks/s) -host_mem_usage 581200 # Number of bytes of host memory used -host_seconds 121.69 # Real time elapsed on the host +host_inst_rate 1225194 # Simulator instruction rate (inst/s) +host_op_rate 1491477 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23889629831 # Simulator tick rate (ticks/s) +host_mem_usage 578692 # Number of bytes of host memory used +host_seconds 116.53 # Real time elapsed on the host sim_insts 142771651 # Number of instructions simulated sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -346,11 +346,8 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks system.cpu.dcache.writebacks::total 682017 # number of writebacks -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1698998 # number of replacements system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use system.cpu.icache.tags.total_refs 145341757 # Total number of references to valid blocks. @@ -398,11 +395,8 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 1698998 # number of writebacks system.cpu.icache.writebacks::total 1698998 # number of writebacks -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109913 # number of replacements system.cpu.l2cache.tags.tagsinuse 65155.314985 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4524855 # Total number of references to valid blocks. @@ -536,11 +530,8 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks system.cpu.l2cache.writebacks::total 101950 # number of writebacks -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 5059903 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540486 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -651,18 +642,18 @@ system.iocache.ReadReq_misses::realview.ide 240 # system.iocache.ReadReq_misses::total 240 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses -system.iocache.demand_misses::total 240 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 240 # number of overall misses -system.iocache.overall_misses::total 240 # number of overall misses +system.iocache.demand_misses::realview.ide 36464 # number of demand (read+write) misses +system.iocache.demand_misses::total 36464 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36464 # number of overall misses +system.iocache.overall_misses::total 36464 # number of overall misses system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 240 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36464 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36464 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36464 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36464 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -677,11 +668,8 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40087 # Transaction distribution system.membus.trans_dist::ReadResp 74202 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index abcd4eac1..28d366488 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.871806 # Nu sim_ticks 2871806231000 # Number of ticks simulated final_tick 2871806231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 937604 # Simulator instruction rate (inst/s) -host_op_rate 1134083 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20478123685 # Simulator tick rate (ticks/s) -host_mem_usage 614632 # Number of bytes of host memory used -host_seconds 140.24 # Real time elapsed on the host +host_inst_rate 717242 # Simulator instruction rate (inst/s) +host_op_rate 867543 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15665668571 # Simulator tick rate (ticks/s) +host_mem_usage 616200 # Number of bytes of host memory used +host_seconds 183.32 # Real time elapsed on the host sim_insts 131483712 # Number of instructions simulated sim_ops 159036662 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -687,8 +687,6 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 733230 # number of writebacks system.cpu0.dcache.writebacks::total 733230 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25285 # number of ReadReq MSHR hits @@ -739,10 +737,8 @@ system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13170657000 system.cpu0.dcache.overall_mshr_miss_latency::total 13170657000 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628843000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628843000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5400920500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5400920500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12029763500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12029763500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628843000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628843000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015824 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015824 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017926 # mshr miss rate for WriteReq accesses @@ -775,11 +771,8 @@ system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15730.421260 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15730.421260 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208342.804161 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208342.804161 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189512.632022 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189512.632022 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199445.644605 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199445.644605 # average overall mshr uncacheable latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109901.899993 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109901.899993 # average overall mshr uncacheable latency system.cpu0.icache.tags.replacements 1147026 # number of replacements system.cpu0.icache.tags.tagsinuse 511.321434 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 120430031 # Total number of references to valid blocks. @@ -838,8 +831,6 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 1147026 # number of writebacks system.cpu0.icache.writebacks::total 1147026 # number of writebacks system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1147547 # number of ReadReq MSHR misses @@ -878,7 +869,6 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.l2cache.prefetcher.num_hwpf_issued 1935584 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 1935659 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 66 # number of redundant prefetches already in prefetch queue @@ -1080,8 +1070,6 @@ system.cpu0.l2cache.blocked::no_mshrs 0 # nu system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.fast_writes 0 # number of fast writes performed -system.cpu0.l2cache.cache_copies 0 # number of cache copies performed system.cpu0.l2cache.unused_prefetches 10692 # number of HardPF blocks evicted w/o reference system.cpu0.l2cache.writebacks::writebacks 231848 # number of writebacks system.cpu0.l2cache.writebacks::total 231848 # number of writebacks @@ -1160,11 +1148,9 @@ system.cpu0.l2cache.overall_mshr_miss_latency::total 28461338140 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6373893500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7560105000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5187056500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5187056500 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11560950000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12747161500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6373893500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7560105000 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013766 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.014908 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.014117 # mshr miss rate for ReadReq accesses @@ -1224,12 +1210,9 @@ system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63704.390920 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200329.807964 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185119.738485 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182008.368715 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182008.368715 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191673.022084 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183840.916958 # average overall mshr uncacheable latency -system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105675.003316 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109032.637226 # average overall mshr uncacheable latency system.cpu0.toL2Bus.snoop_filter.tot_requests 3905427 # Total number of requests made to the snoop filter. system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1969134 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 28903 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -1629,8 +1612,6 @@ system.cpu1.dcache.blocked::no_mshrs 0 # nu system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 148452 # number of writebacks system.cpu1.dcache.writebacks::total 148452 # number of writebacks system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 223 # number of ReadReq MSHR hits @@ -1679,10 +1660,8 @@ system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4699929000 system.cpu1.dcache.overall_mshr_miss_latency::total 4699929000 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 439527500 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 439527500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 303136500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 303136500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742664000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742664000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 439527500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 439527500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035447 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035447 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028102 # mshr miss rate for WriteReq accesses @@ -1715,11 +1694,8 @@ system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21750.673355 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21750.673355 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142611.129137 # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142611.129137 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125107.924061 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125107.924061 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134907.175295 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134907.175295 # average overall mshr uncacheable latency -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79841.507720 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79841.507720 # average overall mshr uncacheable latency system.cpu1.icache.tags.replacements 463484 # number of replacements system.cpu1.icache.tags.tagsinuse 498.310914 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 13457758 # Total number of references to valid blocks. @@ -1778,8 +1754,6 @@ system.cpu1.icache.blocked::no_mshrs 0 # nu system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks::writebacks 463484 # number of writebacks system.cpu1.icache.writebacks::total 463484 # number of writebacks system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463996 # number of ReadReq MSHR misses @@ -1818,7 +1792,6 @@ system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446 # average overall mshr uncacheable latency -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.l2cache.prefetcher.num_hwpf_issued 117918 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 117936 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 16 # number of redundant prefetches already in prefetch queue @@ -2015,8 +1988,6 @@ system.cpu1.l2cache.blocked::no_mshrs 0 # nu system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.fast_writes 0 # number of fast writes performed -system.cpu1.l2cache.cache_copies 0 # number of cache copies performed system.cpu1.l2cache.unused_prefetches 502 # number of HardPF blocks evicted w/o reference system.cpu1.l2cache.writebacks::writebacks 26072 # number of writebacks system.cpu1.l2cache.writebacks::total 26072 # number of writebacks @@ -2093,11 +2064,9 @@ system.cpu1.l2cache.overall_mshr_miss_latency::total 3906024043 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 22219000 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 414523000 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 436742000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 284955500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 284955500 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 22219000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 699478500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 721697500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 414523000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 436742000 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.124642 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.166480 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.140986 # mshr miss rate for ReadReq accesses @@ -2157,12 +2126,9 @@ system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30921.170050 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134498.053212 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134011.046333 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117604.416013 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117604.416013 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127062.397820 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127014.695530 # average overall mshr uncacheable latency -system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75299.364214 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76864.132348 # average overall mshr uncacheable latency system.cpu1.toL2Bus.snoop_filter.tot_requests 1324952 # Total number of requests made to the snoop filter. system.cpu1.toL2Bus.snoop_filter.hit_single_requests 669028 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10089 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -2333,26 +2299,26 @@ system.iocache.ReadReq_misses::realview.ide 255 # system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses -system.iocache.demand_misses::total 255 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 255 # number of overall misses -system.iocache.overall_misses::total 255 # number of overall misses +system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses +system.iocache.demand_misses::total 36479 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36479 # number of overall misses +system.iocache.overall_misses::total 36479 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 32883377 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 32883377 # number of ReadReq miss cycles system.iocache.WriteLineReq_miss_latency::realview.ide 4577110345 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 4577110345 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32883377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32883377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32883377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32883377 # number of overall miss cycles +system.iocache.demand_miss_latency::realview.ide 4609993722 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4609993722 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4609993722 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4609993722 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2365,36 +2331,34 @@ system.iocache.ReadReq_avg_miss_latency::realview.ide 128954.419608 system.iocache.ReadReq_avg_miss_latency::total 128954.419608 # average ReadReq miss latency system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126355.740531 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 126355.740531 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 128954.419608 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 128954.419608 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 128954.419608 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 128954.419608 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 126373.906138 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126373.906138 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 126373.906138 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126373.906138 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 24 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses +system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 20133377 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 20133377 # number of ReadReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2764215832 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 2764215832 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 20133377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 20133377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 20133377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 20133377 # number of overall MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2784349209 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2784349209 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2784349209 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2784349209 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2407,11 +2371,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78954.419608 system.iocache.ReadReq_avg_mshr_miss_latency::total 78954.419608 # average ReadReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76308.961793 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76308.961793 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 78954.419608 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 78954.419608 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 78954.419608 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 78954.419608 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76327.454398 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76327.454398 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76327.454398 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76327.454398 # average overall mshr miss latency system.l2c.tags.replacements 124374 # number of replacements system.l2c.tags.tagsinuse 62971.222447 # Cycle average of tags in use system.l2c.tags.total_refs 421293 # Total number of references to valid blocks. @@ -2693,8 +2656,6 @@ system.l2c.blocked::no_mshrs 0 # nu system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 97172 # number of writebacks system.l2c.writebacks::total 97172 # number of writebacks system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 4 # number of ReadSharedReq MSHR hits @@ -2798,14 +2759,11 @@ system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801182501 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 19032500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 359054501 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 7203084502 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4702546001 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 243701000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4946247001 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10503728502 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5801182501 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 19032500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 602755501 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 12149331503 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 359054501 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 7203084502 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.224375 # mshr miss rate for UpgradeReq accesses @@ -2885,15 +2843,11 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182329.650847 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116613.998376 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163353.770314 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165007.403804 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100578.208832 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159958.831932 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174144.978148 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96179.827923 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109552.072156 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 161954.377048 # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65258.906034 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 96019.362305 # average overall mshr uncacheable latency system.membus.trans_dist::ReadReq 44095 # Transaction distribution system.membus.trans_dist::ReadResp 214453 # Transaction distribution system.membus.trans_dist::WriteReq 30922 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 913ae877a..da0ada0fc 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.909587 # Nu sim_ticks 2909586837500 # Number of ticks simulated final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 929184 # Simulator instruction rate (inst/s) -host_op_rate 1120306 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24040663881 # Simulator tick rate (ticks/s) -host_mem_usage 581600 # Number of bytes of host memory used -host_seconds 121.03 # Real time elapsed on the host +host_inst_rate 812558 # Simulator instruction rate (inst/s) +host_op_rate 979692 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21023218607 # Simulator tick rate (ticks/s) +host_mem_usage 578440 # Number of bytes of host memory used +host_seconds 138.40 # Real time elapsed on the host sim_insts 112457033 # Number of instructions simulated sim_ops 135588117 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -651,8 +651,6 @@ system.cpu.dcache.blocked::no_mshrs 20 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 683846 # number of writebacks system.cpu.dcache.writebacks::total 683846 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 929 # number of ReadReq MSHR hits @@ -699,10 +697,8 @@ system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26477503500 system.cpu.dcache.overall_mshr_miss_latency::total 26477503500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6278149500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6278149500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5089976500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5089976500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11368126000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11368126000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6278149500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6278149500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016969 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016969 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses @@ -733,11 +729,8 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32527.086143 system.cpu.dcache.overall_avg_mshr_miss_latency::total 32527.086143 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.402274 # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.402274 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184492.968212 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184492.968212 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193575.799888 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193575.799888 # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106903.970916 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106903.970916 # average overall mshr uncacheable latency system.cpu.icache.tags.replacements 1695721 # number of replacements system.cpu.icache.tags.tagsinuse 510.436852 # Cycle average of tags in use system.cpu.icache.tags.total_refs 113858019 # Total number of references to valid blocks. @@ -797,8 +790,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 1695721 # number of writebacks system.cpu.icache.writebacks::total 1695721 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696239 # number of ReadReq MSHR misses @@ -837,7 +828,6 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 87565 # number of replacements system.cpu.l2cache.tags.tagsinuse 64865.223598 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4544536 # Total number of references to valid blocks. @@ -1017,8 +1007,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 81185 # number of writebacks system.cpu.l2cache.writebacks::total 81185 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses @@ -1078,11 +1066,9 @@ system.cpu.l2cache.overall_mshr_miss_latency::total 18759768500 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888804000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6918570000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4772572500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4772572500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1029766000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10661376500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11691142500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5888804000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6918570000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000759 # mshr miss rate for ReadReq accesses @@ -1132,12 +1118,9 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.820611 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.532404 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.149402 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.238066 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.238066 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181541.309789 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172565.536023 # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100274.217992 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 102120.621707 # average overall mshr uncacheable latency system.cpu.toL2Bus.snoop_filter.tot_requests 5052863 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536887 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38132 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -1305,26 +1288,26 @@ system.iocache.ReadReq_misses::realview.ide 228 # system.iocache.ReadReq_misses::total 228 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses -system.iocache.demand_misses::total 228 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 228 # number of overall misses -system.iocache.overall_misses::total 228 # number of overall misses +system.iocache.demand_misses::realview.ide 36452 # number of demand (read+write) misses +system.iocache.demand_misses::total 36452 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36452 # number of overall misses +system.iocache.overall_misses::total 36452 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 28180377 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 28180377 # number of ReadReq miss cycles system.iocache.WriteLineReq_miss_latency::realview.ide 4549133150 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 4549133150 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28180377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28180377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28180377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28180377 # number of overall miss cycles +system.iocache.demand_miss_latency::realview.ide 4577313527 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4577313527 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4577313527 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4577313527 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36452 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36452 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36452 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36452 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1337,36 +1320,34 @@ system.iocache.ReadReq_avg_miss_latency::realview.ide 123598.144737 system.iocache.ReadReq_avg_miss_latency::total 123598.144737 # average ReadReq miss latency system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125583.401888 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 125583.401888 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 123598.144737 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 123598.144737 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125570.984500 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125570.984500 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125570.984500 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125570.984500 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses +system.iocache.demand_mshr_misses::realview.ide 36452 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36452 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36452 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36452 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 16780377 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 16780377 # number of ReadReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736521626 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 2736521626 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16780377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16780377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16780377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16780377 # number of overall MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2753302003 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2753302003 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2753302003 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2753302003 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1379,11 +1360,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73598.144737 system.iocache.ReadReq_avg_mshr_miss_latency::total 73598.144737 # average ReadReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75544.435347 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75544.435347 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75532.261687 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75532.261687 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 75532.261687 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75532.261687 # average overall mshr miss latency system.membus.trans_dist::ReadReq 40160 # Transaction distribution system.membus.trans_dist::ReadResp 70548 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index e0084d588..254a8cf36 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu sim_ticks 2783854535000 # Number of ticks simulated final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1278958 # Simulator instruction rate (inst/s) -host_op_rate 1556926 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24937950041 # Simulator tick rate (ticks/s) -host_mem_usage 579412 # Number of bytes of host memory used -host_seconds 111.63 # Real time elapsed on the host +host_inst_rate 1181524 # Simulator instruction rate (inst/s) +host_op_rate 1438316 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23038118447 # Simulator tick rate (ticks/s) +host_mem_usage 579724 # Number of bytes of host memory used +host_seconds 120.84 # Real time elapsed on the host sim_insts 142771651 # Number of instructions simulated sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -391,11 +391,8 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 682241 # number of writebacks system.cpu0.dcache.writebacks::total 682241 # number of writebacks -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 1698998 # number of replacements system.cpu0.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 145341757 # Total number of references to valid blocks. @@ -457,11 +454,8 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 1698998 # number of writebacks system.cpu0.icache.writebacks::total 1698998 # number of writebacks -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -728,18 +722,18 @@ system.iocache.ReadReq_misses::realview.ide 240 # system.iocache.ReadReq_misses::total 240 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses -system.iocache.demand_misses::total 240 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 240 # number of overall misses -system.iocache.overall_misses::total 240 # number of overall misses +system.iocache.demand_misses::realview.ide 36464 # number of demand (read+write) misses +system.iocache.demand_misses::total 36464 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36464 # number of overall misses +system.iocache.overall_misses::total 36464 # number of overall misses system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 240 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36464 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36464 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36464 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36464 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -754,11 +748,8 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 109907 # number of replacements system.l2c.tags.tagsinuse 65155.314985 # Cycle average of tags in use system.l2c.tags.total_refs 4528037 # Total number of references to valid blocks. @@ -948,11 +939,8 @@ system.l2c.blocked::no_mshrs 0 # nu system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 101944 # number of writebacks system.l2c.writebacks::total 101944 # number of writebacks -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40087 # Transaction distribution system.membus.trans_dist::ReadResp 74196 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index cd3a72dfc..e91a37dbe 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.909645 # Nu sim_ticks 2909644861500 # Number of ticks simulated final_tick 2909644861500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 955579 # Simulator instruction rate (inst/s) -host_op_rate 1152126 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24724694945 # Simulator tick rate (ticks/s) -host_mem_usage 580436 # Number of bytes of host memory used -host_seconds 117.68 # Real time elapsed on the host +host_inst_rate 753896 # Simulator instruction rate (inst/s) +host_op_rate 908960 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19506336140 # Simulator tick rate (ticks/s) +host_mem_usage 580236 # Number of bytes of host memory used +host_seconds 149.16 # Real time elapsed on the host sim_insts 112454211 # Number of instructions simulated sim_ops 135584166 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -721,8 +721,6 @@ system.cpu0.dcache.blocked::no_mshrs 22 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6.727273 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 683901 # number of writebacks system.cpu0.dcache.writebacks::total 683901 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 477 # number of ReadReq MSHR hits @@ -789,12 +787,9 @@ system.cpu0.dcache.overall_mshr_miss_latency::total 26462029000 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3048418500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3229696000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6278114500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2495078000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2594854500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5089932500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5543496500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5824550500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11368047000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3048418500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3229696000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6278114500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017211 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016733 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016968 # mshr miss rate for ReadReq accesses @@ -838,13 +833,9 @@ system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32513.588065 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203227.900000 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200129.879787 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201622.278245 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 186338.909634 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182749.102049 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184491.373373 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 195262.293061 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 191994.940172 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193574.454680 # average overall mshr uncacheable latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 107376.488200 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 106460.625639 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 106903.374938 # average overall mshr uncacheable latency system.cpu0.icache.tags.replacements 1695677 # number of replacements system.cpu0.icache.tags.tagsinuse 510.436645 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 113855199 # Total number of references to valid blocks. @@ -924,8 +915,6 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 1695677 # number of writebacks system.cpu0.icache.writebacks::total 1695677 # number of writebacks system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 840174 # number of ReadReq MSHR misses @@ -982,7 +971,6 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126678.452671 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126678.452671 # average overall mshr uncacheable latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1315,26 +1303,26 @@ system.iocache.ReadReq_misses::realview.ide 228 # system.iocache.ReadReq_misses::total 228 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses -system.iocache.demand_misses::total 228 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 228 # number of overall misses -system.iocache.overall_misses::total 228 # number of overall misses +system.iocache.demand_misses::realview.ide 36452 # number of demand (read+write) misses +system.iocache.demand_misses::total 36452 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36452 # number of overall misses +system.iocache.overall_misses::total 36452 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 28181877 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 28181877 # number of ReadReq miss cycles system.iocache.WriteLineReq_miss_latency::realview.ide 4548907143 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 4548907143 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28181877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28181877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28181877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28181877 # number of overall miss cycles +system.iocache.demand_miss_latency::realview.ide 4577089020 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4577089020 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4577089020 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4577089020 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36452 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36452 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36452 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36452 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1347,36 +1335,34 @@ system.iocache.ReadReq_avg_miss_latency::realview.ide 123604.723684 system.iocache.ReadReq_avg_miss_latency::total 123604.723684 # average ReadReq miss latency system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125577.162737 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 125577.162737 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 123604.723684 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 123604.723684 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 123604.723684 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 123604.723684 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125564.825524 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125564.825524 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125564.825524 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125564.825524 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses +system.iocache.demand_mshr_misses::realview.ide 36452 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36452 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36452 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36452 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 16781877 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 16781877 # number of ReadReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736290629 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 2736290629 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16781877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16781877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16781877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16781877 # number of overall MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2753072506 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2753072506 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2753072506 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2753072506 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1389,11 +1375,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73604.723684 system.iocache.ReadReq_avg_mshr_miss_latency::total 73604.723684 # average ReadReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75538.058442 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75538.058442 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 73604.723684 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 73604.723684 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 73604.723684 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 73604.723684 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75525.965818 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75525.965818 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 75525.965818 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75525.965818 # average overall mshr miss latency system.l2c.tags.replacements 87562 # number of replacements system.l2c.tags.tagsinuse 64865.213908 # Cycle average of tags in use system.l2c.tags.total_refs 4551019 # Total number of references to valid blocks. @@ -1651,8 +1636,6 @@ system.l2c.blocked::no_mshrs 0 # nu system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 81183 # number of writebacks system.l2c.writebacks::total 81183 # number of writebacks system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 # number of ReadReq MSHR misses @@ -1741,14 +1724,11 @@ system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2860870000 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 386777500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3027916000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 6918904000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2341022000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2431506500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4772528500 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 643340500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5201892000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2860870000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 386777500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5459422500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 11691432500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3027916000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6918904000 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000687 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000287 # mshr miss rate for ReadReq accesses @@ -1822,15 +1802,11 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190724.666667 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187626.471682 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172283.466135 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 174833.607170 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171244.911613 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172986.643227 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 183229.728778 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 100770.341670 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179959.208228 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 172569.816529 # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 99809.341728 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 102125.551669 # average overall mshr uncacheable latency system.membus.trans_dist::ReadReq 40160 # Transaction distribution system.membus.trans_dist::ReadResp 70546 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution |