diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 16:55:47 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 16:55:47 +0100 |
| commit | dafec4a51542b76a926b390f0cafa6c715a54c49 (patch) | |
| tree | b9088b609725b87ec1ef5f6a5359b3454ed4519c /tests/quick/fs/10.linux-boot/ref/arm/linux | |
| parent | c661cc75eca97989d72c513550b7a63e995a3982 (diff) | |
| download | gem5-dafec4a51542b76a926b390f0cafa6c715a54c49.tar.xz | |
stats: update and fix e273e86a873d
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux')
7 files changed, 455 insertions, 455 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt index 85c0f1360..a1b437e07 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu sim_ticks 2783854535000 # Number of ticks simulated final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1008697 # Simulator instruction rate (inst/s) -host_op_rate 1227927 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19668230366 # Simulator tick rate (ticks/s) -host_mem_usage 576064 # Number of bytes of host memory used -host_seconds 141.54 # Real time elapsed on the host +host_inst_rate 787133 # Simulator instruction rate (inst/s) +host_op_rate 958208 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15348024787 # Simulator tick rate (ticks/s) +host_mem_usage 576068 # Number of bytes of host memory used +host_seconds 181.38 # Real time elapsed on the host sim_insts 142771651 # Number of instructions simulated sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -119,9 +119,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31525949 # DTB read hits +system.cpu.dtb.read_hits 31525950 # DTB read hits system.cpu.dtb.read_misses 8580 # DTB read misses -system.cpu.dtb.write_hits 23124104 # DTB write hits +system.cpu.dtb.write_hits 23124105 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -132,12 +132,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534529 # DTB read accesses -system.cpu.dtb.write_accesses 23125552 # DTB write accesses +system.cpu.dtb.read_accesses 31534530 # DTB read accesses +system.cpu.dtb.write_accesses 23125553 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54650053 # DTB hits +system.cpu.dtb.hits 54650055 # DTB hits system.cpu.dtb.misses 10028 # DTB misses -system.cpu.dtb.accesses 54660081 # DTB accesses +system.cpu.dtb.accesses 54660083 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -220,7 +220,7 @@ system.cpu.num_conditional_control_insts 18730275 # nu system.cpu.num_int_insts 153161279 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions system.cpu.num_int_register_reads 285057575 # number of times the integer registers were read -system.cpu.num_int_register_writes 107178464 # number of times the integer registers were written +system.cpu.num_int_register_writes 107178468 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written system.cpu.num_cc_register_reads 530849543 # number of times the CC registers were read @@ -270,9 +270,9 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class::total 177218432 # Class of executed instruction system.cpu.dcache.tags.replacements 819392 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53783870 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 53783872 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.597765 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.597768 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -282,22 +282,22 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219235080 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219235080 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 30128800 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30128800 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22339791 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22339791 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 219235088 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219235088 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 30128801 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30128801 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22339792 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22339792 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52468591 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52468591 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52863656 # number of overall hits -system.cpu.dcache.overall_hits::total 52863656 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 52468593 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52468593 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52863658 # number of overall hits +system.cpu.dcache.overall_hits::total 52863658 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 396281 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 396281 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses @@ -312,20 +312,20 @@ system.cpu.dcache.demand_misses::cpu.data 697944 # n system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses system.cpu.dcache.overall_misses::total 814065 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30525081 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30525081 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641454 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641454 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 30525082 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30525082 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641455 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641455 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53166535 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53166535 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53677721 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53677721 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 53166537 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53166537 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53677723 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53677723 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 9e43d8fd4..317518f92 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.802883 # Nu sim_ticks 2802882797500 # Number of ticks simulated final_tick 2802882797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 797664 # Simulator instruction rate (inst/s) -host_op_rate 971941 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15227033289 # Simulator tick rate (ticks/s) -host_mem_usage 590380 # Number of bytes of host memory used -host_seconds 184.07 # Real time elapsed on the host +host_inst_rate 748827 # Simulator instruction rate (inst/s) +host_op_rate 912434 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14294755935 # Simulator tick rate (ticks/s) +host_mem_usage 590384 # Number of bytes of host memory used +host_seconds 196.08 # Real time elapsed on the host sim_insts 146828219 # Number of instructions simulated sim_ops 178907974 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -138,9 +138,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570 system.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 20339693 # DTB read hits +system.cpu0.dtb.read_hits 20339694 # DTB read hits system.cpu0.dtb.read_misses 6871 # DTB read misses -system.cpu0.dtb.write_hits 16391003 # DTB write hits +system.cpu0.dtb.write_hits 16391004 # DTB write hits system.cpu0.dtb.write_misses 1093 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -151,12 +151,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 20346564 # DTB read accesses -system.cpu0.dtb.write_accesses 16392096 # DTB write accesses +system.cpu0.dtb.read_accesses 20346565 # DTB read accesses +system.cpu0.dtb.write_accesses 16392097 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 36730696 # DTB hits +system.cpu0.dtb.hits 36730698 # DTB hits system.cpu0.dtb.misses 7964 # DTB misses -system.cpu0.dtb.accesses 36738660 # DTB accesses +system.cpu0.dtb.accesses 36738662 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -239,7 +239,7 @@ system.cpu0.num_conditional_control_insts 13204192 # n system.cpu0.num_int_insts 100762477 # number of integer instructions system.cpu0.num_fp_insts 9755 # number of float instructions system.cpu0.num_int_register_reads 182456959 # number of times the integer registers were read -system.cpu0.num_int_register_writes 69135393 # number of times the integer registers were written +system.cpu0.num_int_register_writes 69135397 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written system.cpu0.num_cc_register_reads 349970686 # number of times the CC registers were read @@ -289,9 +289,9 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu0.op_class::total 116881836 # Class of executed instruction system.cpu0.dcache.tags.replacements 693478 # number of replacements system.cpu0.dcache.tags.tagsinuse 494.853458 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 35932313 # Total number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 35932315 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 693990 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 51.776413 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 51.776416 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853458 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy @@ -301,22 +301,22 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 74113669 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 74113669 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 19108530 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 19108530 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15690319 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15690319 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 74113673 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 74113673 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 19108531 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 19108531 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15690320 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15690320 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346085 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 346085 # number of SoftPFReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379623 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 379623 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363046 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 363046 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34798849 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34798849 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35144934 # number of overall hits -system.cpu0.dcache.overall_hits::total 35144934 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 34798851 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34798851 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35144936 # number of overall hits +system.cpu0.dcache.overall_hits::total 35144936 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 373100 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 373100 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 295799 # number of WriteReq misses @@ -331,20 +331,20 @@ system.cpu0.dcache.demand_misses::cpu0.data 668899 # system.cpu0.dcache.demand_misses::total 668899 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 769220 # number of overall misses system.cpu0.dcache.overall_misses::total 769220 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481630 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 19481630 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986118 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 15986118 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481631 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 19481631 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986119 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 15986119 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446406 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 446406 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386363 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 386363 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381477 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 381477 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 35467748 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 35467748 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 35914154 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 35914154 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 35467750 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 35467750 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 35914156 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 35914156 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 491924c10..422d7eb7f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu sim_ticks 2783854535000 # Number of ticks simulated final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 888036 # Simulator instruction rate (inst/s) -host_op_rate 1081042 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17315504636 # Simulator tick rate (ticks/s) -host_mem_usage 573724 # Number of bytes of host memory used -host_seconds 160.77 # Real time elapsed on the host +host_inst_rate 766060 # Simulator instruction rate (inst/s) +host_op_rate 932555 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14937129777 # Simulator tick rate (ticks/s) +host_mem_usage 573732 # Number of bytes of host memory used +host_seconds 186.37 # Real time elapsed on the host sim_insts 142771651 # Number of instructions simulated sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -119,9 +119,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31525949 # DTB read hits +system.cpu.dtb.read_hits 31525950 # DTB read hits system.cpu.dtb.read_misses 8580 # DTB read misses -system.cpu.dtb.write_hits 23124104 # DTB write hits +system.cpu.dtb.write_hits 23124105 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -132,12 +132,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534529 # DTB read accesses -system.cpu.dtb.write_accesses 23125552 # DTB write accesses +system.cpu.dtb.read_accesses 31534530 # DTB read accesses +system.cpu.dtb.write_accesses 23125553 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54650053 # DTB hits +system.cpu.dtb.hits 54650055 # DTB hits system.cpu.dtb.misses 10028 # DTB misses -system.cpu.dtb.accesses 54660081 # DTB accesses +system.cpu.dtb.accesses 54660083 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -220,7 +220,7 @@ system.cpu.num_conditional_control_insts 18730275 # nu system.cpu.num_int_insts 153161279 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions system.cpu.num_int_register_reads 285057575 # number of times the integer registers were read -system.cpu.num_int_register_writes 107178464 # number of times the integer registers were written +system.cpu.num_int_register_writes 107178468 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written system.cpu.num_cc_register_reads 530849543 # number of times the CC registers were read @@ -270,9 +270,9 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class::total 177218432 # Class of executed instruction system.cpu.dcache.tags.replacements 819392 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53783870 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 53783872 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.597765 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.597768 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -282,22 +282,22 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219235080 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219235080 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 30128800 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30128800 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22339791 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22339791 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 219235088 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219235088 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 30128801 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30128801 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22339792 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22339792 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52468591 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52468591 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52863656 # number of overall hits -system.cpu.dcache.overall_hits::total 52863656 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 52468593 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52468593 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52863658 # number of overall hits +system.cpu.dcache.overall_hits::total 52863658 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 396281 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 396281 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses @@ -312,20 +312,20 @@ system.cpu.dcache.demand_misses::cpu.data 697944 # n system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses system.cpu.dcache.overall_misses::total 814065 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30525081 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30525081 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641454 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641454 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 30525082 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30525082 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641455 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641455 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53166535 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53166535 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53677721 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53677721 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 53166537 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53166537 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53677723 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53677723 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 89a189084..2dd6529c6 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -4,13 +4,13 @@ sim_seconds 2.869789 # Nu sim_ticks 2869788970000 # Number of ticks simulated final_tick 2869788970000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 543935 # Simulator instruction rate (inst/s) -host_op_rate 657921 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11865725522 # Simulator tick rate (ticks/s) -host_mem_usage 611884 # Number of bytes of host memory used -host_seconds 241.86 # Real time elapsed on the host -sim_insts 131553572 # Number of instructions simulated -sim_ops 159121620 # Number of ops (including micro ops) simulated +host_inst_rate 480288 # Simulator instruction rate (inst/s) +host_op_rate 580935 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10477281069 # Simulator tick rate (ticks/s) +host_mem_usage 611892 # Number of bytes of host memory used +host_seconds 273.91 # Real time elapsed on the host +sim_insts 131553574 # Number of instructions simulated +sim_ops 159121622 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory @@ -286,12 +286,12 @@ system.physmem.wrPerTurnAround::172-175 2 0.03% 99.97% # Wr system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 6684 # Writes before turning the bus around for reads -system.physmem.totQLat 4572923146 # Total ticks spent queuing -system.physmem.totMemAccLat 8287466896 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 4572903146 # Total ticks spent queuing +system.physmem.totMemAccLat 8287446896 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 990545000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23082.86 # Average queueing delay per DRAM burst +system.physmem.avgQLat 23082.76 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41832.86 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 41832.76 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.42 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.22 # Average system read bandwidth in MiByte/s @@ -313,28 +313,28 @@ system.physmem_0.preEnergy 190001625 # En system.physmem_0.readEnergy 823219800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 453593520 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 84729045645 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1647547992750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1921532542260 # Total energy per rank (pJ) +system.physmem_0.actBackEnergy 84729042225 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647547995750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1921532541840 # Total energy per rank (pJ) system.physmem_0.averagePower 669.573415 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2740710561422 # Time in different power states +system.physmem_0.memoryStateTime::IDLE 2740710565422 # Time in different power states system.physmem_0.memoryStateTime::REF 95828460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33249852578 # Time in different power states +system.physmem_0.memoryStateTime::ACT 33249848578 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 326047680 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 177903000 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 722022600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 425178720 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 84061532610 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1648133530500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1921286682870 # Total energy per rank (pJ) +system.physmem_1.actBackEnergy 84061530045 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1648133532750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1921286682555 # Total energy per rank (pJ) system.physmem_1.averagePower 669.487743 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2741691176386 # Time in different power states +system.physmem_1.memoryStateTime::IDLE 2741691180386 # Time in different power states system.physmem_1.memoryStateTime::REF 95828460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32266572364 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32266568364 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -425,9 +425,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6549 system.cpu0.dtb.walker.walkRequestOrigin::total 14492 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25156507 # DTB read hits +system.cpu0.dtb.read_hits 25156508 # DTB read hits system.cpu0.dtb.read_misses 6829 # DTB read misses -system.cpu0.dtb.write_hits 18749940 # DTB write hits +system.cpu0.dtb.write_hits 18749941 # DTB write hits system.cpu0.dtb.write_misses 1114 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -438,12 +438,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 1731 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25163336 # DTB read accesses -system.cpu0.dtb.write_accesses 18751054 # DTB write accesses +system.cpu0.dtb.read_accesses 25163337 # DTB read accesses +system.cpu0.dtb.write_accesses 18751055 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 43906447 # DTB hits +system.cpu0.dtb.hits 43906449 # DTB hits system.cpu0.dtb.misses 7943 # DTB misses -system.cpu0.dtb.accesses 43914390 # DTB accesses +system.cpu0.dtb.accesses 43914392 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -533,19 +533,19 @@ system.cpu0.numWorkItemsStarted 0 # nu system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed -system.cpu0.committedInsts 115352403 # Number of instructions committed -system.cpu0.committedOps 139380192 # Number of ops (including micro ops) committed +system.cpu0.committedInsts 115352405 # Number of instructions committed +system.cpu0.committedOps 139380194 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 123360698 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9756 # Number of float alu accesses system.cpu0.num_func_calls 12675179 # number of times a function call or return occured system.cpu0.num_conditional_control_insts 15700187 # number of instructions that are conditional controls system.cpu0.num_int_insts 123360698 # number of integer instructions system.cpu0.num_fp_insts 9756 # number of float instructions -system.cpu0.num_int_register_reads 227087076 # number of times the integer registers were read -system.cpu0.num_int_register_writes 85717148 # number of times the integer registers were written +system.cpu0.num_int_register_reads 227087077 # number of times the integer registers were read +system.cpu0.num_int_register_writes 85717152 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7496 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 504942673 # number of times the CC registers were read +system.cpu0.num_cc_register_reads 504942676 # number of times the CC registers were read system.cpu0.num_cc_register_writes 52291767 # number of times the CC registers were written system.cpu0.num_mem_refs 45042977 # number of memory refs system.cpu0.num_load_insts 25408336 # Number of load instructions @@ -592,9 +592,9 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu0.op_class::total 143145074 # Class of executed instruction system.cpu0.dcache.tags.replacements 692159 # number of replacements system.cpu0.dcache.tags.tagsinuse 489.914647 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43035504 # Total number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 43035506 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 692671 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 62.129790 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 62.129793 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1151827000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.914647 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.956865 # Average percentage of cache occupancy @@ -604,22 +604,22 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 103 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88449495 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88449495 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 23895287 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23895287 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 18018355 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18018355 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 88449499 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88449499 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 23895288 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23895288 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 18018356 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18018356 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319106 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 319106 # number of SoftPFReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365501 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 365501 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362365 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 362365 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 41913642 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41913642 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 42232748 # number of overall hits -system.cpu0.dcache.overall_hits::total 42232748 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 41913644 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41913644 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 42232750 # number of overall hits +system.cpu0.dcache.overall_hits::total 42232750 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 396096 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 396096 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 325040 # number of WriteReq misses @@ -634,8 +634,8 @@ system.cpu0.dcache.demand_misses::cpu0.data 721136 # system.cpu0.dcache.demand_misses::total 721136 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 848828 # number of overall misses system.cpu0.dcache.overall_misses::total 848828 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5078700000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5078700000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5078698000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5078698000 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5729362000 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 5729362000 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 329182500 # number of LoadLockedReq miss cycles @@ -644,24 +644,24 @@ system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472585500 system.cpu0.dcache.StoreCondReq_miss_latency::total 472585500 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1446500 # number of StoreCondFailReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1446500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 10808062000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 10808062000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 10808062000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 10808062000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291383 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 24291383 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 18343395 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 18343395 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 10808060000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 10808060000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 10808060000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 10808060000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291384 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 24291384 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 18343396 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 18343396 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446798 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 446798 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387085 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 387085 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382166 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 382166 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 42634778 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42634778 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 43081576 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43081576 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 42634780 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42634780 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 43081578 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43081578 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016306 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.016306 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017720 # miss rate for WriteReq accesses @@ -676,8 +676,8 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016914 system.cpu0.dcache.demand_miss_rate::total 0.016914 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019703 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.019703 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12821.891663 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12821.891663 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12821.886613 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12821.886613 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17626.636722 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 17626.636722 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15251.227761 # average LoadLockedReq miss latency @@ -686,10 +686,10 @@ system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23866.749154 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23866.749154 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14987.550199 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14987.550199 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12732.923513 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12732.923513 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14987.547425 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14987.547425 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12732.921157 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12732.921157 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -726,8 +726,8 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28463 system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60255 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4312933000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4312933000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4312931000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4312931000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5404322000 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5404322000 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1615427000 # number of SoftPFReq MSHR miss cycles @@ -738,10 +738,10 @@ system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 452825500 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 452825500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1405500 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1405500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9717255000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9717255000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11332682000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11332682000 # number of overall MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9717253000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9717253000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11332680000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11332680000 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628901000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628901000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628901000 # number of overall MSHR uncacheable cycles @@ -760,8 +760,8 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016321 system.cpu0.dcache.demand_mshr_miss_rate::total 0.016321 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018484 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.018484 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11631.050236 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11631.050236 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11631.044842 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11631.044842 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16626.636722 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16626.636722 # average WriteReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16076.779921 # average SoftPFReq mshr miss latency @@ -772,10 +772,10 @@ system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22868.819757 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22868.819757 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13964.542748 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13964.542748 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14231.066362 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14231.066362 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13964.539873 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13964.539873 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14231.063850 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14231.063850 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208508.461248 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208508.461248 # average ReadReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110014.123309 # average overall mshr uncacheable latency @@ -977,18 +977,18 @@ system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2047795000 system.cpu0.l2cache.ReadExReq_miss_latency::total 2047795000 # number of ReadExReq miss cycles system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2416123000 # number of ReadCleanReq miss cycles system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2416123000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2805930000 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2805930000 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2805928000 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2805928000 # number of ReadSharedReq miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5649500 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3340000 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2416123000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 4853725000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 7278837500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 4853723000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 7278835500 # number of demand (read+write) miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5649500 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3340000 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2416123000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 4853725000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 7278837500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 4853723000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 7278835500 # number of overall miss cycles system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10462 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4713 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::total 15175 # number of ReadReq accesses(hits+misses) @@ -1056,18 +1056,18 @@ system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 47834.501285 system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47834.501285 # average ReadExReq miss latency system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53359.606890 # average ReadCleanReq miss latency system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53359.606890 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29797.381248 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29797.381248 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29797.360009 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29797.360009 # average ReadSharedReq miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23857.142857 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53359.606890 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35434.598509 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 39857.178450 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35434.583908 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 39857.167498 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23857.142857 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53359.606890 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35434.598509 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 39857.178450 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35434.583908 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 39857.167498 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1124,8 +1124,8 @@ system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69277 system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2500000 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 6793500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13785840950 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13785840950 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13785822950 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13785822950 # number of HardPFReq MSHR miss cycles system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1059758500 # number of UpgradeReq MSHR miss cycles system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1059758500 # number of UpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 304568000 # number of SCUpgradeReq MSHR miss cycles @@ -1136,19 +1136,19 @@ system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1683019500 system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1683019500 # number of ReadExReq MSHR miss cycles system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2144443000 # number of ReadCleanReq MSHR miss cycles system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2144443000 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2236277000 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2236277000 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2236275000 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2236275000 # number of ReadSharedReq MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2500000 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2144443000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3919296500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 6070533000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3919294500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 6070531000 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2500000 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2144443000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3919296500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13785840950 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 19856373950 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3919294500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13785822950 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 19856353950 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 743751500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6374150500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7117902000 # number of ReadReq MSHR uncacheable cycles @@ -1186,8 +1186,8 @@ system.cpu0.l2cache.overall_mshr_miss_rate::total 0.236165 system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 18561.475410 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.869237 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53108.869237 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.799894 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53108.799894 # average HardPFReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19237.556274 # average UpgradeReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19237.556274 # average UpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15382.999141 # average SCUpgradeReq mshr miss latency @@ -1198,19 +1198,19 @@ system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40410.571936 system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40410.571936 # average ReadExReq mshr miss latency system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average ReadCleanReq mshr miss latency system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47359.606890 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23755.558388 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23755.558388 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23755.537143 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23755.537143 # average ReadSharedReq mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28863.987186 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33459.182830 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28863.972456 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33459.171806 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28863.987186 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.869237 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45024.974490 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28863.972456 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.799894 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45024.929140 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200495.423377 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174398.539717 # average ReadReq mshr uncacheable latency @@ -2512,30 +2512,30 @@ system.l2c.ReadExReq_miss_latency::total 1749515500 # nu system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 703500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 174000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1440677500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 776893500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 12971819632 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 776891500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.inst 189843000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.data 77251000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 16119848689 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 16119828689 # number of ReadSharedReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 703500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 174000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.inst 1440677500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1864554000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12971819632 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1864552000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.inst 189843000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 739106000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 17869364189 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 17869344189 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 703500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 174000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.inst 1440677500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1864554000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12971819632 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1864552000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.inst 189843000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 739106000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of overall miss cycles -system.l2c.overall_miss_latency::total 17869364189 # number of overall miss cycles +system.l2c.overall_miss_latency::total 17869344189 # number of overall miss cycles system.l2c.WritebackDirty_accesses::writebacks 260994 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackDirty_accesses::total 260994 # number of WritebackDirty accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 40660 # number of UpgradeReq accesses(hits+misses) @@ -2628,30 +2628,30 @@ system.l2c.ReadExReq_avg_miss_latency::total 90185.860096 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 100500 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 87000 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 81824.132447 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87665.707515 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87665.481833 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82973.339161 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90246.495327 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 95084.401110 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 95084.283138 # average ReadSharedReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 100500 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 81824.132447 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 92167.770638 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 92167.671775 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 82973.339161 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 83167.098008 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 94581.430199 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 94581.324341 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 100500 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 81824.132447 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 92167.770638 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 92167.671775 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 82973.339161 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 83167.098008 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 94581.430199 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 94581.324341 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2732,30 +2732,30 @@ system.l2c.ReadExReq_mshr_miss_latency::total 1555525500 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 633500 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 154000 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1264511501 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 688273500 # 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number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 154000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.inst 1264511501 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 1662254000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11632976638 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1662252000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 166489000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 650235501 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 15979479699 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 15979459699 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 633500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 154000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 1264511501 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 1662254000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11632976638 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1662252000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 166489000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 650235501 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 15979479699 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 15979459699 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 581355000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801887500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11263000 # number of ReadReq MSHR uncacheable cycles @@ -2816,30 +2816,30 @@ system.l2c.ReadExReq_avg_mshr_miss_latency::total 80185.860096 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77665.707515 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77665.481833 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80245.912383 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85088.039022 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85087.921041 # average ReadSharedReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82167.770638 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82167.671775 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 84584.657278 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 84584.551411 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82167.770638 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82167.671775 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 84584.657278 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 84584.551411 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182495.203196 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average ReadReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index db033150d..e1254a2d4 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,13 +4,13 @@ sim_seconds 2.909587 # Nu sim_ticks 2909586837500 # Number of ticks simulated final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 581636 # Simulator instruction rate (inst/s) -host_op_rate 701272 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15048595995 # Simulator tick rate (ticks/s) -host_mem_usage 573724 # Number of bytes of host memory used -host_seconds 193.35 # Real time elapsed on the host -sim_insts 112457033 # Number of instructions simulated -sim_ops 135588117 # Number of ops (including micro ops) simulated +host_inst_rate 495886 # Simulator instruction rate (inst/s) +host_op_rate 597884 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12830006266 # Simulator tick rate (ticks/s) +host_mem_usage 573732 # Number of bytes of host memory used +host_seconds 226.78 # Real time elapsed on the host +sim_insts 112457035 # Number of instructions simulated +sim_ops 135588119 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory @@ -261,12 +261,12 @@ system.physmem.wrPerTurnAround::148-151 1 0.02% 99.89% # Wr system.physmem.wrPerTurnAround::160-163 4 0.07% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::176-179 2 0.04% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5615 # Writes before turning the bus around for reads -system.physmem.totQLat 1624802000 # Total ticks spent queuing -system.physmem.totMemAccLat 4747089500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1624800000 # Total ticks spent queuing +system.physmem.totMemAccLat 4747087500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 832610000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9757.28 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9757.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28507.28 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28507.27 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s @@ -302,14 +302,14 @@ system.physmem_1.preEnergy 116362125 # En system.physmem_1.readEnergy 596668800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 370733760 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 190039717920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 88049301345 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1668512802000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1947898845990 # Total energy per rank (pJ) +system.physmem_1.actBackEnergy 88049300490 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668512802750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1947898845885 # Total energy per rank (pJ) system.physmem_1.averagePower 669.477277 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2775567504000 # Time in different power states +system.physmem_1.memoryStateTime::IDLE 2775567506000 # Time in different power states system.physmem_1.memoryStateTime::REF 97157320000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 36861865500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 36861863500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -389,9 +389,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7382 system.cpu.dtb.walker.walkRequestOrigin::total 16928 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24520655 # DTB read hits +system.cpu.dtb.read_hits 24520656 # DTB read hits system.cpu.dtb.read_misses 8124 # DTB read misses -system.cpu.dtb.write_hits 19606816 # DTB write hits +system.cpu.dtb.write_hits 19606817 # DTB write hits system.cpu.dtb.write_misses 1422 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -402,12 +402,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24528779 # DTB read accesses -system.cpu.dtb.write_accesses 19608238 # DTB write accesses +system.cpu.dtb.read_accesses 24528780 # DTB read accesses +system.cpu.dtb.write_accesses 19608239 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44127471 # DTB hits +system.cpu.dtb.hits 44127473 # DTB hits system.cpu.dtb.misses 9546 # DTB misses -system.cpu.dtb.accesses 44137017 # DTB accesses +system.cpu.dtb.accesses 44137019 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -491,19 +491,19 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu.committedInsts 112457033 # Number of instructions committed -system.cpu.committedOps 135588117 # Number of ops (including micro ops) committed +system.cpu.committedInsts 112457035 # Number of instructions committed +system.cpu.committedOps 135588119 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 119893391 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses system.cpu.num_func_calls 9892146 # number of times a function call or return occured system.cpu.num_conditional_control_insts 15230571 # number of instructions that are conditional controls system.cpu.num_int_insts 119893391 # number of integer instructions system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218063465 # number of times the integer registers were read -system.cpu.num_int_register_writes 82646448 # number of times the integer registers were written +system.cpu.num_int_register_reads 218063466 # number of times the integer registers were read +system.cpu.num_int_register_writes 82646452 # number of times the integer registers were written system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489743456 # number of times the CC registers were read +system.cpu.num_cc_register_reads 489743459 # number of times the CC registers were read system.cpu.num_cc_register_writes 51893999 # number of times the CC registers were written system.cpu.num_mem_refs 45407924 # number of memory refs system.cpu.num_load_insts 24843119 # Number of load instructions @@ -550,9 +550,9 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class::total 138708215 # Class of executed instruction system.cpu.dcache.tags.replacements 819223 # number of replacements system.cpu.dcache.tags.tagsinuse 511.702328 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43236235 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 43236237 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 819735 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.744161 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.744164 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.702328 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999419 # Average percentage of cache occupancy @@ -563,22 +563,22 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177112671 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177112671 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23112983 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23112983 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18824226 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18824226 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 177112679 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177112679 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23112984 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23112984 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18824227 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18824227 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 392786 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 392786 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 443250 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 443250 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460223 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460223 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41937209 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41937209 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42329995 # number of overall hits -system.cpu.dcache.overall_hits::total 42329995 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 41937211 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41937211 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42329997 # number of overall hits +system.cpu.dcache.overall_hits::total 42329997 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 399912 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 399912 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 298709 # number of WriteReq misses @@ -605,20 +605,20 @@ system.cpu.dcache.demand_miss_latency::cpu.data 25589348500 system.cpu.dcache.demand_miss_latency::total 25589348500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 25589348500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 25589348500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23512895 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23512895 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19122935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19122935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 23512896 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23512896 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19122936 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19122936 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 511167 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 511167 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466006 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 466006 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460225 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42635830 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42635830 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43146997 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43146997 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 42635832 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42635832 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43146999 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43146999 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017008 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.017008 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015620 # miss rate for WriteReq accesses @@ -760,12 +760,12 @@ system.cpu.icache.demand_misses::cpu.inst 1696239 # n system.cpu.icache.demand_misses::total 1696239 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1696239 # number of overall misses system.cpu.icache.overall_misses::total 1696239 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24272134000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24272134000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24272134000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24272134000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24272134000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24272134000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24272132000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24272132000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24272132000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24272132000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24272132000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24272132000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 115554258 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 115554258 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 115554258 # number of demand (read+write) accesses @@ -778,12 +778,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.014679 system.cpu.icache.demand_miss_rate::total 0.014679 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.014679 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.014679 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.383289 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14309.383289 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14309.383289 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14309.383289 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.382109 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14309.382109 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.382109 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14309.382109 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.382109 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14309.382109 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -802,12 +802,12 @@ system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22575895000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22575895000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22575895000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22575895000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22575895000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22575895000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22575893000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22575893000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22575893000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22575893000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22575893000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22575893000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1142541000 # number of overall MSHR uncacheable cycles @@ -818,12 +818,12 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014679 system.cpu.icache.demand_mshr_miss_rate::total 0.014679 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014679 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.014679 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.383289 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.383289 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.383289 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.383289 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.382109 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.382109 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.382109 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.382109 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.382109 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.382109 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency @@ -914,20 +914,20 @@ system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16382558000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 16382558000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2351294500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2351294500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2351292500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2351292500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1615422500 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 1615422500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 957500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 266000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2351294500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2351292500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 17997980500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20350498500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20350496500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 957500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 266000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2351294500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 2351292500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 17997980500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20350498500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20350496500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7814 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4041 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 11855 # number of ReadReq accesses(hits+misses) @@ -987,20 +987,20 @@ system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127082.280298 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127082.280298 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130787.323395 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130787.323395 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130787.212148 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130787.212148 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132705.372546 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132705.372546 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130787.323395 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130787.212148 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127567.444679 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 127931.820611 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 127931.808038 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130787.323395 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130787.212148 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127567.444679 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 127931.820611 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 127931.808038 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1049,20 +1049,20 @@ system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 139000 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15093428000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15093428000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2171514500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2171514500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2171512500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2171512500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1493692500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1493692500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 887500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 246000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2171514500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2171512500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16587120500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18759768500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18759766500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 887500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 246000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171514500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171512500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16587120500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18759768500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18759766500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888804000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6918570000 # number of ReadReq MSHR uncacheable cycles @@ -1101,20 +1101,20 @@ system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117082.280298 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117082.280298 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120787.323395 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120787.323395 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120787.212148 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120787.212148 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122705.372546 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122705.372546 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120787.212148 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117931.808038 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.212148 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.808038 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.532404 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.149402 # average ReadReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index bc56e0971..cde05e946 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783854 # Nu sim_ticks 2783853866500 # Number of ticks simulated final_tick 2783853866500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 806647 # Simulator instruction rate (inst/s) -host_op_rate 981963 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15728650419 # Simulator tick rate (ticks/s) -host_mem_usage 576800 # Number of bytes of host memory used -host_seconds 176.99 # Real time elapsed on the host +host_inst_rate 760140 # Simulator instruction rate (inst/s) +host_op_rate 925348 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14821821018 # Simulator tick rate (ticks/s) +host_mem_usage 577060 # Number of bytes of host memory used +host_seconds 187.82 # Real time elapsed on the host sim_insts 142770436 # Number of instructions simulated sim_ops 173800089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -136,9 +136,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4680 system.cpu0.dtb.walker.walkRequestOrigin::total 10381 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 15997245 # DTB read hits +system.cpu0.dtb.read_hits 15997246 # DTB read hits system.cpu0.dtb.read_misses 4805 # DTB read misses -system.cpu0.dtb.write_hits 11281011 # DTB write hits +system.cpu0.dtb.write_hits 11281012 # DTB write hits system.cpu0.dtb.write_misses 896 # DTB write misses system.cpu0.dtb.flush_tlb 2813 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA @@ -149,12 +149,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 769 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 202 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 16002050 # DTB read accesses -system.cpu0.dtb.write_accesses 11281907 # DTB write accesses +system.cpu0.dtb.read_accesses 16002051 # DTB read accesses +system.cpu0.dtb.write_accesses 11281908 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 27278256 # DTB hits +system.cpu0.dtb.hits 27278258 # DTB hits system.cpu0.dtb.misses 5701 # DTB misses -system.cpu0.dtb.accesses 27283957 # DTB accesses +system.cpu0.dtb.accesses 27283959 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -237,7 +237,7 @@ system.cpu0.num_conditional_control_insts 9459738 # n system.cpu0.num_int_insts 77491639 # number of integer instructions system.cpu0.num_fp_insts 5273 # number of float instructions system.cpu0.num_int_register_reads 144069521 # number of times the integer registers were read -system.cpu0.num_int_register_writes 54447635 # number of times the integer registers were written +system.cpu0.num_int_register_writes 54447639 # number of times the integer registers were written system.cpu0.num_fp_register_reads 4051 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1224 # number of times the floating registers were written system.cpu0.num_cc_register_reads 268878195 # number of times the CC registers were read @@ -287,9 +287,9 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu0.op_class::total 89752341 # Class of executed instruction system.cpu0.dcache.tags.replacements 819388 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 53783376 # Total number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 53783378 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 819900 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 65.597483 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 65.597485 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.830508 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.166666 # Average occupied blocks per requestor @@ -301,14 +301,14 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 219233084 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 219233084 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15305417 # number of ReadReq hits +system.cpu0.dcache.tags.tag_accesses 219233092 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 219233092 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15305418 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 14823075 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 30128492 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10893994 # number of WriteReq hits +system.cpu0.dcache.ReadReq_hits::total 30128493 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 10893995 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu1.data 11445651 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 22339645 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 22339646 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185752 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209291 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 395043 # number of SoftPFReq hits @@ -318,12 +318,12 @@ system.cpu0.dcache.LoadLockedReq_hits::total 457316 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236694 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223428 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 26199411 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 26199413 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu1.data 26268726 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 52468137 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 26385163 # number of overall hits +system.cpu0.dcache.demand_hits::total 52468139 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 26385165 # number of overall hits system.cpu0.dcache.overall_hits::cpu1.data 26478017 # number of overall hits -system.cpu0.dcache.overall_hits::total 52863180 # number of overall hits +system.cpu0.dcache.overall_hits::total 52863182 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 197452 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu1.data 198861 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 396313 # number of ReadReq misses @@ -344,12 +344,12 @@ system.cpu0.dcache.demand_misses::total 697978 # nu system.cpu0.dcache.overall_misses::cpu0.data 389311 # number of overall misses system.cpu0.dcache.overall_misses::cpu1.data 424732 # number of overall misses system.cpu0.dcache.overall_misses::total 814043 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 15502869 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu0.data 15502870 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu1.data 15021936 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 30524805 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 11031501 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 30524806 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 11031502 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu1.data 11609809 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 22641310 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 22641311 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240104 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 271004 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 511108 # number of SoftPFReq accesses(hits+misses) @@ -359,12 +359,12 @@ system.cpu0.dcache.LoadLockedReq_accesses::total 465945 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236694 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223430 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 26534370 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 26534372 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::cpu1.data 26631745 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 53166115 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 26774474 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::total 53166117 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 26774476 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu1.data 26902749 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 53677223 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 53677225 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012736 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013238 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 0b3858068..444bbfba5 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -4,13 +4,13 @@ sim_seconds 2.903880 # Nu sim_ticks 2903879904500 # Number of ticks simulated final_tick 2903879904500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 558564 # Simulator instruction rate (inst/s) -host_op_rate 673462 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14421337908 # Simulator tick rate (ticks/s) -host_mem_usage 577056 # Number of bytes of host memory used -host_seconds 201.36 # Real time elapsed on the host -sim_insts 112472356 # Number of instructions simulated -sim_ops 135608165 # Number of ops (including micro ops) simulated +host_inst_rate 505304 # Simulator instruction rate (inst/s) +host_op_rate 609246 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13046252349 # Simulator tick rate (ticks/s) +host_mem_usage 577060 # Number of bytes of host memory used +host_seconds 222.58 # Real time elapsed on the host +sim_insts 112472358 # Number of instructions simulated +sim_ops 135608167 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory @@ -291,12 +291,12 @@ system.physmem.wrPerTurnAround::176-179 1 0.02% 99.97% # Wr system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::188-191 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5814 # Writes before turning the bus around for reads -system.physmem.totQLat 1475229250 # Total ticks spent queuing -system.physmem.totMemAccLat 4623710500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1475227250 # Total ticks spent queuing +system.physmem.totMemAccLat 4623708500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 839595000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8785.36 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8785.35 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27535.36 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27535.35 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.70 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s @@ -584,9 +584,9 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu0.op_class::total 68839780 # Class of executed instruction system.cpu0.dcache.tags.replacements 819212 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.827217 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43241766 # Total number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 43241768 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 819724 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.751616 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.751619 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1013369500 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 311.161528 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu1.data 200.665688 # Average occupied blocks per requestor @@ -599,14 +599,14 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::1 369 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177132709 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177132709 # Number of data accesses +system.cpu0.dcache.tags.tag_accesses 177132717 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 177132717 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 11490299 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11626239 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23116538 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 11626240 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23116539 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 9270780 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9555063 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18825843 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 9555064 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18825844 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200211 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::cpu1.data 192673 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 392884 # number of SoftPFReq hits @@ -617,11 +617,11 @@ system.cpu0.dcache.StoreCondReq_hits::cpu0.data 232922 system.cpu0.dcache.StoreCondReq_hits::cpu1.data 227346 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 460268 # number of StoreCondReq hits system.cpu0.dcache.demand_hits::cpu0.data 20761079 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 21181302 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41942381 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 21181304 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41942383 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::cpu0.data 20961290 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21373975 # number of overall hits -system.cpu0.dcache.overall_hits::total 42335265 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 21373977 # number of overall hits +system.cpu0.dcache.overall_hits::total 42335267 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 199689 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu1.data 200118 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 399807 # number of ReadReq misses @@ -660,11 +660,11 @@ system.cpu0.dcache.overall_miss_latency::cpu0.data 8732466000 system.cpu0.dcache.overall_miss_latency::cpu1.data 9861594500 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 18594060500 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 11689988 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 11826357 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23516345 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 11826358 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23516346 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 9413501 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9710991 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19124492 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 9710992 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 19124493 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 257183 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 253897 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 511080 # number of SoftPFReq accesses(hits+misses) @@ -675,11 +675,11 @@ system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 232924 system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 227346 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 460270 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::cpu0.data 21103489 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 21537348 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42640837 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 21537350 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42640839 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 21360672 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 21791245 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43151917 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 21791247 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43151919 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.017082 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.016921 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.017001 # miss rate for ReadReq accesses @@ -878,14 +878,14 @@ system.cpu0.icache.overall_misses::cpu0.inst 854412 system.cpu0.icache.overall_misses::cpu1.inst 844092 # number of overall misses system.cpu0.icache.overall_misses::total 1698504 # number of overall misses system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11714597500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11693316500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 23407914000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11693314500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 23407912000 # number of ReadReq miss cycles system.cpu0.icache.demand_miss_latency::cpu0.inst 11714597500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 11693316500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 23407914000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 11693314500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 23407912000 # number of demand (read+write) miss cycles system.cpu0.icache.overall_miss_latency::cpu0.inst 11714597500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 11693316500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 23407914000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 11693314500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 23407912000 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 57466570 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::cpu1.inst 58103866 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 115570436 # number of ReadReq accesses(hits+misses) @@ -905,14 +905,14 @@ system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014868 system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014527 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.014697 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13710.712747 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13853.130346 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13781.488887 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13853.127977 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13781.487709 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13710.712747 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13853.130346 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13781.488887 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13853.127977 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13781.487709 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13710.712747 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13853.130346 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13781.488887 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13853.127977 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13781.487709 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -935,14 +935,14 @@ system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10860185500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10849224500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 21709410000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10849222500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 21709408000 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10860185500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10849224500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 21709410000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10849222500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 21709408000 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10860185500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10849224500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 21709410000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10849222500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 21709408000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 687287000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 687287000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 687287000 # number of overall MSHR uncacheable cycles @@ -957,14 +957,14 @@ system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014868 system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014527 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.014697 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12710.712747 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12853.130346 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12781.488887 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12853.127977 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12781.487709 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12710.712747 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12853.130346 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12781.488887 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12853.127977 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12781.487709 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12710.712747 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12853.130346 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12781.488887 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12853.127977 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12781.487709 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 76179.006872 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 76179.006872 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 76179.006872 # average overall mshr uncacheable latency @@ -1034,9 +1034,9 @@ system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5422 system.cpu1.dtb.walker.walkRequestOrigin::total 11977 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12327133 # DTB read hits +system.cpu1.dtb.read_hits 12327134 # DTB read hits system.cpu1.dtb.read_misses 5631 # DTB read misses -system.cpu1.dtb.write_hits 9951025 # DTB write hits +system.cpu1.dtb.write_hits 9951026 # DTB write hits system.cpu1.dtb.write_misses 924 # DTB write misses system.cpu1.dtb.flush_tlb 2933 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA @@ -1047,12 +1047,12 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 895 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 222 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12332764 # DTB read accesses -system.cpu1.dtb.write_accesses 9951949 # DTB write accesses +system.cpu1.dtb.read_accesses 12332765 # DTB read accesses +system.cpu1.dtb.write_accesses 9951950 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 22278158 # DTB hits +system.cpu1.dtb.hits 22278160 # DTB hits system.cpu1.dtb.misses 6555 # DTB misses -system.cpu1.dtb.accesses 22284713 # DTB accesses +system.cpu1.dtb.accesses 22284715 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1138,19 +1138,19 @@ system.cpu1.numWorkItemsStarted 0 # nu system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 56542374 # Number of instructions committed -system.cpu1.committedOps 68331078 # Number of ops (including micro ops) committed +system.cpu1.committedInsts 56542376 # Number of instructions committed +system.cpu1.committedOps 68331080 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 60434186 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5384 # Number of float alu accesses system.cpu1.num_func_calls 4958421 # number of times a function call or return occured system.cpu1.num_conditional_control_insts 7671718 # number of instructions that are conditional controls system.cpu1.num_int_insts 60434186 # number of integer instructions system.cpu1.num_fp_insts 5384 # number of float instructions -system.cpu1.num_int_register_reads 109968089 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41558580 # number of times the integer registers were written +system.cpu1.num_int_register_reads 109968090 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41558584 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3965 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1422 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 246670954 # number of times the CC registers were read +system.cpu1.num_cc_register_reads 246670957 # number of times the CC registers were read system.cpu1.num_cc_register_writes 26165253 # number of times the CC registers were written system.cpu1.num_mem_refs 22910809 # number of memory refs system.cpu1.num_load_insts 12487681 # Number of load instructions @@ -1510,8 +1510,8 @@ system.l2c.ReadExReq_miss_latency::cpu0.data 4487898000 system.l2c.ReadExReq_miss_latency::cpu1.data 5568339500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 10056237500 # number of ReadExReq miss cycles system.l2c.ReadCleanReq_miss_latency::cpu0.inst 663327500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 794140000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1457467500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 794138000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1457465500 # number of ReadCleanReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.data 478260000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.data 540016500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::total 1018276500 # number of ReadSharedReq miss cycles @@ -1521,18 +1521,18 @@ system.l2c.demand_miss_latency::cpu0.inst 663327500 # n system.l2c.demand_miss_latency::cpu0.data 4966158000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 447000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.itb.walker 83500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 794140000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 794138000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 6108356000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 12532847000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 12532845000 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 251000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 84000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.inst 663327500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 4966158000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 447000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.itb.walker 83500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 794140000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 794138000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 6108356000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 12532847000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 12532845000 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 6059 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 3328 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 5254 # number of ReadReq accesses(hits+misses) @@ -1625,8 +1625,8 @@ system.l2c.ReadExReq_avg_miss_latency::cpu0.data 77402.907849 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76857.688061 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total 77100.056735 # average ReadExReq miss latency system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 81479.855055 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80688.884373 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 81046.961019 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80688.681162 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 81046.849803 # average ReadCleanReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 84933.404369 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 83671.599008 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::total 84259.536616 # average ReadSharedReq miss latency @@ -1636,18 +1636,18 @@ system.l2c.demand_avg_miss_latency::cpu0.inst 81479.855055 system.l2c.demand_avg_miss_latency::cpu0.data 78069.515186 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89400 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 80688.884373 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 80688.681162 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 77415.035993 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 78081.895719 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 78081.883259 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83666.666667 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 84000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 81479.855055 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 78069.515186 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89400 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 80688.884373 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 80688.681162 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 77415.035993 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 78081.895719 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 78081.883259 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1718,8 +1718,8 @@ system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3908088000 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4843839500 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::total 8751927500 # number of ReadExReq MSHR miss cycles system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 581917500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 695720000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 1277637500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 695718000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1277635500 # number of ReadCleanReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 421950000 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 475476500 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::total 897426500 # number of ReadSharedReq MSHR miss cycles @@ -1729,18 +1729,18 @@ system.l2c.demand_mshr_miss_latency::cpu0.inst 581917500 system.l2c.demand_mshr_miss_latency::cpu0.data 4330038000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 397000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 73500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 695720000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 695718000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 5319316000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 10927757000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 10927755000 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 221000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 74000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 581917500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.data 4330038000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 397000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 73500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 695720000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 695718000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 5319316000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 10927757000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 10927755000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 574512000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2654142000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3237757500 # number of ReadReq MSHR uncacheable cycles @@ -1800,8 +1800,8 @@ system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 67402.907849 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66857.688061 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 67100.056735 # average ReadExReq mshr miss latency system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 71479.855055 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70688.884373 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71046.961019 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70688.681162 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71046.849803 # average ReadCleanReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74933.404369 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73671.599008 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74259.536616 # average ReadSharedReq mshr miss latency @@ -1811,18 +1811,18 @@ system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71479.855055 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68069.515186 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79400 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70688.884373 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70688.681162 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67415.035993 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 68081.895719 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 68081.883259 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73666.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71479.855055 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68069.515186 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79400 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70688.884373 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70688.681162 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67415.035993 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 68081.895719 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 68081.883259 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63679.006872 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184008.735441 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193715.298552 # average ReadReq mshr uncacheable latency |