diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
commit | 74553c7d3fc5430752c0c08f2b319a99fb7ed632 (patch) | |
tree | 79b2a309fff0edaf1ef3e9aa62656904c3351650 /tests/quick/fs/10.linux-boot/ref/arm/linux | |
parent | 3bc4ecdcb4785a976a1c3fd463bf7052b8415d8b (diff) | |
download | gem5-74553c7d3fc5430752c0c08f2b319a99fb7ed632.tar.xz |
stats: Update the stats to reflect bus and memory changes
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux')
5 files changed, 2760 insertions, 1653 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 9a52baa4f..57671b2bd 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.912097 # Nu sim_ticks 912096763500 # Number of ticks simulated final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1025890 # Simulator instruction rate (inst/s) -host_op_rate 1320831 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15183699019 # Simulator tick rate (ticks/s) -host_mem_usage 392232 # Number of bytes of host memory used -host_seconds 60.07 # Real time elapsed on the host +host_inst_rate 749434 # Simulator instruction rate (inst/s) +host_op_rate 964895 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11092016800 # Simulator tick rate (ticks/s) +host_mem_usage 399496 # Number of bytes of host memory used +host_seconds 82.23 # Real time elapsed on the host sim_insts 61625970 # Number of instructions simulated sim_ops 79343340 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory @@ -188,6 +188,9 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access @@ -227,6 +230,9 @@ system.realview.nvmem.bw_inst_read::total 75 # I system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 64986577 # Throughput (bytes/s) +system.membus.data_through_bus 59274047 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.l2c.replacements 70658 # number of replacements system.l2c.tagsinuse 51560.149653 # Cycle average of tags in use system.l2c.total_refs 1623339 # Total number of references to valid blocks. @@ -409,6 +415,11 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.toL2Bus.throughput 154009014 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 140471123 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.iobus.throughput 45730949 # Throughput (bytes/s) +system.iobus.data_through_bus 41711051 # Total data (bytes) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 7975768 # DTB read hits diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 9271f187d..979b75345 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu sim_ticks 2332810264000 # Number of ticks simulated final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1712706 # Simulator instruction rate (inst/s) -host_op_rate 2202434 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66139785958 # Simulator tick rate (ticks/s) -host_mem_usage 391204 # Number of bytes of host memory used -host_seconds 35.27 # Real time elapsed on the host +host_inst_rate 692273 # Simulator instruction rate (inst/s) +host_op_rate 890221 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26733610702 # Simulator tick rate (ticks/s) +host_mem_usage 396420 # Number of bytes of host memory used +host_seconds 87.26 # Real time elapsed on the host sim_insts 60408639 # Number of instructions simulated sim_ops 77681819 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory @@ -171,6 +171,9 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access @@ -204,12 +207,17 @@ system.realview.nvmem.bw_inst_read::cpu.inst 9 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 55969585 # Throughput (bytes/s) +system.membus.data_through_bus 130566422 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.iobus.throughput 48895252 # Throughput (bytes/s) +system.iobus.data_through_bus 114063346 # Total data (bytes) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 14971214 # DTB read hits @@ -490,6 +498,9 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks system.cpu.dcache.writebacks::total 592643 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 59102649 # Throughput (bytes/s) +system.cpu.toL2Bus.data_through_bus 137875266 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 99dfbb1fa..7372967ce 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,147 +1,147 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.183438 # Number of seconds simulated -sim_ticks 1183437503500 # Number of ticks simulated -final_tick 1183437503500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.194897 # Number of seconds simulated +sim_ticks 1194896580500 # Number of ticks simulated +final_tick 1194896580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 462248 # Simulator instruction rate (inst/s) -host_op_rate 589061 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8900686287 # Simulator tick rate (ticks/s) -host_mem_usage 440324 # Number of bytes of host memory used -host_seconds 132.96 # Real time elapsed on the host -sim_insts 61460532 # Number of instructions simulated -sim_ops 78321652 # Number of ops (including micro ops) simulated +host_inst_rate 311660 # Simulator instruction rate (inst/s) +host_op_rate 397163 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6068013925 # Simulator tick rate (ticks/s) +host_mem_usage 403588 # Number of bytes of host memory used +host_seconds 196.92 # Real time elapsed on the host +sim_insts 61371297 # Number of instructions simulated +sim_ops 78208202 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393828 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4708980 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4819184 # Number of bytes read from this memory -system.physmem.bytes_read::total 62150116 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393828 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 716992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4119552 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7146896 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 463972 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6626100 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 255836 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2904240 # Number of bytes read from this memory +system.physmem.bytes_read::total 62155108 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 463972 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 255836 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 719808 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4136192 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory +system.physmem.bytes_written::total 7163536 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12372 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73650 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75326 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654550 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64368 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821204 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43859107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 332783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3979069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 273072 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4072191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52516602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 332783 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 273072 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 605855 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3481005 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14365 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2543729 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6039099 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3481005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43859107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 332783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3993434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 273072 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6615920 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58555700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654550 # Total number of read requests seen -system.physmem.writeReqs 821204 # Total number of write requests seen -system.physmem.cpureqs 235817 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 425891200 # Total number of bytes read from memory -system.physmem.bytesWritten 52557056 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62150116 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7146896 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 97 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 11788 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 422295 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 415695 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 415259 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 415928 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 415873 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 415149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 415167 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 415977 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 415766 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 415145 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 415183 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 415709 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 415657 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 415044 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 414930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 415676 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51328 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50890 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51482 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51387 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50754 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50751 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51440 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51875 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51227 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51302 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51806 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51729 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51213 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51075 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51789 # Track writes on a per bank basis +system.physmem.num_reads::cpu0.inst 13468 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 103605 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4079 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 45405 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654628 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64628 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory +system.physmem.num_writes::total 821464 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43438497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 388295 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 5545333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 214107 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2430537 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52017144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 388295 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 214107 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 602402 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3461548 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 2533528 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5995110 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3461548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43438497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 388295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 8078862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 214107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2430570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58012254 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654628 # Total number of read requests seen +system.physmem.writeReqs 821464 # Total number of write requests seen +system.physmem.cpureqs 235013 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 425896192 # Total number of bytes read from memory +system.physmem.bytesWritten 52573696 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62155108 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7163536 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 139 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 10646 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 415731 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 415559 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 414958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 415336 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 422399 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 415419 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 415520 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 415298 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 415351 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 415631 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 415270 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 414902 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 415547 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 416079 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 415762 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 415727 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50036 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 49924 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51324 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51581 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51646 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51464 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51327 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51592 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51318 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51082 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51567 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51872 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51738 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51694 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1183433014000 # Total gap between requests +system.physmem.totGap 1194892168500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6825 # Categorize read packet sizes system.physmem.readPktSize::3 6488064 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159661 # Categorize read packet sizes +system.physmem.readPktSize::6 159739 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 64368 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 571102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 408461 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 415701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1537889 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1165282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1169319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1141412 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 29559 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 48416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 68998 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 48154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 5894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 5718 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5372 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 81 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64628 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 581008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 419779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 439715 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1589810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1189300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1185139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1157962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 13029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 10446 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 15424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 15138 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 4570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 4445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 4046 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 75 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -156,59 +156,336 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 147040385750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 189361608250 # Sum of mem lat for all requests -system.physmem.totBusLat 33272265000 # Total cycles spent in databus access -system.physmem.totBankLat 9048957500 # Total cycles spent in bank access -system.physmem.avgQLat 22096.54 # Average queueing delay per request -system.physmem.avgBankLat 1359.83 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 34609 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 13824.665723 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 735.190153 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 27804.066503 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-127 7914 22.87% 22.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-191 4043 11.68% 34.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-255 2692 7.78% 42.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-319 1927 5.57% 47.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-383 1400 4.05% 51.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-447 1123 3.24% 55.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-511 878 2.54% 57.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-575 878 2.54% 60.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-639 638 1.84% 62.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-703 541 1.56% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-767 480 1.39% 65.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-831 476 1.38% 66.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-895 262 0.76% 67.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-959 253 0.73% 67.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-1023 191 0.55% 68.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1087 292 0.84% 69.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1151 145 0.42% 69.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1215 146 0.42% 70.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1279 123 0.36% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1343 107 0.31% 70.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1407 79 0.23% 71.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1471 170 0.49% 71.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1535 949 2.74% 74.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1599 246 0.71% 74.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1663 151 0.44% 75.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1727 129 0.37% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1791 98 0.28% 76.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1855 72 0.21% 76.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1919 65 0.19% 76.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1983 51 0.15% 76.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2047 51 0.15% 76.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2111 71 0.21% 76.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2175 44 0.13% 77.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2239 29 0.08% 77.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2303 19 0.05% 77.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2367 23 0.07% 77.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2431 27 0.08% 77.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2495 13 0.04% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2559 27 0.08% 77.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2623 12 0.03% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2687 9 0.03% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2751 14 0.04% 77.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2815 11 0.03% 77.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2879 12 0.03% 77.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2943 14 0.04% 77.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-3007 6 0.02% 77.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3071 7 0.02% 77.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3135 15 0.04% 77.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3199 4 0.01% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3263 7 0.02% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3327 4 0.01% 77.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3391 14 0.04% 77.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3455 11 0.03% 77.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3519 7 0.02% 77.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3583 7 0.02% 77.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3647 11 0.03% 77.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3711 8 0.02% 78.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3775 5 0.01% 78.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3839 12 0.03% 78.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3903 4 0.01% 78.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3967 5 0.01% 78.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-4031 8 0.02% 78.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4095 6 0.02% 78.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4159 41 0.12% 78.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4223 3 0.01% 78.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4287 4 0.01% 78.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4351 5 0.01% 78.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4415 4 0.01% 78.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4479 5 0.01% 78.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4543 4 0.01% 78.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4607 5 0.01% 78.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4671 9 0.03% 78.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4735 4 0.01% 78.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4799 2 0.01% 78.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4863 4 0.01% 78.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4927 4 0.01% 78.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4991 1 0.00% 78.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5055 5 0.01% 78.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5119 3 0.01% 78.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5183 10 0.03% 78.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5247 3 0.01% 78.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5375 2 0.01% 78.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5439 5 0.01% 78.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5503 2 0.01% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5631 5 0.01% 78.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5695 3 0.01% 78.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5759 6 0.02% 78.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5823 2 0.01% 78.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5887 3 0.01% 78.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5951 5 0.01% 78.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-6015 4 0.01% 78.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6079 3 0.01% 78.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6143 3 0.01% 78.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6207 170 0.49% 79.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6271 3 0.01% 79.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6335 1 0.00% 79.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6399 4 0.01% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6463 4 0.01% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6591 1 0.00% 79.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6655 2 0.01% 79.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6719 5 0.01% 79.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6783 3 0.01% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6847 21 0.06% 79.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6911 3 0.01% 79.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6975 1 0.00% 79.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7103 1 0.00% 79.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7167 1 0.00% 79.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7231 4 0.01% 79.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7295 3 0.01% 79.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7359 2 0.01% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7423 1 0.00% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7487 3 0.01% 79.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7551 4 0.01% 79.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7615 3 0.01% 79.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7679 3 0.01% 79.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7743 4 0.01% 79.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7807 2 0.01% 79.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7935 5 0.01% 79.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7999 2 0.01% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8063 2 0.01% 79.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8127 7 0.02% 79.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8191 4 0.01% 79.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8255 318 0.92% 80.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8511 1 0.00% 80.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8767 1 0.00% 80.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-9023 2 0.01% 80.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9279 4 0.01% 80.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9471 1 0.00% 80.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9535 2 0.01% 80.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9663 1 0.00% 80.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9791 2 0.01% 80.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10303 17 0.05% 80.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10559 2 0.01% 80.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10815 1 0.00% 80.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11071 2 0.01% 80.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11263 1 0.00% 80.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11327 2 0.01% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11583 2 0.01% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12095 1 0.00% 80.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12799 1 0.00% 80.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13375 1 0.00% 80.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13631 2 0.01% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13887 1 0.00% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14399 1 0.00% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15423 2 0.01% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15679 1 0.00% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15935 1 0.00% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16191 1 0.00% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16447 1 0.00% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16767 1 0.00% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17215 1 0.00% 80.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17280-17343 1 0.00% 80.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17471 2 0.01% 80.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17791 1 0.00% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17919 1 0.00% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18239 1 0.00% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18495 2 0.01% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19263 1 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20543 13 0.04% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20799 1 0.00% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-21055 1 0.00% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21567 2 0.01% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21823 1 0.00% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22591 3 0.01% 80.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22847 1 0.00% 80.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23103 2 0.01% 80.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23615 3 0.01% 80.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23871 1 0.00% 80.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24127 1 0.00% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24128-24191 1 0.00% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24383 1 0.00% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24639 1 0.00% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24895 2 0.01% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25216-25279 1 0.00% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25663 3 0.01% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25919 2 0.01% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26687 1 0.00% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26943 3 0.01% 80.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27199 1 0.00% 80.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27455 2 0.01% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27711 1 0.00% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27840-27903 1 0.00% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27967 1 0.00% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-28031 1 0.00% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28479 1 0.00% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28735 2 0.01% 80.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28991 2 0.01% 80.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29247 1 0.00% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29567 1 0.00% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29759 4 0.01% 80.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-30015 5 0.01% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30271 1 0.00% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30527 1 0.00% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30783 1 0.00% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31040-31103 1 0.00% 80.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31423 1 0.00% 80.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31680-31743 1 0.00% 80.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31807 2 0.01% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32063 2 0.01% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32319 1 0.00% 80.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32831 6 0.02% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33343 1 0.00% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33472-33535 5 0.01% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33599 49 0.14% 80.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33663 2 0.01% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34879 1 0.00% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35135 1 0.00% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35903 1 0.00% 80.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38079 1 0.00% 80.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38463 1 0.00% 80.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39487 1 0.00% 80.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-41023 1 0.00% 80.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42047 2 0.01% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42112-42175 1 0.00% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43071 1 0.00% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43327 1 0.00% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46911 1 0.00% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48447 1 0.00% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48576-48639 1 0.00% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53311 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53504-53567 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53760-53823 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54016-54079 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54272-54335 1 0.00% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54528-54591 1 0.00% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55296-55359 1 0.00% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55744-55807 1 0.00% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55808-55871 2 0.01% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56320-56383 3 0.01% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56576-56639 1 0.00% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58880-58943 1 0.00% 80.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59520-59583 1 0.00% 80.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60416-60479 1 0.00% 80.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60608-60671 1 0.00% 80.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62464-62527 1 0.00% 80.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63488-63551 1 0.00% 80.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65087 7 0.02% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65152-65215 2 0.01% 81.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65216-65279 1 0.00% 81.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65344-65407 1 0.00% 81.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65535 6 0.02% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65599 6201 17.92% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65920-65983 1 0.00% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::66304-66367 1 0.00% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74240-74303 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::76480-76543 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::76864-76927 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::84416-84479 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::86848-86911 1 0.00% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::87040-87103 1 0.00% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::87424-87487 1 0.00% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::97024-97087 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::97472-97535 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::97600-97663 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::99520-99583 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::109120-109183 1 0.00% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::110080-110143 1 0.00% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::111168-111231 1 0.00% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::114496-114559 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::120896-120959 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::121152-121215 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::121728-121791 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::122112-122175 1 0.00% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129856-129919 1 0.00% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130112-130175 1 0.00% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131135 336 0.97% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::136576-136639 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196032-196095 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196608-196671 2 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 34609 # Bytes accessed per row activation +system.physmem.totQLat 134116991750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 175932036750 # Sum of mem lat for all requests +system.physmem.totBusLat 33272445000 # Total cycles spent in databus access +system.physmem.totBankLat 8542600000 # Total cycles spent in bank access +system.physmem.avgQLat 20154.36 # Average queueing delay per request +system.physmem.avgBankLat 1283.73 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28456.37 # Average memory access latency -system.physmem.avgRdBW 359.88 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 44.41 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 52.52 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.04 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 26438.10 # Average memory access latency +system.physmem.avgRdBW 356.43 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 44.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 52.02 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.16 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 11.75 # Average write queue length over time -system.physmem.readRowHits 6612404 # Number of row buffer hits during reads -system.physmem.writeRowHits 800418 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.47 # Row buffer hit rate for writes -system.physmem.avgGap 158302.83 # Average gap between requests +system.physmem.busUtil 3.13 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 12.03 # Average write queue length over time +system.physmem.readRowHits 6636609 # Number of row buffer hits during reads +system.physmem.writeRowHits 804716 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.96 # Row buffer hit rate for writes +system.physmem.avgGap 159828.45 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -219,245 +496,306 @@ system.realview.nvmem.num_reads::cpu0.inst 5 # system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 69541 # number of replacements -system.l2c.tagsinuse 53035.489918 # Cycle average of tags in use -system.l2c.total_refs 1672596 # Total number of references to valid blocks. -system.l2c.sampled_refs 134740 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.413507 # Average number of references to valid blocks. +system.membus.throughput 60028731 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703147 # Transaction distribution +system.membus.trans_dist::ReadResp 7703147 # Transaction distribution +system.membus.trans_dist::WriteReq 767201 # Transaction distribution +system.membus.trans_dist::WriteResp 767201 # Transaction distribution +system.membus.trans_dist::Writeback 64628 # Transaction distribution +system.membus.trans_dist::UpgradeReq 27727 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 16403 # Transaction distribution +system.membus.trans_dist::UpgradeResp 10646 # Transaction distribution +system.membus.trans_dist::ReadExReq 137752 # Transaction distribution +system.membus.trans_dist::ReadExResp 137298 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382564 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966658 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8856 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4359022 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382564 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 14942786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 8856 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 17335150 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389882 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17414132 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17712 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19823614 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2389882 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 69318644 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 17712 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 71728126 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71728126 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1224802500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 9206920000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.8 # Layer utilization (%) +system.membus.reqLayer3.occupancy 7965000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 2500 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer6.occupancy 777000 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 5076821641 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.respLayer2.occupancy 14663419999 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.2 # Layer utilization (%) +system.l2c.replacements 69621 # number of replacements +system.l2c.tagsinuse 53152.412760 # Cycle average of tags in use +system.l2c.total_refs 1651309 # Total number of references to valid blocks. +system.l2c.sampled_refs 134782 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.251703 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40180.165903 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000406 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001420 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3726.817906 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4242.402809 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.742182 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2823.857423 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2059.501869 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.613101 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 40039.064508 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 2.667880 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.001518 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4643.192238 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 5788.281913 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.001659 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 1923.389950 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 755.813095 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.610948 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056867 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.064734 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.043089 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.031426 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.809257 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 3941 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1769 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 419774 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 205645 # 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number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109374 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 3941 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1769 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 419774 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 262542 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5809 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2015 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 464124 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 196082 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356056 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 3941 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1769 # number of overall hits -system.l2c.overall_hits::cpu0.inst 419774 # number of overall hits -system.l2c.overall_hits::cpu0.data 262542 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5809 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2015 # number of overall hits -system.l2c.overall_hits::cpu1.inst 464124 # number of overall hits -system.l2c.overall_hits::cpu1.data 196082 # number of overall hits -system.l2c.overall_hits::total 1356056 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses +system.l2c.occ_percent::cpu0.inst 0.070849 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.088322 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.029349 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.011533 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.811041 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 4524 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1439 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 483114 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 241880 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 3782 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1868 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 372301 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 110577 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1219485 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 576235 # number of Writeback hits +system.l2c.Writeback_hits::total 576235 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1306 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 431 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1737 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 257 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 99 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 97500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 401430000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 5570734562 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 76250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 233821750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2388981363 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 8595486925 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 340227750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12648650244 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4863250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154086171248 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167079912492 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16271278232 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486203500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16757481732 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 340227750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28919928476 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4863250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154572374748 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183837394224 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001388 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013950 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038621 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010609 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016805 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.018070 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.753212 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.886459 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.808869 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.599064 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.827526 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.706996 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.592032 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.495550 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.557393 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001388 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013950 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.254314 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010609 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.229619 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.108651 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001388 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013950 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.254314 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010609 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.229619 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.108651 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 86375 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58731.528895 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 58235.386333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58572.582665 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68885.978836 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 59348.458135 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10009.778726 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10031.009510 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.497347 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10021.825521 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10038.892632 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10031.263097 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 52609.097926 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50644.309836 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 51981.966994 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86375 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58731.528895 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53130.515613 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58572.582665 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51385.888946 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 53001.306767 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86375 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58731.528895 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53130.515613 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58572.582665 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51385.888946 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 53001.306767 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -639,28 +977,237 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.toL2Bus.throughput 118409228 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2504917 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2504917 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767201 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767201 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 576235 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 27028 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 16759 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 43787 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 262464 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 262464 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 993919 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2951089 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 5837 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 14921 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 753559 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 2879854 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 6195 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 11995 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 7617369 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 31383352 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 53719796 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 5764 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 18112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 24083148 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 27940806 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 7476 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 15128 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 137173582 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 137173582 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4313200 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4765991701 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2214801410 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 2446229482 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 10393499 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 1696938433 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 2203617971 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 4326998 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 8213499 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 45438572 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7671400 # Transaction distribution +system.iobus.trans_dist::ReadResp 7671400 # Transaction distribution +system.iobus.trans_dist::WriteReq 7946 # Transaction distribution +system.iobus.trans_dist::WriteResp 7946 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8062 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382564 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 8062 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 15358692 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16124 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389882 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 16124 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 54294394 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 54294394 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 4037000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 376000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374618000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) +system.iobus.respLayer1.occupancy 12976128000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7074446 # DTB read hits -system.cpu0.dtb.read_misses 3765 # DTB read misses -system.cpu0.dtb.write_hits 5659669 # DTB write hits -system.cpu0.dtb.write_misses 803 # DTB write misses +system.cpu0.dtb.read_hits 9653493 # DTB read hits +system.cpu0.dtb.read_misses 3738 # DTB read misses +system.cpu0.dtb.write_hits 7597651 # DTB write hits +system.cpu0.dtb.write_misses 1585 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1806 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7078211 # DTB read accesses -system.cpu0.dtb.write_accesses 5660472 # DTB write accesses +system.cpu0.dtb.read_accesses 9657231 # DTB read accesses +system.cpu0.dtb.write_accesses 7599236 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12734115 # DTB hits -system.cpu0.dtb.misses 4568 # DTB misses -system.cpu0.dtb.accesses 12738683 # DTB accesses -system.cpu0.itb.inst_hits 29576941 # ITB inst hits +system.cpu0.dtb.hits 17251144 # DTB hits +system.cpu0.dtb.misses 5323 # DTB misses +system.cpu0.dtb.accesses 17256467 # DTB accesses +system.cpu0.itb.inst_hits 43299111 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -677,79 +1224,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29579146 # ITB inst accesses -system.cpu0.itb.hits 29576941 # DTB hits +system.cpu0.itb.inst_accesses 43301316 # ITB inst accesses +system.cpu0.itb.hits 43299111 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29579146 # DTB accesses -system.cpu0.numCycles 2366875007 # number of cpu cycles simulated +system.cpu0.itb.accesses 43301316 # DTB accesses +system.cpu0.numCycles 2389793161 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28878978 # Number of instructions committed -system.cpu0.committedOps 37226861 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33113061 # Number of integer alu accesses +system.cpu0.committedInsts 42572187 # Number of instructions committed +system.cpu0.committedOps 53304847 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 48061724 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241874 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4373945 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33113061 # number of integer instructions +system.cpu0.num_func_calls 1403541 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5582883 # number of instructions that are conditional controls +system.cpu0.num_int_insts 48061724 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 190134215 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36237784 # number of times the integer registers were written +system.cpu0.num_int_register_reads 272457591 # number of times the integer registers were read +system.cpu0.num_int_register_writes 52272439 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13402466 # number of memory refs -system.cpu0.num_load_insts 7412077 # Number of load instructions -system.cpu0.num_store_insts 5990389 # Number of store instructions -system.cpu0.num_idle_cycles 2224972760.370120 # Number of idle cycles -system.cpu0.num_busy_cycles 141902246.629880 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059953 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940047 # Percentage of idle cycles +system.cpu0.num_mem_refs 18020656 # number of memory refs +system.cpu0.num_load_insts 10037354 # Number of load instructions +system.cpu0.num_store_insts 7983302 # Number of store instructions +system.cpu0.num_idle_cycles 2150335736.878201 # Number of idle cycles +system.cpu0.num_busy_cycles 239457424.121800 # Number of busy cycles +system.cpu0.not_idle_fraction 0.100200 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.899800 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46700 # number of quiesce instructions executed -system.cpu0.icache.replacements 425548 # number of replacements -system.cpu0.icache.tagsinuse 509.590371 # Cycle average of tags in use -system.cpu0.icache.total_refs 29150863 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 426060 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 68.419619 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 75070085000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.590371 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995294 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995294 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29150863 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29150863 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29150863 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29150863 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29150863 # number of overall hits -system.cpu0.icache.overall_hits::total 29150863 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 426061 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 426061 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 426061 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 426061 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 426061 # number of overall misses -system.cpu0.icache.overall_misses::total 426061 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5812849500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5812849500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5812849500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5812849500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5812849500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5812849500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29576924 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29576924 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29576924 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29576924 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29576924 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29576924 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014405 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014405 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014405 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014405 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014405 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014405 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13643.233011 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13643.233011 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13643.233011 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13643.233011 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13643.233011 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13643.233011 # average overall miss latency +system.cpu0.kern.inst.quiesce 51313 # number of quiesce instructions executed +system.cpu0.icache.replacements 490180 # number of replacements +system.cpu0.icache.tagsinuse 509.396236 # Cycle average of tags in use +system.cpu0.icache.total_refs 42808401 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 490692 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 87.240878 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 76020026000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.396236 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.994915 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.994915 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 42808401 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 42808401 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 42808401 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 42808401 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 42808401 # number of overall hits +system.cpu0.icache.overall_hits::total 42808401 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 490693 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 490693 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 490693 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 490693 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 490693 # number of overall misses +system.cpu0.icache.overall_misses::total 490693 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6812744000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6812744000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6812744000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6812744000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6812744000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6812744000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 43299094 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 43299094 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 43299094 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 43299094 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 43299094 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 43299094 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011333 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011333 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011333 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011333 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011333 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011333 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13883.923349 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13883.923349 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13883.923349 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13883.923349 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13883.923349 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13883.923349 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -758,120 +1305,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # 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number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4960727500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 299599000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 299599000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 299599000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 299599000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014405 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014405 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014405 # 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average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11883.831826 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11883.831826 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11883.831826 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11883.831826 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11883.831826 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # 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number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 16073018 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028046 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.028046 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026485 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.026485 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059581 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059581 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044318 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044318 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027398 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027398 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027398 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.027398 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14678.798579 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14678.798579 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42511.318555 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42511.318555 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9995.664011 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9995.664011 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5462.096555 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5462.096555 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25846.706875 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25846.706875 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25846.706875 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 25846.706875 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -880,66 +1427,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 306255 # number of writebacks -system.cpu0.dcache.writebacks::total 306255 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227474 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 227474 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141720 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141720 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9335 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9335 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7498 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7498 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369194 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 369194 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 369194 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 369194 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2686390000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2686390000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3877797500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3877797500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69967000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69967000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29358500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29358500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 376588 # number of writebacks +system.cpu0.dcache.writebacks::total 376588 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263671 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 263671 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176701 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 176701 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9917 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9917 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7370 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7370 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 440372 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 440372 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 440372 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 440372 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3343027009 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3343027009 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7158388504 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7158388504 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79292501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79292501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25539500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25539500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6564187500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6564187500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6564187500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6564187500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13562288000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13562288000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128633000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128633000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14690921000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14690921000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033295 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033295 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025785 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025785 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059350 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059350 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047695 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047695 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029947 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029947 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029947 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029947 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11809.657367 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11809.657367 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27362.387101 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27362.387101 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7495.125870 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7495.125870 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3915.510803 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3915.510803 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10501415513 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10501415513 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10501415513 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10501415513 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13765210500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13765210500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807067504 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807067504 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39572278004 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39572278004 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028046 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028046 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026485 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026485 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059581 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059581 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044294 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044294 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027398 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027398 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12678.781546 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12678.781546 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40511.307259 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40511.307259 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7995.613694 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7995.613694 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3465.332429 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3465.332429 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17779.778382 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17779.778382 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17779.778382 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17779.778382 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23846.692144 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23846.692144 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23846.692144 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23846.692144 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -949,26 +1496,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8312224 # DTB read hits -system.cpu1.dtb.read_misses 3649 # DTB read misses -system.cpu1.dtb.write_hits 5828610 # DTB write hits -system.cpu1.dtb.write_misses 1432 # DTB write misses +system.cpu1.dtb.read_hits 5706432 # DTB read hits +system.cpu1.dtb.read_misses 3576 # DTB read misses +system.cpu1.dtb.write_hits 3873109 # DTB write hits +system.cpu1.dtb.write_misses 645 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1964 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8315873 # DTB read accesses -system.cpu1.dtb.write_accesses 5830042 # DTB write accesses +system.cpu1.dtb.read_accesses 5710008 # DTB read accesses +system.cpu1.dtb.write_accesses 3873754 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14140834 # DTB hits -system.cpu1.dtb.misses 5081 # DTB misses -system.cpu1.dtb.accesses 14145915 # DTB accesses -system.cpu1.itb.inst_hits 33192056 # ITB inst hits +system.cpu1.dtb.hits 9579541 # DTB hits +system.cpu1.dtb.misses 4221 # DTB misses +system.cpu1.dtb.accesses 9583762 # DTB accesses +system.cpu1.itb.inst_hits 19379683 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -985,79 +1532,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33194227 # ITB inst accesses -system.cpu1.itb.hits 33192056 # DTB hits +system.cpu1.itb.inst_accesses 19381854 # ITB inst accesses +system.cpu1.itb.hits 19379683 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33194227 # DTB accesses -system.cpu1.numCycles 2365415230 # number of cpu cycles simulated +system.cpu1.itb.accesses 19381854 # DTB accesses +system.cpu1.numCycles 2388360365 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32581554 # Number of instructions committed -system.cpu1.committedOps 41094791 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37318858 # Number of integer alu accesses +system.cpu1.committedInsts 18799110 # Number of instructions committed +system.cpu1.committedOps 24903355 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22267252 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962092 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3732954 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37318858 # number of integer instructions +system.cpu1.num_func_calls 796685 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2514656 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22267252 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 213696952 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39459665 # number of times the integer registers were written +system.cpu1.num_int_register_reads 130770555 # number of times the integer registers were read +system.cpu1.num_int_register_writes 23319815 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14678596 # number of memory refs -system.cpu1.num_load_insts 8634126 # Number of load instructions -system.cpu1.num_store_insts 6044470 # Number of store instructions -system.cpu1.num_idle_cycles 1868274479.951726 # Number of idle cycles -system.cpu1.num_busy_cycles 497140750.048273 # Number of busy cycles -system.cpu1.not_idle_fraction 0.210171 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.789829 # Percentage of idle cycles +system.cpu1.num_mem_refs 10014978 # number of memory refs +system.cpu1.num_load_insts 5983060 # Number of load instructions +system.cpu1.num_store_insts 4031918 # Number of store instructions +system.cpu1.num_idle_cycles 1968746844.438183 # Number of idle cycles +system.cpu1.num_busy_cycles 419613520.561817 # Number of busy cycles +system.cpu1.not_idle_fraction 0.175691 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.824309 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43886 # number of quiesce instructions executed -system.cpu1.icache.replacements 469169 # number of replacements -system.cpu1.icache.tagsinuse 478.729775 # Cycle average of tags in use -system.cpu1.icache.total_refs 32722371 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 469681 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 69.669352 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 92399174500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.729775 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.935019 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.935019 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 32722371 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32722371 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32722371 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32722371 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32722371 # number of overall hits -system.cpu1.icache.overall_hits::total 32722371 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 469681 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 469681 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 469681 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 469681 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 469681 # number of overall misses -system.cpu1.icache.overall_misses::total 469681 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6362521500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6362521500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6362521500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6362521500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6362521500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6362521500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33192052 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33192052 # 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average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20901.158311 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20901.158311 # average overall miss latency +system.cpu1.dcache.replacements 220463 # number of replacements +system.cpu1.dcache.tagsinuse 471.524014 # Cycle average of tags in use +system.cpu1.dcache.total_refs 8230847 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 220830 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 37.272323 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 106217593500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 471.524014 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.920945 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.920945 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 4389322 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4389322 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3673243 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3673243 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73459 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 73459 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73734 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 73734 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 8062565 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 8062565 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 8062565 # number of overall hits +system.cpu1.dcache.overall_hits::total 8062565 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 133853 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 133853 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 112791 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 112791 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9745 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9745 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9392 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 9392 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 246644 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 246644 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 246644 # number of overall misses +system.cpu1.dcache.overall_misses::total 246644 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1652691000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1652691000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3703180000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3703180000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77927500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 77927500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 48937000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 48937000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 5355871000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5355871000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5355871000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5355871000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4523175 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4523175 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3786034 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3786034 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83204 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 83204 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83126 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 83126 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 8309209 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 8309209 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 8309209 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 8309209 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029593 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.029593 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029791 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.029791 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117122 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117122 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112985 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112985 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029683 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.029683 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029683 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.029683 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12347.059834 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12347.059834 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32832.229522 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 32832.229522 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 7996.664956 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 7996.664956 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5210.498296 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5210.498296 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21714.985972 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 21714.985972 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21714.985972 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21714.985972 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1188,66 +1735,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 265193 # number of writebacks -system.cpu1.dcache.writebacks::total 265193 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170592 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170592 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149961 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 149961 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11053 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11053 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10042 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10042 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 320553 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 320553 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 320553 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 320553 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1822921500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1822921500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4235901500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4235901500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70121500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70121500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31910500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31910500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 199647 # number of writebacks +system.cpu1.dcache.writebacks::total 199647 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133853 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 133853 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112791 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 112791 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9745 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9745 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9391 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 9391 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 246644 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 246644 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 246644 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 246644 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1384976517 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1384976517 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3477593010 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3477593010 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58436502 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58436502 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30157000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30157000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6058823000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6058823000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6058823000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6058823000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168642031500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168642031500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17668268500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17668268500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186310300000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186310300000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023965 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023965 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030123 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030123 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119040 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119040 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108237 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108237 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026500 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026500 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026500 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026500 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10685.855726 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10685.855726 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28246.687472 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28246.687472 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6344.114720 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6344.114720 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3177.703645 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3177.703645 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4862569527 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4862569527 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4862569527 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4862569527 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168387734500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168387734500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531024500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531024500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168918759000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168918759000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029593 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029593 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029791 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029791 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117122 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117122 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112973 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112973 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029683 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029683 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029683 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.029683 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10346.996459 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10346.996459 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30832.185281 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30832.185281 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 5996.562545 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 5996.562545 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3211.266106 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3211.266106 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18901.158311 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18901.158311 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18901.158311 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18901.158311 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19714.931346 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19714.931346 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19714.931346 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19714.931346 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1269,10 +1816,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509664351240 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 509664351240 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509664351240 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 509664351240 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 626235127001 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 626235127001 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 626235127001 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 626235127001 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 4975edc6e..934a4cb6c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,129 +1,129 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.603674 # Number of seconds simulated -sim_ticks 2603674284000 # Number of ticks simulated -final_tick 2603674284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.615622 # Number of seconds simulated +sim_ticks 2615622384000 # Number of ticks simulated +final_tick 2615622384000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 271279 # Simulator instruction rate (inst/s) -host_op_rate 345198 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11733407598 # Simulator tick rate (ticks/s) -host_mem_usage 403640 # Number of bytes of host memory used -host_seconds 221.90 # Real time elapsed on the host -sim_insts 60197457 # Number of instructions simulated -sim_ops 76600355 # Number of ops (including micro ops) simulated +host_inst_rate 264818 # Simulator instruction rate (inst/s) +host_op_rate 336993 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11506330329 # Simulator tick rate (ticks/s) +host_mem_usage 396436 # Number of bytes of host memory used +host_seconds 227.32 # Real time elapsed on the host +sim_insts 60198587 # Number of instructions simulated +sim_ops 76605405 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9050192 # Number of bytes read from this memory -system.physmem.bytes_read::total 132439216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3677632 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093200 # Number of bytes read from this memory +system.physmem.bytes_read::total 132481840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3709760 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6693704 # Number of bytes written to this memory +system.physmem.bytes_written::total 6725832 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494095 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57463 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142115 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494761 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57965 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811481 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47119332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 270817 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3475931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50866276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 270817 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 270817 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1412478 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1158391 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2570868 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1412478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47119332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 270817 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4634322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53437145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494095 # Total number of read requests seen -system.physmem.writeReqs 811481 # Total number of write requests seen -system.physmem.cpureqs 213992 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 991622080 # Total number of bytes read from memory -system.physmem.bytesWritten 51934784 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132439216 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6693704 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 974844 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 967900 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 967764 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 968566 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 968387 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 967635 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 967737 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 968249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 968100 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 967668 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 967710 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 968007 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 968101 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 967570 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 967434 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 968087 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50753 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50356 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50308 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51002 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50784 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50139 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50212 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50710 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51142 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50724 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51058 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50650 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50587 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51214 # Track writes on a per bank basis +system.physmem.num_writes::total 811983 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46904092 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 269458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3476496 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50650216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 269458 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269458 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1418309 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1153099 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2571408 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1418309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46904092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 269458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4629595 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53221624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494761 # Total number of read requests seen +system.physmem.writeReqs 811983 # Total number of write requests seen +system.physmem.cpureqs 215166 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 991664704 # Total number of bytes read from memory +system.physmem.bytesWritten 51966912 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 132481840 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6725832 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 301 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4516 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 968108 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 967904 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 967765 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 967946 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 974722 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 968494 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 967971 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 967832 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 968523 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 968301 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 967958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 967809 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 967930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 967629 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 967885 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 967683 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 49010 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50853 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50913 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51127 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51430 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51246 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51368 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50878 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50797 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 50871 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50522 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50825 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 50676 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2603669924000 # Total gap between requests +system.physmem.totGap 2615618000000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6652 # Categorize read packet sizes system.physmem.readPktSize::3 15335424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152019 # Categorize read packet sizes +system.physmem.readPktSize::6 152685 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 57463 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1115862 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 960938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 976049 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3645924 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2755202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2757935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2724600 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 64133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 62351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 112886 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 163253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 112534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10838 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 10625 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 10165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 93 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57965 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1126555 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 973164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1018253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3775658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2831038 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2826406 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2774250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 21901 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 19136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 31670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 43534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 30921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 5697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 5598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5184 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 40 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -139,59 +139,340 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 341488215750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 436408620750 # Sum of mem lat for all requests -system.physmem.totBusLat 77468795000 # Total cycles spent in databus access -system.physmem.totBankLat 17451610000 # Total cycles spent in bank access -system.physmem.avgQLat 22040.37 # Average queueing delay per request -system.physmem.avgBankLat 1126.36 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 38567 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 27059.676926 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2495.376643 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 33105.439598 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-127 5489 14.23% 14.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-191 3331 8.64% 22.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-255 2176 5.64% 28.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-319 1697 4.40% 32.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-383 1162 3.01% 35.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-447 1046 2.71% 38.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-511 828 2.15% 40.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-575 748 1.94% 42.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-639 582 1.51% 44.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-703 509 1.32% 45.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-767 411 1.07% 46.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-831 479 1.24% 47.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-895 285 0.74% 48.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-959 248 0.64% 49.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-1023 187 0.48% 49.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1087 239 0.62% 50.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1151 141 0.37% 50.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1215 137 0.36% 51.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1279 106 0.27% 51.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1343 105 0.27% 51.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1407 92 0.24% 51.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1471 151 0.39% 52.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1535 970 2.52% 54.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1599 203 0.53% 55.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1663 135 0.35% 55.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1727 110 0.29% 55.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1791 91 0.24% 56.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1855 77 0.20% 56.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1919 66 0.17% 56.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1983 47 0.12% 56.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2047 51 0.13% 56.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2111 64 0.17% 56.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2175 37 0.10% 57.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2239 25 0.06% 57.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2303 18 0.05% 57.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2367 25 0.06% 57.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2431 26 0.07% 57.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2495 13 0.03% 57.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2559 25 0.06% 57.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2623 11 0.03% 57.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2687 14 0.04% 57.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2751 8 0.02% 57.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2815 18 0.05% 57.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2879 9 0.02% 57.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2943 8 0.02% 57.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-3007 14 0.04% 57.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3071 7 0.02% 57.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3135 17 0.04% 57.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3199 7 0.02% 57.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3263 8 0.02% 57.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3327 12 0.03% 57.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3391 12 0.03% 57.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3455 3 0.01% 57.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3519 9 0.02% 57.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3583 3 0.01% 57.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3647 6 0.02% 57.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3711 12 0.03% 57.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3775 9 0.02% 57.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3839 7 0.02% 57.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3903 9 0.02% 57.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3967 4 0.01% 57.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-4031 6 0.02% 57.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4095 9 0.02% 57.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4159 44 0.11% 58.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4223 3 0.01% 58.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4287 2 0.01% 58.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4351 3 0.01% 58.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4415 5 0.01% 58.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4479 6 0.02% 58.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4543 2 0.01% 58.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4607 5 0.01% 58.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4671 2 0.01% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4735 1 0.00% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4799 1 0.00% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4863 3 0.01% 58.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4927 7 0.02% 58.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5055 6 0.02% 58.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5119 1 0.00% 58.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5183 12 0.03% 58.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5247 1 0.00% 58.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5311 5 0.01% 58.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5375 3 0.01% 58.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5439 5 0.01% 58.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5503 7 0.02% 58.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5567 2 0.01% 58.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5631 2 0.01% 58.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5695 2 0.01% 58.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5759 6 0.02% 58.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5887 3 0.01% 58.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5951 2 0.01% 58.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-6015 3 0.01% 58.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6079 2 0.01% 58.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6143 2 0.01% 58.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6207 180 0.47% 58.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6271 1 0.00% 58.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6335 1 0.00% 58.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6399 3 0.01% 58.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6463 5 0.01% 58.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6527 2 0.01% 58.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6591 3 0.01% 58.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6655 1 0.00% 58.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6719 2 0.01% 58.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6783 1 0.00% 58.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6847 15 0.04% 58.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6911 3 0.01% 58.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6975 1 0.00% 58.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7039 2 0.01% 58.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7103 2 0.01% 58.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7295 3 0.01% 58.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7423 1 0.00% 58.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7487 2 0.01% 58.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7551 3 0.01% 58.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7615 3 0.01% 58.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7679 3 0.01% 58.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7743 11 0.03% 59.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7807 3 0.01% 59.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7871 4 0.01% 59.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7935 4 0.01% 59.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7999 3 0.01% 59.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8063 1 0.00% 59.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8127 6 0.02% 59.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8191 4 0.01% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8255 327 0.85% 59.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8511 5 0.01% 59.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8895 1 0.00% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-9023 1 0.00% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9279 3 0.01% 59.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9535 2 0.01% 59.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10303 18 0.05% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10559 1 0.00% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10815 1 0.00% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11263 1 0.00% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11327 2 0.01% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11583 2 0.01% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11647 1 0.00% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11839 1 0.00% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12095 1 0.00% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12351 3 0.01% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12607 1 0.00% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13119 1 0.00% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13631 1 0.00% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14143 1 0.00% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14399 2 0.01% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14655 2 0.01% 60.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15423 3 0.01% 60.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15743 1 0.00% 60.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15935 1 0.00% 60.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16191 2 0.01% 60.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16447 1 0.00% 60.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17471 2 0.01% 60.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17727 1 0.00% 60.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17983 1 0.00% 60.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18239 1 0.00% 60.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18495 2 0.01% 60.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19008-19071 1 0.00% 60.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19263 1 0.00% 60.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19519 3 0.01% 60.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19775 3 0.01% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-20031 1 0.00% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20287 1 0.00% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20543 2 0.01% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20799 1 0.00% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21311 1 0.00% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21567 1 0.00% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21823 2 0.01% 60.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22591 4 0.01% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22847 1 0.00% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23103 3 0.01% 60.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23615 5 0.01% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23871 1 0.00% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24127 2 0.01% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24639 1 0.00% 60.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24895 1 0.00% 60.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24960-25023 1 0.00% 60.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25663 3 0.01% 60.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25919 2 0.01% 60.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26431 1 0.00% 60.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26687 4 0.01% 60.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26943 1 0.00% 60.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27199 1 0.00% 60.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27967 1 0.00% 60.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28096-28159 1 0.00% 60.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28735 1 0.00% 60.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28991 1 0.00% 60.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29376-29439 1 0.00% 60.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29759 6 0.02% 60.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-30015 2 0.01% 60.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30527 3 0.01% 60.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30783 3 0.01% 60.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31168-31231 1 0.00% 60.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31295 2 0.01% 60.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31807 5 0.01% 60.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32063 1 0.00% 60.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32831 2 0.01% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33343 4 0.01% 60.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33599 56 0.15% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33663 1 0.00% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34111 1 0.00% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34879 1 0.00% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35903 1 0.00% 60.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37439 1 0.00% 60.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38975 1 0.00% 60.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39999 2 0.01% 60.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42303 1 0.00% 60.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42559 2 0.01% 60.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43071 1 0.00% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43583 1 0.00% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45119 1 0.00% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45631 1 0.00% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46143 1 0.00% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47423 1 0.00% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48191 1 0.00% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49215 2 0.01% 60.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49664-49727 2 0.01% 60.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50239 1 0.00% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51263 1 0.00% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52480-52543 1 0.00% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52992-53055 1 0.00% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56320-56383 3 0.01% 60.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57088-57151 1 0.00% 60.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59392-59455 1 0.00% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60416-60479 2 0.01% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61440-61503 1 0.00% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63488-63551 2 0.01% 60.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63808-63871 1 0.00% 60.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64512-64575 1 0.00% 60.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65087 19 0.05% 60.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65088-65151 6 0.02% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65152-65215 2 0.01% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65343 6 0.02% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65344-65407 6 0.02% 60.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65408-65471 14 0.04% 60.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65535 6 0.02% 60.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65599 14789 38.35% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::71360-71423 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73984-74047 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::83008-83071 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::85504-85567 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::93120-93183 1 0.00% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::97152-97215 1 0.00% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::97408-97471 1 0.00% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::100672-100735 1 0.00% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::103680-103743 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::104768-104831 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::106432-106495 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::109760-109823 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::110848-110911 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::110912-110975 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::114240-114303 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::115328-115391 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::116992-117055 1 0.00% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::120320-120383 1 0.00% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::121408-121471 1 0.00% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::121472-121535 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::124416-124479 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::127552-127615 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128640-128703 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130176-130239 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130368-130431 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130432-130495 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130496-130559 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130624-130687 1 0.00% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130688-130751 1 0.00% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130880-130943 1 0.00% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131135 328 0.85% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::136576-136639 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::161408-161471 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::190336-190399 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196032-196095 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196608-196671 2 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38567 # Bytes accessed per row activation +system.physmem.totQLat 306544443250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 400266823250 # Sum of mem lat for all requests +system.physmem.totBusLat 77472300000 # Total cycles spent in databus access +system.physmem.totBankLat 16250080000 # Total cycles spent in bank access +system.physmem.avgQLat 19784.13 # Average queueing delay per request +system.physmem.avgBankLat 1048.77 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28166.74 # Average memory access latency -system.physmem.avgRdBW 380.85 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 25832.90 # Average memory access latency +system.physmem.avgRdBW 379.13 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 19.87 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 50.65 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.13 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 12.40 # Average write queue length over time -system.physmem.readRowHits 15418728 # Number of row buffer hits during reads -system.physmem.writeRowHits 794030 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes -system.physmem.avgGap 159679.73 # Average gap between requests +system.physmem.busUtil 3.12 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 10.80 # Average write queue length over time +system.physmem.readRowHits 15469403 # Number of row buffer hits during reads +system.physmem.writeRowHits 798459 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 98.33 # Row buffer hit rate for writes +system.physmem.avgGap 160401.00 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -204,34 +485,248 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54138467 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16546589 # Transaction distribution +system.membus.trans_dist::ReadResp 16546589 # Transaction distribution +system.membus.trans_dist::WriteReq 763368 # Transaction distribution +system.membus.trans_dist::WriteResp 763368 # Transaction distribution +system.membus.trans_dist::Writeback 57965 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution +system.membus.trans_dist::ReadExReq 132246 # Transaction distribution +system.membus.trans_dist::ReadExResp 132246 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893707 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280555 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 32564555 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34951403 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16524280 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18922393 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 139207672 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 141605785 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141605785 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1206150500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 17904777500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer3.occupancy 3613000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4945376509 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 34635651750 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.iobus.throughput 47817981 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16518751 # Transaction distribution +system.iobus.trans_dist::ReadResp 16518751 # Transaction distribution +system.iobus.trans_dist::WriteReq 8166 # Transaction distribution +system.iobus.trans_dist::WriteResp 8166 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33053834 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 125073781 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 125073781 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374820000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 30670848000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14995645 # DTB read hits -system.cpu.dtb.read_misses 7332 # DTB read misses -system.cpu.dtb.write_hits 11230857 # DTB write hits -system.cpu.dtb.write_misses 2203 # DTB write misses +system.cpu.dtb.read_hits 14996055 # DTB read hits +system.cpu.dtb.read_misses 7342 # DTB read misses +system.cpu.dtb.write_hits 11230429 # DTB write hits +system.cpu.dtb.write_misses 2216 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15002977 # DTB read accesses -system.cpu.dtb.write_accesses 11233060 # DTB write accesses +system.cpu.dtb.read_accesses 15003397 # DTB read accesses +system.cpu.dtb.write_accesses 11232645 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226502 # DTB hits -system.cpu.dtb.misses 9535 # DTB misses -system.cpu.dtb.accesses 26236037 # DTB accesses -system.cpu.itb.inst_hits 61491397 # ITB inst hits +system.cpu.dtb.hits 26226484 # DTB hits +system.cpu.dtb.misses 9558 # DTB misses +system.cpu.dtb.accesses 26236042 # DTB accesses +system.cpu.itb.inst_hits 61492425 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -248,79 +743,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61495868 # ITB inst accesses -system.cpu.itb.hits 61491397 # DTB hits +system.cpu.itb.inst_accesses 61496896 # ITB inst accesses +system.cpu.itb.hits 61492425 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61495868 # DTB accesses -system.cpu.numCycles 5207348568 # number of cpu cycles simulated +system.cpu.itb.accesses 61496896 # DTB accesses +system.cpu.numCycles 5231244768 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60197457 # Number of instructions committed -system.cpu.committedOps 76600355 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68868122 # Number of integer alu accesses +system.cpu.committedInsts 60198587 # Number of instructions committed +system.cpu.committedOps 76605405 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68872209 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2139722 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7947784 # number of instructions that are conditional controls -system.cpu.num_int_insts 68868122 # number of integer instructions +system.cpu.num_func_calls 2140451 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7948368 # number of instructions that are conditional controls +system.cpu.num_int_insts 68872209 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394755172 # number of times the integer registers were read -system.cpu.num_int_register_writes 74176013 # number of times the integer registers were written +system.cpu.num_int_register_reads 394776354 # number of times the integer registers were read +system.cpu.num_int_register_writes 74181797 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27393871 # number of memory refs -system.cpu.num_load_insts 15659652 # Number of load instructions -system.cpu.num_store_insts 11734219 # Number of store instructions -system.cpu.num_idle_cycles 4579092042.576241 # Number of idle cycles -system.cpu.num_busy_cycles 628256525.423759 # Number of busy cycles -system.cpu.not_idle_fraction 0.120648 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.879352 # Percentage of idle cycles +system.cpu.num_mem_refs 27393915 # number of memory refs +system.cpu.num_load_insts 15660071 # Number of load instructions +system.cpu.num_store_insts 11733844 # Number of store instructions +system.cpu.num_idle_cycles 4582065338.612248 # Number of idle cycles +system.cpu.num_busy_cycles 649179429.387752 # Number of busy cycles +system.cpu.not_idle_fraction 0.124097 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.875903 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed -system.cpu.icache.replacements 855484 # number of replacements -system.cpu.icache.tagsinuse 510.979435 # Cycle average of tags in use -system.cpu.icache.total_refs 60635401 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 855996 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.836080 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 18713179000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.979435 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.998007 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.998007 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60635401 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60635401 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60635401 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60635401 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60635401 # number of overall hits -system.cpu.icache.overall_hits::total 60635401 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 855996 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 855996 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 855996 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 855996 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 855996 # number of overall misses -system.cpu.icache.overall_misses::total 855996 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11568776000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11568776000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11568776000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11568776000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11568776000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11568776000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61491397 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61491397 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61491397 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61491397 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61491397 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61491397 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013921 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13514.988388 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13514.988388 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13514.988388 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13514.988388 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13514.988388 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13514.988388 # average overall miss latency +system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed +system.cpu.icache.replacements 856250 # number of replacements +system.cpu.icache.tagsinuse 510.885364 # Cycle average of tags in use +system.cpu.icache.total_refs 60635663 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 856762 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 70.773054 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 19768699000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.885364 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.997823 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.997823 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 60635663 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60635663 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60635663 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60635663 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60635663 # number of overall hits +system.cpu.icache.overall_hits::total 60635663 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856762 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856762 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856762 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856762 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856762 # number of overall misses +system.cpu.icache.overall_misses::total 856762 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11759087500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11759087500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11759087500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11759087500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11759087500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11759087500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61492425 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61492425 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61492425 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61492425 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61492425 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61492425 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13725.033907 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13725.033907 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13725.033907 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13725.033907 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13725.033907 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13725.033907 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -329,174 +824,174 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855996 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 855996 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 855996 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 855996 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 855996 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 855996 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9856784000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9856784000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9856784000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9856784000 # 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average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -600,79 +1095,79 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 627296 # number of replacements -system.cpu.dcache.tagsinuse 511.912639 # Cycle average of tags in use -system.cpu.dcache.total_refs 23655010 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 627808 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.678733 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 472186000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.912639 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999829 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999829 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13195118 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13195118 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9973036 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9973036 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236277 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236277 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247678 # 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average overall miss latency +system.cpu.dcache.replacements 626656 # number of replacements +system.cpu.dcache.tagsinuse 511.879114 # Cycle average of tags in use +system.cpu.dcache.total_refs 23655617 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 627168 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.718150 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 650249000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.879114 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999764 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999764 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13195840 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13195840 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9972724 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9972724 # 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average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25719.022479 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25719.022479 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -681,54 +1176,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 596040 # number of writebacks -system.cpu.dcache.writebacks::total 596040 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368785 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368785 # 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number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18709226000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200791850500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 200791850500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027189 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027189 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024504 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024504 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046035 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046035 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12165.646650 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12165.646650 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30103.785296 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30103.785296 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11656.463778 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11656.463778 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19421.980536 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19421.980536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19421.980536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19421.980536 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 595512 # number of writebacks +system.cpu.dcache.writebacks::total 595512 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368347 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368347 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250279 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250279 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11453 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11453 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 618626 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 618626 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 618626 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 618626 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4641851500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4641851500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10031352500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10031352500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135954000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135954000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14673204000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14673204000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14673204000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14673204000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050723500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050723500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234076500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234076500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284800000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284800000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027156 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027156 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024482 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024482 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046219 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046219 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026007 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026007 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12601.844185 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12601.844185 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40080.679961 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40080.679961 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11870.601589 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11870.601589 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23719.022479 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23719.022479 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23719.022479 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23719.022479 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -736,6 +1231,38 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 53002965 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2454953 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2454953 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 595512 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2911 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2911 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247368 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1725126 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5750616 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 12461 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 27468 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7515671 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54754292 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 83665829 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 14140 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 34916 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 138469177 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 138469177 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 166564 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3009252000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1291764000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2507996500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 18739000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -750,10 +1277,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199377224257 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1199377224257 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199377224257 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1199377224257 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1470128900250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1470128900250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1470128900250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1470128900250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 1dc10f98b..35b3a08bb 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,25 +4,13 @@ sim_seconds 2.332810 # Nu sim_ticks 2332810264000 # Number of ticks simulated final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1307768 # Simulator instruction rate (inst/s) -host_op_rate 1681709 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50502250863 # Simulator tick rate (ticks/s) -host_mem_usage 395644 # Number of bytes of host memory used -host_seconds 46.19 # Real time elapsed on the host +host_inst_rate 662335 # Simulator instruction rate (inst/s) +host_op_rate 851722 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25577480180 # Simulator tick rate (ticks/s) +host_mem_usage 396424 # Number of bytes of host memory used +host_seconds 91.21 # Real time elapsed on the host sim_insts 60408639 # Number of instructions simulated sim_ops 77681819 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory @@ -196,6 +184,9 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access @@ -217,6 +208,21 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate nan # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap nan # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 55969561 # Throughput (bytes/s) +system.membus.data_through_bus 130566366 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.l2c.replacements 62242 # number of replacements system.l2c.tagsinuse 50006.300222 # Cycle average of tags in use system.l2c.total_refs 1678485 # Total number of references to valid blocks. @@ -379,6 +385,11 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.toL2Bus.throughput 59119250 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 137913994 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.iobus.throughput 48895252 # Throughput (bytes/s) +system.iobus.data_through_bus 114063346 # Total data (bytes) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 7929205 # DTB read hits |